JP2937471B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wafer-like or chip-like semiconductor integrated circuit including a circuit to be diagnosed, and a diagnostic circuit capable of diagnosing the operation of the circuit. The present invention relates to a technology that enables a diagnosis equivalent to a wafer probing test of a included circuit to be diagnosed in a non-contact state.

[Conventional technology]

The operation diagnosis of a semiconductor integrated circuit is performed by inputting diagnostic information such as a test pattern or a signal to a semiconductor integrated circuit to be diagnosed and comparing the output value from the semiconductor integrated circuit with an expected value to evaluate the function of the semiconductor integrated circuit. The wafer probing test is used to judge the quality of the data and to measure the input / output signals. This wafer probing test is a test in which a probe is mechanically brought into contact with a bonding pad or the like of a semiconductor integrated circuit in a wafer state before a chip is cut out to measure electrical characteristics. The wafer prober used is required. The wafer prober enables input / output of signals from a test apparatus and supply of power through a probe that is in contact with the bonding pad. By sequentially moving the probe, a plurality of semiconductor integrated devices on the wafer can be integrated. Circuits can be tested one after another.

As an example of a document describing a wafer probing test, there is an "LSI Handbook" issued by Ohmsha on November 30, 1984.

[Problems to be solved by the invention]

According to the study by the present inventor on the above prior art, the following problems were found.

In the wafer probing test described above, the probe is brought into contact with the bonding pad, which may damage the bonding pad. In addition, only one semiconductor integrated circuit with which the probe is currently in contact can be tested at the same time, and the probe needs to be moved each time the test is completed. It takes a long time to complete an integrated circuit test.

An object of the present invention is to provide a technique capable of completing operation diagnosis of all semiconductor integrated circuits on one wafer in a short time without damaging electrode pads.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, when a plurality of circuits to be diagnosed and a plurality of circuits for diagnosis that enable operation diagnosis of the circuit to be diagnosed are formed on the same wafer, a storage unit for storing diagnostic information; A logic circuit unit that enables the quality judgment of the circuit to be diagnosed by comparing the output result of the circuit to be diagnosed when given to the circuit with its expected value; The diagnostic circuit is formed by including an interface unit that enables an external output of a diagnostic result to the wafer in a non-contact state. In a more specific aspect, the interface unit can be formed including a light receiving unit that senses a diagnosis start instruction optically given from the outside and a light emitting unit that optically outputs the diagnosis result. At this time, in order to eliminate the need for external power supply to the semiconductor integrated circuit in the operation diagnosis, it is preferable to provide a solar cell as a power supply for the operation diagnosis on the wafer. After the operation diagnosis, the diagnostic circuit is not required except in special cases, so that it can be formed so as to be cut out as a separate chip from the circuit to be diagnosed,
In the case where the interface unit can be actively used even after the circuit to be diagnosed is cut out from the wafer,
Alternatively, if no problem is caused by the inclusion of the interface section, one diagnostic circuit and a corresponding diagnostic circuit can be formed as one semiconductor chip so as to be cut out from the wafer.

(Operation)

According to the above-described means, the interface unit included in the diagnostic circuit enables a diagnosis start instruction from the outside and external recognition of the diagnosis result in a state of relative contact with the wafer including the semiconductor integrated circuit, This enables operation diagnosis without damaging electrode pads such as bonding pads. Further, a plurality of the above-mentioned diagnostic circuits are formed corresponding to the diagnosis target circuit, thereby enabling simultaneous diagnosis of a plurality of diagnosis target circuits, which is useful for the operation diagnosis of all the semiconductor integrated circuits on one wafer. It acts to reduce the time required.

〔Example〕

 FIG. 1 shows an LSI according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a wafer. On the wafer 1, a plurality of diagnosis target circuits 3A to be diagnosed and a plurality of diagnosis circuits 3B capable of diagnosing the operation of the diagnosis target circuit 3A are formed. The diagnosis target circuit 3A and the corresponding diagnosis circuit 3B are shown in an enlarged manner in FIG.
It is formed so as to be cut out as one semiconductor chip 2 in dicing described later.

Although the diagnosis target circuit 3A is not particularly limited, it is a logic unit formed by a gate array method, and the logic unit and the diagnosis circuit 3B are connected by an aluminum wiring layer A1.

Although not particularly limited, the diagnostic circuit 3B is configured as follows.

Reference numeral 4 denotes a solar cell that is used as a power source in the operation diagnosis of the diagnostic circuit 3A, and generates a predetermined potential by receiving light having a wavelength α from the outside. The generated potential can be applied to each part of the LSI. Reference numeral 5 denotes a ROM (Read Only Memory) in which test pattern information and expected value information as diagnostic information are stored. The test pattern information can be transmitted to the diagnosis target circuit 3A. It can be transmitted to. When the test pattern information is given to the diagnosis target circuit 3A, the logic unit 6 performs the diagnosis target circuit 3A.
The operation diagnosis of the diagnosis target circuit 3A can be performed by comparing the output of the diagnosis target circuit 3A with the expected value. The logic unit 6 is coupled to an interface unit 90 that enables the external input of a diagnostic instruction signal and the external output of a diagnostic result to the wafer 1 in a non-contact state. The interface unit 90 includes, but is not limited to, a light receiving unit 7 having sensitivity to light having a wavelength β and a light emitting unit 8 capable of generating light having a wavelength γ. The light receiving unit 7 includes a light receiving element, for example, a light receiving diode 70, and a processing circuit for an output signal thereof.
Has a light emitting element, for example, a light emitting diode 80, and a driving circuit thereof. Light-receiving diode 70 and light-emitting diode 80
It can be built in the same process as LSI manufacturing. The wavelength in that case is determined by the material constituting the diode. For example, in the case of a Ga1-xAlxAs system, the wavelength can be set in the range of 750 to 905 nm by controlling the Al mixing ratio. When the light having the wavelength β is received by the light receiving unit 7, the logic unit 6 starts the operation diagnosis of the diagnosis target circuit 3A. In this operation diagnosis, a circuit to be diagnosed is
When it is determined that the operation of 3A is normal, the light emitting unit 8 is driven by the logic unit 6, and the light having the wavelength γ is emitted from the light emitting unit 8.

FIG. 2 shows a state of operation diagnosis in this embodiment.

In the figure, reference numeral 9 denotes a first light source that generates light 10 having a wavelength α, 11 denotes a second light source that generates light having a wavelength β, and 14 denotes a wavelength γ.
A camera 20 having a sensitivity to the light 13 is a dicing device for cutting the wafer 1. Above 1,
The second light sources 9 and 10 are arranged at positions where the wafer 1 can be irradiated, and the camera 14 is arranged at a position where the wafer 1 can be photographed. The photographing information by the camera 14 is taken into the dicing device 20 at the subsequent stage. The dicing apparatus 20 is formed on the wafer 1 based on the photographing information of the camera 14 and a coordinate calculator 21 for calculating the position coordinates of the light emitting diode 80 emitting light of wavelength γ on the wafer 1. And a chip cutout section for extracting only a semiconductor integrated circuit including the light-emitting diode based on the calculation result of the coordinate calculation section.

In the present embodiment, the operation diagnosis of the diagnosis target circuit 3A and the chip cutting are performed as follows.

 FIG. 3 shows a flow of the operation diagnosis.

When the first light source 9 is turned on, the light 10 having the wavelength α
Is irradiated on the wafer 1 (step ST1). This light 10
Is applied to each of the circuits 3A and 3B, whereby the respective parts are made operable. The irradiation of the light 10 having the wavelength α is
The operation is continued until the operation diagnosis of the plurality of diagnosis target circuits 3A in the wafer 1 is completed.

Next, the wafer 1 is irradiated with light 12 having a wavelength β from the second light source 11. When the light 12 is received by the light receiving diode 80, the diagnostic circuit 3B is operated, whereby the operation diagnosis of the diagnosis target circuit 3A is started (step ST).
2). In this operation diagnosis, a test pattern (for example, ABCD) is input to the diagnosis target circuit 3A from the test pattern ROM 5 in a predetermined order. Then, the value output from the diagnosis target circuit 3A is compared with the expected value (Z) in the logic unit 6 (step ST3). In this comparison, if it is determined that the output of the diagnosis target circuit 3A matches the expected value (YES), it means that the diagnosis circuit 3A is operating normally, and the logic unit at that time is determined. The light emitting diode 80 based on the diagnosis result of 6.
Is driven, whereby the wavelength γ is output from the diode 80.
Is generated (step ST4). If it is determined in the comparison by the logic section 6 that the output of the diagnostic circuit 3A does not match the expected value (NO), the light emitting element 80
Is not driven, so that the light 13 having the wavelength γ is not generated (step ST5).

The above operation diagnosis is started almost simultaneously in all the diagnostic circuits 3B in the wafer 1 by irradiating the wafer 1 with the light 10 from the first light source 9. That is, all the circuits to be diagnosed in the wafer 1
Since the diagnostic circuit 3B is provided corresponding to 3A, the wafer 1 is irradiated by the light 10 from the first light source 9 described above.
Are started individually and almost simultaneously.

When the above operation diagnosis is completed, the camera
The wafer 1 is photographed by 14, and the image information is input to the dicing device 20. As a result, in the dicing apparatus 20, the coordinate calculation unit 21 obtains the position coordinates of the light-emitting diode 80 that is turned on, and performs chip cutting based on the obtained coordinate information. Light emitting diode
The fact that 80 is lit means that the diagnosis target circuit 3B including the diode 80 is a non-defective product that normally operates, and thus only non-defective products are extracted in the dicing apparatus 20 by the chip cutting.

 According to this embodiment, the following operation and effect can be obtained.

(1) When the first light source 9 is turned on, light 10 having a wavelength α is irradiated on the wafer 1, and the light 10 is irradiated on the solar cell 4, and the potential generated by the light 10 is applied to the circuits 3A and 3B. It is supplied to each part, and thereby each part is made operable. In this state, the wafer 1 is irradiated with the light 12 having the wavelength β from the second light source 11 and is received by the light receiving diode 80, whereby the diagnostic circuit 3B is operated, whereby the operation of the diagnosis target circuit 3A is performed. Diagnosis is started. The result of the operation diagnosis can be output to the outside by the light emitting diode 80, whereby the diagnosis result can be grasped. Since the information can be optically exchanged in this manner, the operation diagnosis of the diagnosis target circuit 3A can be performed in a non-contact state with respect to the wafer 1, so that the bonding pads can be used as in the conventional wafer probing test. There is no risk of damage due to the probe, and no undesirable stress is applied to the wafer 1.

(2) All the circuits to be diagnosed on the wafer 1
A diagnosis circuit 3B and an interface unit 90 are provided corresponding to 3A, and the operation diagnosis of all the diagnosis target circuits 3A on the wafer 1 is individually performed by irradiation of the light 12 from the second light source 11, and Since the operations are started almost simultaneously, the operation diagnosis of all the diagnosis target circuits 3A in the wafer 1 can be performed in a short time.

(3) After the operation diagnosis, the wafer 1 is photographed by the camera 14 and the image information is input to the dicing device 20. In the dicing device 20, the position coordinates of the light emitting diode 80 that is turned on are obtained and obtained. Since a chip including the light emitting diode 80, that is, a non-defective chip is cut out based on the coordinate information, automation from a circuit operation diagnosis to a non-defective chip can be performed.

(4) One diagnostic circuit 3A and the corresponding diagnostic circuit
Since 3B is cut out as one semiconductor chip, the operation diagnosis of the diagnosis target circuit 3A can be performed again by using the diagnostic circuit 3B after cutting out the chip.

(5) By providing the solar cell 4 on the wafer, the probe contact for power supply at the time of diagnosis is not required, so that the above-mentioned effect (1) is more remarkable.

Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the diagnosis target circuit 3A and the diagnosis circuit 3B
Are cut out as one chip. However, if the diagnosis circuit 3B is unnecessary after the operation diagnosis, the diagnosis circuit 3B is cut out as a separate chip to reduce the chip size of the diagnosis target circuit 3A. You may make it aim.

In the above-described embodiment, the interface unit 90 is configured so that the operation diagnosis result can be optically recognized externally. However, an electron beam test technique using an electron beam (EB) as a probe may be used. According to this technique, it is possible to directly measure the wiring potential in the circuit using the potential contrast observed by the scanning electron microscope, and if this is used, the light emitting unit 8 in FIG. 1 can be omitted. can do.
Further, if an ultrasonic transducer capable of generating ultrasonic waves is provided instead of the light emitting section 8, the quality of the diagnosis target circuit 3A can be recognized based on the presence or absence of the ultrasonic output from the transducer. Even if the above-described electron beam or ultrasonic wave is used, the operation diagnosis of the circuit to be diagnosed can be performed in a non-contact state with the chip, and the same effect as in the above embodiment can be obtained.

Furthermore, in order to reduce the size of the chip, the solar cell 4 may be arranged on the circuit 3A for diagnosis or the circuit 3B for diagnosis, or the solar cell 4 may be placed on a portion that does not contribute to circuit formation, such as the edge of the chip. A battery may be formed and used as a common power supply for each circuit in the chip.

In the above description, the case where the invention made by the inventor is mainly applied to the logic LSI serving as the background has been described, but the present invention is not limited thereto.
The present invention can be applied to various LSIs such as a one-chip microcomputer including a semiconductor memory. The present invention can be applied to a circuit in which at least a plurality of circuits to be diagnosed and diagnostic circuits thereof are formed on the same wafer.

〔The invention's effect〕

The result obtained by a representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, by the interface unit included in the diagnostic circuit, a diagnostic start instruction from the outside and external recognition of the diagnostic result can be made in a specific contact state with respect to the wafer including the semiconductor integrated circuit, and thereby, the electrode pad The operation diagnosis can be performed without damage. Further, since a plurality of the diagnostic circuits are formed corresponding to the diagnosis target circuit, thereby enabling simultaneous diagnosis of the plurality of diagnosis target circuits,
The time required for operation diagnosis of all the semiconductor integrated circuits on one wafer can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the structure of a wafer on which an LSI according to an embodiment of the present invention is formed and its main part, FIG. 2 is an explanatory view of an operation diagnosis of the LSI shown in FIG. 1, and FIG. It is a flowchart of operation | movement diagnosis. 1 ... Wafer, 2 ... Chip, 3A ... Diagnosis target circuit,
3B ... Diagnostic circuit, 4 ... Solar cell, 5 ... ROM, 6 ...
... Logic section, 7... Light receiving section, 8... Light emitting section, 70... Light receiving diode, 80.

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit having a plurality of diagnostic circuits and a plurality of diagnostic circuits capable of diagnosing the operation of the diagnostic circuit are formed on the same wafer, wherein the diagnostic circuit stores diagnostic information. And a logic circuit which can determine the quality of the circuit under diagnosis by comparing the output result of the circuit under diagnosis with the expected value when the information for diagnosis is given to the circuit under diagnosis. A semiconductor integrated circuit comprising: a unit; and an interface unit configured to allow external input of a diagnosis start instruction signal and external output of a diagnosis result in a non-contact state with respect to the wafer. 2. The semiconductor integrated circuit according to claim 1, wherein the interface section includes a light receiving section for sensing a diagnosis start instruction optically given from the outside, and a light emitting section for optically outputting the diagnosis result. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein a solar cell serving as a power supply for operation diagnosis is provided on said wafer. 4. The semiconductor integrated circuit according to claim 1, wherein said diagnostic circuit and the corresponding diagnostic circuit are formed as separate chips so as to be cut out from each other. 5. A semiconductor integrated circuit, wherein one diagnostic circuit and a corresponding diagnostic circuit are cut out as one semiconductor chip from the semiconductor integrated circuit according to claim 1, 2, or 3.