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JP2938800B2 - Semiconductor device - Google Patents
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JP2938800B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2938800B2
JP2938800B2 JP8052808A JP5280896A JP2938800B2 JP 2938800 B2 JP2938800 B2 JP 2938800B2 JP 8052808 A JP8052808 A JP 8052808A JP 5280896 A JP5280896 A JP 5280896A JP 2938800 B2 JP2938800 B2 JP 2938800B2
Authority
JP
Japan
Prior art keywords
circuit board
circuit
conductor
semiconductor device
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8052808A
Other languages
Japanese (ja)
Other versions
JPH09246462A (en
Inventor
文朗 山本
弘之 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP8052808A priority Critical patent/JP2938800B2/en
Publication of JPH09246462A publication Critical patent/JPH09246462A/en
Application granted granted Critical
Publication of JP2938800B2 publication Critical patent/JP2938800B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards

Landscapes

  • Waveguides (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、通信機器、レー
ダ等の高周波機器に搭載される半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted on a high-frequency device such as a communication device and a radar.

【0002】[0002]

【従来の技術】高周波用半導体装置はマイクロ波帯以上
の高周波で使用される装置で、通信機器、レーダ等の高
周波機器に搭載されている。このように高周波の影響は
無視できないため、高周波用半導体装置は通常気密封止
のパッケージを含めた構成になっている。
2. Description of the Related Art A high-frequency semiconductor device is used at a high frequency of a microwave band or higher, and is mounted on a high-frequency device such as a communication device and a radar. As described above, since the influence of high frequency cannot be ignored, the high frequency semiconductor device usually includes a hermetically sealed package.

【0003】ここで、従来の高周波用半導体装置につい
て図4を用いて説明する。制御回路と高周波回路をパッ
ケージケースに包含した従来の半導体装置の断面図を図
4(a)に示す。2つの空間を有するパッケージケース
411の一方の空間にセラミック製高周波回路基板41
4が設置され、他方の空間にセラミック製制御回路基板
416が設置される。このパッケージケース411は蓋
413で封止される。また、高周波回路及び制御回路と
パッケージの外部とは高周波同軸コネクタ412及び制
御用コネクタ418で電気的に接続される。なお、セラ
ミック製制御回路基板416からセラミック製高周波回
路基板414へ送られる制御信号の伝送は、一般にはガ
ラス端子419に接合して行う。
Here, a conventional high frequency semiconductor device will be described with reference to FIG. FIG. 4A is a sectional view of a conventional semiconductor device including a control circuit and a high-frequency circuit in a package case. The ceramic high-frequency circuit board 41 is provided in one space of the package case 411 having two spaces.
4 is installed, and a ceramic control circuit board 416 is installed in the other space. This package case 411 is sealed with a lid 413. The high-frequency circuit and the control circuit are electrically connected to the outside of the package by a high-frequency coaxial connector 412 and a control connector 418. The control signal transmitted from the ceramic control circuit board 416 to the ceramic high-frequency circuit board 414 is generally connected to the glass terminal 419.

【0004】上記構造では、セラミック製高周波回路基
板414とセラミック製制御回路基板416は一体化さ
れておらず、そのため制御信号伝送にガラス端子419
等、後接合部品が必要となり、構造が複雑でかつ接栓接
続数も増すためコスト高になる。
In the above structure, the ceramic high-frequency circuit board 414 and the ceramic control circuit board 416 are not integrated, and therefore, the glass terminals 419 are used for transmitting control signals.
For example, post-joining parts are required, the structure is complicated, and the number of plug-in connections increases, resulting in high cost.

【0005】そこで、セラミック製高周波回路基板とセ
ラミック製制御回路基板を一体化した構造の半導体装置
もある。その構造の断面図を図4(b)に示す。この構
造はパッケージケース421と高周波複合回路基板42
4が接合され、蓋423で封止される。また、パッケー
ジ外部との電気的接続は高周波同軸コネクタ422及び
制御用コネクタ427により接続される。ところで、高
周波複合回路基板内にはバイアホールが開けられ、この
バイアホール内に設けられた導体(以下、VIA導体と
記す)により高周波回路と制御回路は電気的に接続され
ている(以下、バイアホールによる接続部をVIAと記
す)。高周波複合回路基板424はセラミック基板と回
路導体を積層し、この積層体を同時焼成することで製作
される(以下、コ・ファイア同時焼成技術と記す)。コ
・ファイア同時焼成技術で用いられる回路導体およびV
IA導体は、一般には導電率の低いタングステンやモリ
ブデン等の高融点金属の厚膜焼結金属を用いる。また、
その表面には接続のためと腐食防止のためニッケル(N
i)、金(Au)等のメッキ処理を施される。
There is a semiconductor device having a structure in which a ceramic high-frequency circuit board and a ceramic control circuit board are integrated. FIG. 4B shows a cross-sectional view of the structure. This structure includes a package case 421 and a high-frequency composite circuit board 42.
4 are joined and sealed with a lid 423. Electrical connection to the outside of the package is made by a high-frequency coaxial connector 422 and a control connector 427. By the way, a via hole is opened in the high-frequency composite circuit board, and the high-frequency circuit and the control circuit are electrically connected by a conductor (hereinafter, referred to as a VIA conductor) provided in the via hole (hereinafter, a via hole). The connection part by a hole is described as VIA). The high-frequency composite circuit board 424 is manufactured by laminating a ceramic substrate and a circuit conductor and simultaneously firing the laminated body (hereinafter, referred to as a co-fire simultaneous firing technique). Circuit conductor and V used in co-fire co-firing technology
As the IA conductor, a thick film sintered metal of a high melting point metal such as tungsten or molybdenum having low conductivity is generally used. Also,
Nickel (N
i), a plating process of gold (Au) or the like is performed.

【0006】[0006]

【発明が解決しようとする課題】ところで、上記した構
造の半導体装置は、高周波の特徴として表皮効果がある
ため、高周波電流のほとんどはこの導電率の低い厚膜層
を流れてしまう。その結果高周波損失が増加し、高周波
性能が劣化してしまう。また、高周波複合回路基板42
4とパッケージケース421との接合は一般的には銀ろ
う材を用いて行う。この厚膜層には機械的な緩衝効果は
ほとんど期待できないため、時として半導体装置自体の
発熱により、高周波複合回路基板424が接合したパッ
ケージケース421との熱膨張差のため割れてしまう問
題がある。
Since the semiconductor device having the above structure has a skin effect as a characteristic of high frequency, most of the high frequency current flows through the thick film layer having low conductivity. As a result, high-frequency loss increases, and high-frequency performance deteriorates. The high frequency composite circuit board 42
4 and the package case 421 are generally joined using a silver brazing material. Since a mechanical buffering effect can hardly be expected from this thick film layer, there is a problem that the semiconductor device itself sometimes breaks due to heat expansion difference from the package case 421 to which the high-frequency composite circuit board 424 is joined due to heat generation of the semiconductor device itself. .

【0007】そこで本発明は、半導体装置内の高周波損
失の低減を図り、また回路基板とパッケージケースとの
熱膨張差により割れない高信頼性の半導体装置を提供す
ることを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to reduce the high-frequency loss in a semiconductor device and to provide a highly reliable semiconductor device which is not broken by a difference in thermal expansion between a circuit board and a package case.

【0008】[0008]

【課題を解決するための手段】前述した目的を達成する
ために、セラミック製制御回路基板のみをコ・ファイア
同時焼成技術を用いて製作し、セラミック製高周波回路
はセラミック基板の一方の面に導電率の高い回路導体を
設け製作する。このセラミック製制御回路基板とセラミ
ック製高周波回路基板は接地導体を挟んで一体化接合す
る。この接地導体には延性、機械的緩衝効果の大きい銅
板または銅系合金板を用い、DBC(D-irect Bonding
Copper)技術等で接合する。DBC技術とは、セラミッ
ク等の基板と銅板または銅系合金板とを直接接合する技
術である。これは、セラミック基板と銅板または銅系合
金板とを、真空中または還元雰囲気中で同時に焼成する
ことで接続できる。この構造により回路の高周波損失が
低減でき、熱膨張差による基板等の割れが減少する。
In order to achieve the above-mentioned object, only a ceramic control circuit board is manufactured by using a co-fire co-firing technique, and a ceramic high-frequency circuit is electrically conductive on one side of the ceramic board. A circuit conductor with high efficiency is provided and manufactured. The ceramic control circuit board and the ceramic high-frequency circuit board are integrally joined with a ground conductor interposed therebetween. A copper plate or a copper-based alloy plate having a large ductile and mechanical buffer effect is used for the ground conductor, and the DBC (D-irect Bonding) is used.
(Copper) technology. The DBC technique is a technique for directly joining a substrate such as a ceramic and a copper plate or a copper-based alloy plate. This can be achieved by simultaneously firing a ceramic substrate and a copper plate or a copper-based alloy plate in a vacuum or a reducing atmosphere. With this structure, high-frequency loss of the circuit can be reduced, and cracks in the substrate and the like due to the difference in thermal expansion are reduced.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施の形態を図1
乃至図3の図示例と共に説明する。図1に本発明の一つ
の実施の形態を示す。図1(a)は斜視破断図を示し、
図1(b)はA−A’の断面図を示す。セラミック製制
御回路基板は、タングステンやモリブデン等の高融点金
属を回路導体とし、セラミック板と多層配線化した後コ
・ファイア同時焼成技術で作成する。セラミック製高周
波回路基板115とセラミック製制御回路基板116
を、伝送ピン120を通すための穴を開けた接地導体1
14でDBC技術により接合し、回路基板を一体化す
る。接地導体は機械的緩衝効果が高く、導伝率の高い銅
板等を用いる。その後セラミック製高周波回路基板11
5側表面に金等の導伝率の高い金属で高周波回路の回路
導体121を形成する。この一体化した回路基板を複合
回路基板と呼ぶことにする。パッケージケース111は
導体金属を用い、伝送ピン120はセラミック製制御回
路基板116の取付部に銀ろう付けされる。パッケージ
ケース111外部との電気的な入出力は高周波同軸コネ
クタ112、制御用同軸コネクタ119によって接続さ
れている。
FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to the examples shown in FIGS. FIG. 1 shows one embodiment of the present invention. FIG. 1A shows a perspective cutaway view,
FIG. 1B is a cross-sectional view taken along the line AA ′. The ceramic control circuit board is made by a co-fire co-firing technique after multilayer wiring with a ceramic plate using a high melting point metal such as tungsten or molybdenum as a circuit conductor. Ceramic high-frequency circuit board 115 and ceramic control circuit board 116
To the ground conductor 1 having a hole for passing the transmission pin 120 through.
At 14, bonding is performed by DBC technology, and the circuit board is integrated. As the ground conductor, a copper plate or the like having a high mechanical buffering effect and a high conductivity is used. Then the ceramic high-frequency circuit board 11
The circuit conductor 121 of the high-frequency circuit is formed of a metal having a high conductivity such as gold on the surface on the fifth side. This integrated circuit board is called a composite circuit board. The package case 111 is made of a conductive metal, and the transmission pins 120 are soldered to the mounting portion of the control circuit board 116 made of silver. Electrical input and output to and from the outside of the package case 111 are connected by a high-frequency coaxial connector 112 and a control coaxial connector 119.

【0010】上記構成により、セラミック製制御回路基
板116のみをコ・ファイア同時焼成技術で製作するの
で小型一体化できる。また、セラミック製高周波回路基
板115の回路導体121には金等、高周波回路と制御
回路の共通の接地導体114には銅板等の導電率の高い
金属が用いられるので、高周波損失を低減できる。これ
により半導体装置の外形寸法小型化と低損失性を同時に
満たすことができる。さらに、パッケージケース111
と複合回路基板との熱膨張差により発生する割れも、セ
ラミック製高周波回路基板115と制御回路基板116
の間にDBC工程の際アニールされた接地導体114が
あるので、機械的緩衝効果が高く割れることが少なくな
る。
With the above configuration, only the ceramic control circuit board 116 is manufactured by the co-firing simultaneous firing technique, so that it can be integrated in a small size. In addition, since the circuit conductor 121 of the ceramic high-frequency circuit board 115 is made of gold or the like and the ground conductor 114 common to the high-frequency circuit and the control circuit is made of a metal having high conductivity such as a copper plate, high-frequency loss can be reduced. As a result, it is possible to simultaneously reduce the external dimensions of the semiconductor device and reduce the loss. Further, the package case 111
Cracks caused by the difference in thermal expansion between the ceramic high-frequency circuit board 115 and the control circuit board 116
Since the ground conductor 114 is annealed during the DBC process, the mechanical buffering effect is high and cracking is reduced.

【0011】上記の他に、パッケージケースの外部と電
気的に接続する入出力部として同軸コネクタを用いず、
リード端子を用いた場合も適用できる。その他の実施の
形態を図2に示し、図2の(a)に斜視破断図、図2の
(b)にB−B’の断面図を示す。なお、図1に対応す
る重複部分の説明は一部省略している。
In addition to the above, a coaxial connector is not used as an input / output unit for electrically connecting to the outside of the package case.
The present invention can be applied to a case where a lead terminal is used. FIG. 2A shows another embodiment, and FIG. 2A shows a perspective cutaway view, and FIG. 2B shows a cross-sectional view taken along line BB ′. The description of the overlapping part corresponding to FIG. 1 is partially omitted.

【0012】セラミック製高周波回路基板215はパッ
ケージケース211外側まで延長され、その延長部分の
上面にセラミック壁222が積層されている。一方回路
導体221は、セラミック壁222の下部を通り抜けて
基板端部まで形成されている。高周波回路リード端子2
12は、パッケージケース211の切欠部分に露出した
回路導体221に接続されている。また制御回路につい
ても同様に、セラミック製制御回路基板216はパッケ
ージケース211外側まで延長され、その延長部分の上
面にセラミック壁223が積層されている。このパッケ
ージケース211の切欠に露出した制御基板の延長部分
に、制御回路リード端子219が接続されている。
The ceramic high-frequency circuit board 215 extends to the outside of the package case 211, and a ceramic wall 222 is laminated on the upper surface of the extension. On the other hand, the circuit conductor 221 passes through the lower portion of the ceramic wall 222 and is formed up to the substrate end. High frequency circuit lead terminal 2
Reference numeral 12 is connected to the circuit conductor 221 exposed in the cutout portion of the package case 211. Similarly, for the control circuit, the ceramic control circuit board 216 extends to the outside of the package case 211, and a ceramic wall 223 is laminated on the upper surface of the extension. A control circuit lead terminal 219 is connected to an extension of the control board exposed in the notch of the package case 211.

【0013】上記構成により、セラミック製制御回路基
板216のみをコ・ファイア同時焼成技術で製作し小型
一体化しておき、セラミック製高周波回路基板215の
回路導体221と複合回路基板の接地導体214には、
導電率の高い金属が使用できるので、半導体装置の外形
寸法小型化と高周波の低損失性を同時に満たすことがで
きる。また、パッケージケース211と複合回路基板と
の熱膨張差により発生する割れも、それらの間にDBC
工程の際アニールされた接地導体214があるので、機
械的緩衝効果が高く割れることが少なくなる。
According to the above configuration, only the ceramic control circuit board 216 is manufactured by the co-firing simultaneous firing technique and compactly integrated, and the circuit conductor 221 of the ceramic high-frequency circuit board 215 and the ground conductor 214 of the composite circuit board are provided. ,
Since a metal having high conductivity can be used, the external dimensions of the semiconductor device can be reduced and the high-frequency low-loss property can be satisfied at the same time. Further, cracks generated due to a difference in thermal expansion between the package case 211 and the composite circuit board are also caused by a DBC between them.
The presence of the ground conductor 214 that has been annealed during the process results in a high mechanical buffering effect and less cracking.

【0014】上記では、同軸コネクタまたはリード端子
のみを用いた実施形態について述べたが、同軸コネクタ
とリード端子を混合しても本発明は適用できる。また、
同軸コネクタやリード端子のみを用いた実施形態と同様
の効果が得られる。
Although the embodiment using only the coaxial connector or the lead terminal has been described above, the present invention can be applied even if the coaxial connector and the lead terminal are mixed. Also,
The same effect as the embodiment using only the coaxial connector and the lead terminal can be obtained.

【0015】本発明の他の実施の形態について図3に示
し説明する。図1、図2で述べたよように、導体金属を
用いたパッケージケースの場合について説明したが、セ
ラミックを用いたパッケージケースについても本発明は
適用できる。図3(a)に斜視破断図、図3(b)にC
−C’の断面図を示した。なお、図3では図1、図2に
対応する重複部分の説明は一部省略している。
Another embodiment of the present invention will be described with reference to FIG. As described with reference to FIGS. 1 and 2, the case of the package case using the conductive metal has been described, but the present invention is also applicable to the package case using the ceramic. FIG. 3A is a perspective cutaway view, and FIG.
A cross-sectional view of -C 'is shown. Note that, in FIG. 3, the description of the overlapping portions corresponding to FIGS. 1 and 2 is partially omitted.

【0016】複合回路基板は前述した図1、図2の実施
例と同様の構造を有しており、コ・ファイア同時焼成技
術で作成したセラミック製制御回路基板316とセラミ
ック製高周波回路基板315の間に挟むように接地導体
314が接合される。この実施形態の半導体装置は、パ
ッケージを含めた大きな装置の接地面324と接合する
構造をとる。また、パッケージ側面に設けた切欠に導体
が形成される(以下、ハーフバイアと記す)。このハー
フバイア323により接地導体314と接地面324が
電気的に接続される。
The composite circuit board has a structure similar to that of the embodiment shown in FIGS. 1 and 2 described above, and includes a ceramic control circuit board 316 and a ceramic high-frequency circuit board 315 made by co-fire simultaneous firing technology. The ground conductor 314 is joined so as to be interposed therebetween. The semiconductor device of this embodiment has a structure in which the semiconductor device is bonded to a ground plane 324 of a large device including a package. Further, a conductor is formed in a notch provided on the side surface of the package (hereinafter, referred to as a half via). The ground conductor 314 and the ground plane 324 are electrically connected by the half via 323.

【0017】上記構造により、セラミック製制御回路基
板316のみをコ・ファイア同時焼成技術で製作し小型
一体化しておき、セラミック製高周波回路基板315の
回路導体321と複合回路基板の接地導体314には、
導電率の高い金属が使用できるので、半導体装置の外形
寸法小型化と高周波の低損失性を同時に満たすことがで
きる。また、パッケージケース311と複合回路基板と
の熱膨張差により発生する割れも、それらの間にDBC
工程の際アニールされた接地導体314があるので、機
械的緩衝効果が高く割れることが少なくなる。さらに、
パッケージケース311と複合回路基板は銅板を用いた
接地導体314でDBC技術により1度ですべて一体化
することができる。
With the above structure, only the ceramic control circuit board 316 is manufactured by the co-firing simultaneous firing technique and compactly integrated, and the circuit conductor 321 of the ceramic high-frequency circuit board 315 and the ground conductor 314 of the composite circuit board are provided. ,
Since a metal having high conductivity can be used, the external dimensions of the semiconductor device can be reduced and the high-frequency low-loss property can be satisfied at the same time. In addition, cracks caused by the difference in thermal expansion between the package case 311 and the composite circuit board are also caused by DBC between them.
The presence of the ground conductor 314 that has been annealed during the process results in a high mechanical buffering effect and less cracking. further,
The package case 311 and the composite circuit board can be integrated all at once by the DBC technique using the ground conductor 314 using a copper plate.

【0018】[0018]

【発明の効果】本発明によれば、小型軽量で高周波損失
の小さな高信頼性な半導体装置を提供できる。
According to the present invention, it is possible to provide a highly reliable semiconductor device which is small and lightweight and has a small high-frequency loss.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態による半導体装置を示す
FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention;

【図2】本発明の他の実施の形態による半導体装置を示
す図
FIG. 2 is a diagram showing a semiconductor device according to another embodiment of the present invention;

【図3】本発明の他の実施の形態による半導体装置を示
す図
FIG. 3 is a diagram showing a semiconductor device according to another embodiment of the present invention;

【図4】従来例による半導体装置図FIG. 4 is a diagram of a semiconductor device according to a conventional example.

【符号の説明】[Explanation of symbols]

111,211,311,411,421 ・・・・パッケージケース 112,412,422 ・・・・・・・・高周波同軸コネクタ 113,213,313,413,423 ・・・・蓋 114,214,314 ・・・・・・・・接地導体 115,215,414,315 ・・・・・・セラミック製高周波回路
基板 116,216,416,316 ・・・・・・セラミック製制御回路基
板 117,217,317,415,425 ・・・・高周波素子 118,218,318,417,426 ・・・・制御素子 119,418,427 ・・・・・・・・制御用同軸コネクタ 120,220,320 ・・・・・・・・伝送ピン 121,221,321 ・・・・・・・・回路導体 212,312 ・・・・・・・・・・高周波回路リード端子 219,319 ・・・・・・・・・・制御回路リード端子 222,223,322 ・・・・・・・・セラミック壁 323 ・・・・・・・・・・・・ハーフバイア 424 ・・・・・・・・・・・・高周波複合回路基板 428 ・・・・・・・・・・・・VIA
111,211,311,411,421 ・ ・ ・ ・ Package case 112,412,422 ・ ・ ・ ・ ・ ・ ・ High frequency coaxial connector 113,213,313,413,423 ・ ・ ・ ・ Lid 114,214,314・ ・ ・ ・ ・ Ceramic control circuit board 117,217,317,415,425 ・ ・ ・ ・ High frequency element 118,218,318,417,426 ・ ・ ・ ・ Control element 119,418,427・ ・ ・ ・ ・ ・ ・ Circuit conductor 212,312 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ High frequency circuit lead terminal 219,319 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Control circuit lead terminal 222,223,322 ・ ・ ・ ・ ・ ・ ・ ・ Ceramic wall 323 ・ ・ ・ ・ Half via 424 ・ ・ ・ ・ High frequency composite circuit board 428 ・ ・ ・ ・ VIA

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】第1の基板と回路導体とを少なくとも1層
以上積層した第1の回路基板と、第2の基板の一方面に
回路導体を設けた第2の回路基板と、各々前記回路基板
の一面に接続し、2枚の前記回路基板の間に挟み込んだ
接地導体を具備し、前記接地導体とパッケージケースと
が少なくとも一部を接合して形成されることを特徴とす
る半導体装置。
At least one layer of a first substrate and a circuit conductor is provided.
The first circuit board laminated above and one surface of the second board
A second circuit board provided with circuit conductors, each of said circuit boards
Connected to one side and sandwiched between the two circuit boards
A ground conductor, and the ground conductor and the package case;
Is formed by joining at least a part of the semiconductor device.
【請求項2】第1の基板と回路導体とを少なくとも1層
以上積層し、得られた積層体を焼成して形成された第1
の回路基板と、第2の基板の一方面に回路導体を設けた
第2の回路基板と、各々前記回路基板の一面に接続し、
2枚の前記回路基板の間に挟み込んだ接地導体を具備
し、前記接地導体とパッケージケースとが少なくとも一
部を接合して形成されることを特徴とする半導体装置。
2. The method according to claim 1, wherein the first substrate and the circuit conductor have at least one layer.
The first layer formed by stacking the above and firing the obtained laminate is
And a circuit conductor provided on one surface of the second substrate.
A second circuit board, each connected to one side of the circuit board;
A ground conductor sandwiched between the two circuit boards is provided.
And at least one of the ground conductor and the package case is
A semiconductor device formed by joining parts .
【請求項3】前記接地導体に穴をあけ、前記第1の回路
基板と前記第2の回路基板とを接続する伝送ピンを設け
たことを特徴とする請求項1または請求項2記載の半導
体装置。
3. The first circuit according to claim 1, wherein a hole is formed in the ground conductor.
Providing a transmission pin for connecting the substrate and the second circuit board;
The semiconductor device according to claim 1 or 2, wherein:
【請求項4】第1の基板と回路導体とを少なくとも1層
以上積層した第1の回路基板と、第2の基板の一方面に
回路導体を設けた第2の回路基板と、各々前記回路基板
の接地面に接続し、2枚の前記回路基板の間に挟み込ん
だ共通の接地導体を具備し、前記接地導体に穴をあけ、
前記第1の回路基板と前記第2の回路基板とを接続する
伝送ピンを設けたことを特徴とした半導体装置。
4. The method according to claim 1, wherein the first substrate and the circuit conductor have at least one layer.
The first circuit board laminated above and one surface of the second board
A second circuit board provided with circuit conductors, each of said circuit boards
Connected to the ground plane, and sandwiched between the two circuit boards.
Having a common ground conductor, and drilling a hole in the ground conductor,
Connecting the first circuit board and the second circuit board
A semiconductor device comprising a transmission pin .
【請求項5】第1の基板と回路導体とを少なくとも1層
以上積層し、得られた積層体を焼成して形成された第1
の回路基板と、第2の基板の一方面に回路導体を設けた
第2の回路基板と、各々前記回路基板の接地面に接続
し、2枚の前記回路基板の間に挟み込んだ共通の接地導
体を具備し、前記接地導体に穴をあけ、前記第1の回路
基板と前記第2の回路基板とを接続する伝送ピンを設け
たことを特徴とした半導体装置。
5. The method according to claim 1, wherein the first substrate and the circuit conductor are formed in at least one layer.
The first layer formed by stacking the above and firing the obtained laminate is
And a circuit conductor provided on one surface of the second substrate.
A second circuit board, each connected to a ground plane of the circuit board;
And a common ground conductor sandwiched between the two circuit boards.
A hole in said ground conductor, said first circuit
Providing a transmission pin for connecting the substrate and the second circuit board;
A semiconductor device characterized by the above.
【請求項6】前記接地導体に銅材料を用いることを特徴
とする請求項1、請求項2、請求項4または請求項5記
の半導体装置。
6. The method of claim 1 which comprises using the copper material to the ground conductor, claim 2, claim 4 or claim 5 Symbol
Mounting semiconductor device.
【請求項7】前記第1、第2の回路基板にセラミック材
料を用いることを特徴とする請求項1、請求項2、請求
項4または請求項5記載の半導体装置。
7. The method of claim 1, characterized in that a ceramic material in the first, second circuit board, according to claim 2, wherein
6. The semiconductor device according to claim 4 or claim 5 .
JP8052808A 1996-03-11 1996-03-11 Semiconductor device Expired - Lifetime JP2938800B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8052808A JP2938800B2 (en) 1996-03-11 1996-03-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8052808A JP2938800B2 (en) 1996-03-11 1996-03-11 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH09246462A JPH09246462A (en) 1997-09-19
JP2938800B2 true JP2938800B2 (en) 1999-08-25

Family

ID=12925154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8052808A Expired - Lifetime JP2938800B2 (en) 1996-03-11 1996-03-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2938800B2 (en)

Also Published As

Publication number Publication date
JPH09246462A (en) 1997-09-19

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