JP2940022B2 - High reliability semiconductor integrated circuit device and design method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of ensuring high reliability against hot carrier deterioration, and a method of designing the same.

2. Description of the Related Art Degradation of hot carriers due to an increase in an electric field near a drain accompanying miniaturization and high integration of devices has become a major problem in reliability. As a method of reducing the hot carrier deterioration of the semiconductor integrated circuit device, there are attempts to change the device structure such as reducing the electric field strength of the drain junction by making the drain junction a gentle slope structure, such as an LDD structure, Attempts have been made to devise a manufacturing process to prevent generation of fixed charges and generation of interface states even when hot carriers are generated by forming the gate insulating film and injected into the oxide film. I have.

However, each of these methods has a structure of an element,
This complicates the manufacturing process and increases the manufacturing cost or lowers the manufacturing yield. Further, these methods have physical limitations, and it is impossible to rely on these methods alone to advance the miniaturization and high integration of elements.

Also, lowering the power supply voltage itself is an effective method for reducing hot carrier deterioration. However, this method also impairs the effect of shortening the delay time, which is one of the great advantages brought by miniaturization, and also reduces the noise margin of the signal, resulting in a decrease in reliability in another sense. There is also a problem in the interface due to the difference in power supply voltage with the peripheral circuit.

Problems to be Solved by the Invention As described above, reduction of hot carrier deterioration by devising an element structure and a manufacturing process involves problems such as an increase in manufacturing cost and a decrease in manufacturing yield. Furthermore, these methods have physical limitations, and there is a problem in unnecessarily pursuing these methods. In addition, in order to reduce the deterioration due to the decrease in the power supply voltage, not only the operation speed is reduced by increasing the circuit delay time, but also the reliability is reduced due to the reduction of the noise margin, and the interface with peripheral circuits is problematic.

The present invention has been made in order to solve such a problem, and a semiconductor integrated circuit capable of ensuring high reliability against hot carrier deterioration regardless of a change in an element structure / manufacturing process or a power supply voltage. It is an object of the present invention to provide an apparatus and a design method thereof.

Means for Solving the Problems In order to solve the above problems, the present invention relates to a CMOS semiconductor integrated circuit device, which comprises an inverter circuit and a NO.
The rise time of the input signal of the R circuit is tr [s], and the conduction coefficient of the n-channel MOSFET (μCoxW / 2 ·
L) is β [A / V ² ], and the load capacity of the next stage connected to the output is
When Co [F], the maximum value of Co / tr · β of all circuits constituting the entire apparatus is 1 × 10 ⁻² [F · V ² / s ·
A].

According to another invention, in designing a CMOS semiconductor integrated circuit device, a rise time of an input signal of an inverter circuit or a NOR circuit constituting the circuit is tr [s], and a conduction coefficient (μCoxW) of an n-channel MOSFET constituting the circuit is set. / 2 · L) to β
[A / V ² ], the load capacitance of the next stage connected to the output is Co [F]
Then, the Co / t of all the circuits that make up the entire device
At least one of the load capacitance of the next stage or β of the n-channel MOSFET constituting this circuit so that the maximum value of r · β is 1 × 10 ^-2 [F · V ² / s · A] or less. It is designed by controlling one of them.

Operation The present invention can realize a semiconductor integrated circuit device which can secure high reliability against hot carrier deterioration by the above-described configuration.

According to another aspect of the present invention, it is possible to realize a semiconductor integrated circuit device which realizes the above-described configuration by the above-described method and can ensure high reliability against hot carrier deterioration.

Embodiment An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 shows a CM constituting a part of a semiconductor integrated circuit device.
3 shows an OS inverter circuit. p-ch MOSFET4 and n-chMOS
The signal output from the preceding circuit 1 is input to the CMOS inverter circuit constituted by the FET 5, and a signal obtained by inverting this signal is output to the next circuit 2. A parasitic load capacitance 3 exists between the circuit 2 and the next stage. Normally, the load capacitance 3 is composed of a junction capacitance of the output drain of the inverter circuit, a wiring capacitance to the next-stage circuit 2, an input capacitance of the gate electrode of the next-stage circuit 2, and the like. FIG. 2 shows the relationship between the input voltage waveform 6 and the output voltage waveform 7. Hot carrier deterioration is usually more remarkable in the n-ch MOSFET than in the p-MOSFET. Therefore, focusing on the n-ch MOSFET, the relationship between the input voltage waveform 6 and the output voltage waveform 7 can be divided into three parts, two transient states and one steady state. Input waveform rising section 8 where input voltage rises and output voltage falls, input waveform falling section 9 where input voltage falls and output voltage rises, both transistors
The stationary part 10 where no current flows in 4 and 5. In the steady part 10, deterioration does not occur because current does not flow through the transistor. When the input waveform rising section 8 is compared with the input waveform falling section 9, the output waveform is delayed compared to the switching of the input waveform due to the load capacitance 3. However, in the input waveform falling section 9, the gate voltage falls while the drain voltage is low. As a result, the deterioration of the input waveform rising portion 8 where switching occurs while the drain voltage is high becomes dominant.

Next, FIG. 3 shows the relationship between the input voltage waveform and the output voltage waveform when the load capacitance is changed. When the load capacitance Co3 is small, the output waveform 7 changes like the waveform 11. Load capacity 3
As the value increases, the waveform fades (waveform 12 → waveform 13). Therefore, the hot carrier deterioration becomes more remarkable when the load capacitance at which the gate voltage (input waveform 6) is switched while the drain voltage (output waveform 7) is high is large. Conversely, the conduction coefficient β of the n-channel MOSFET; (μCoxW / 2 ·
When L) is changed, as β decreases, the output waveform becomes dull and the deterioration becomes more remarkable. Also, when the rise time tr is changed, the shorter the rise time tr, the more the output waveform becomes distorted with respect to the rise time, and the hot carrier deterioration life τ · tr standardized by the rise time.
Becomes shorter. If this value is expressed as an equation, if the value of Co / tr · β is constant, the output waveform will be similar to the rise time of the input waveform, and the lifetime τ · tr normalized by the rise time
Is constant.

FIG. 4 conceptually shows the relationship between the lifetime τ · tr and the waveform factor Co / tr · β. Waveform factor Co / t
When r · β is sufficiently small, the output waveform can perform switching sufficiently following the input waveform, and the hot carrier deterioration life τ · tr normalized by the rise time converges to a constant value 14. Conversely, when the waveform factor is sufficiently large, the input voltage (gate voltage) completes switching while the output voltage hardly decreases, and the lifetime τ · tr also converges to a constant value 15. When the waveform factor takes an intermediate value between the two, the lifetime also has two convergence values 14,15.
Take an intermediate value of. The actual circuit operates at a position relatively close to the convergence value 14 above. FIG. 5 shows the relationship obtained experimentally using an actual inverter circuit.
This figure shows a portion 16 where the normalized hot carrier deterioration lifetime τ · tr starts to decrease as the waveform factor Co / tr · β increases. F on the vertical axis represents the frequency, but strictly speaking, can be said to be the number of times of switching per unit time. Although this result was obtained using a transistor manufactured by a specific process, the absolute value of the vertical axis τtr The relationship with the waveform factor Co / tr · β is hardly affected. From this figure, it can be seen that the waveform factors Co of all the circuits constituting the entire semiconductor integrated circuit device are
In a semiconductor integrated circuit device in which the value of / tr · β is 1 × 10 ^-2 [F · V ² / s · A] or less, high reliability against hot carrier deterioration can be ensured. Further, Co, tr, and β are adjusted so that the value of the waveform factor Co / tr · β of all the circuits constituting the entire semiconductor integrated circuit device becomes 1 × 10 ⁻² [F · V ² / s · A] or less. By doing so, it becomes possible to design a semiconductor integrated circuit that is highly reliable against hot carrier deterioration.

In addition, by setting the waveform factor of all circuits except for the output circuit to a fixed value or less, even if the output delay time cannot be guaranteed, the lifespan of malfunction due to the timing shift caused by deterioration of the internal circuit will be extended. Can be improved.
In addition, transfer gate transistors (switching transistors) whose source and drain are replaced by deterioration
Therefore, a considerable effect can be obtained by setting the waveform factor to a certain value or less only for these transistors.

Effects of the Invention As described above, according to the present invention, in a semiconductor integrated circuit device, the value of Co / tr · β of a circuit constituting the device is set to 1
High reliability against hot carrier deterioration can be obtained by setting the value to × 10 ^-2 [F · V ² / s · A] or less.

[Brief description of the drawings]

FIG. 1 is an inverter circuit diagram for explaining the present embodiment,
FIG. 2 is a diagram showing the relationship between the input voltage waveform and the output voltage waveform of the inverter circuit, FIG. 3 is a characteristic diagram showing the relationship between the input waveform and the output waveform when the load capacitance is changed, and FIG. FIG. 5 is a characteristic diagram conceptually showing the relationship, and FIG. 5 is a characteristic diagram showing the relationship between the life and the waveform factor experimentally obtained using an actual inverter circuit. Reference numeral 1 denotes a preceding circuit, 2 denotes a subsequent circuit, 3 denotes a load capacitance, 4 denotes a p-chMOS, 5 denotes an n-chMOS, 6 denotes an input voltage waveform, 7 denotes an output voltage waveform, and 8 …… Input waveform rising part, 9 …… Input voltage falling part, 10 …… Standing part, 14,15
...... Convergence value.

Claims (4)

(57) [Claims] In a CMOS semiconductor integrated circuit device, a rise time of an input signal of an inverter circuit or a NOR circuit constituting the CMOS circuit is tr [s], and an n-channel MO constituting the circuit is provided.
The conduction coefficient (μCoxW / 2 · L) of the SFET is β [A / V ² ], and the total load capacitance up to the next circuit connected to the output is Co [F].
Then, the Co / t of all the circuits that make up the entire device
A semiconductor integrated circuit device, wherein the maximum value of r · β is 1 × 10 ^-2 [F · V ² / s · A] or less. 2. The semiconductor integrated circuit device according to claim 1, wherein the target circuit is all circuits except an output circuit for an external device. 3. The semiconductor integrated circuit device according to claim 1, wherein the target circuit is only a transfer gate circuit. 4. A method for designing a CMOS semiconductor integrated circuit device, comprising:
The rise time of the input signal of the inverter circuit or the NOR circuit constituting the circuit is tr [s], the conduction coefficient (μCoxW / 2 · L) of the n-channel MOSFET constituting the circuit is β [A / V ² ],
Calculate the total load capacitance up to the next circuit connected to the output.
When Co [F], the maximum value of Co / tr · β of all circuits constituting the entire apparatus is 1 × 10 ⁻² [F · V ² / s ·
A] A method of designing a semiconductor integrated circuit device, characterized by controlling at least one of a load capacitance of a next stage and β of an n-channel MOSFET constituting this circuit so as to be as follows.