JP2940046B2 - Amplitude detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplitude detection circuit, and more particularly, to an amplitude detection circuit using a differential circuit.

[Prior Art] As shown in FIG. 3, a conventional basic circuit of this kind of amplitude detection circuit is a differential circuit composed of transistors 301 and 302 and a constant current source 315, and smoothes the output of the differential circuit. And a smoothing circuit 321 that performs the processing. In this circuit, the voltage of the input bias voltage source 312 of the differential circuit is V _B, together phase from an input signal source 313 and 314 is output 180 ° different signals. The output signal of the differential circuit is extracted from the common emitter terminal of the transistors 301 and 302, and is output to the output terminal 330 via the smoothing circuit 312.

 Next, the operation will be described.

The input signal to the input terminal 318 is V _IN1 , the input signal to the input terminal 319 is V _IN2, and the collector current of the transistor 301 is I
Assuming that c ₁ , the collector current of the transistor 302 is Ic _2, and the voltage of the common emitter of the transistors 301 and 302 is V _E , V _IN1 −V _E = v _T ln (Ic ₁ / I _s ) V _IN2 −V _E = _{v T ln (Ic 2 / I} s) ( where, v _T is the thermal voltage of the transistor, I _s is the reverse saturation current) becomes.

Then, placing the signal variation of the signal source 313 and 314 and _{V IN, V IN1 = V IN} + V since _B V _IN2 = written as -V _IN + V _B, V _IN that the following equation is obtained from the above Equation 4 _{+ V B -V E = v T} ln (Ic 1 / I s) -V IN + V B -V E = v T ln (Ic 2 / it s) when the two equations are added as the formula is obtained.

2V _B −2V _E = v _T lnIc ₁ Ic ₂ / I _S ² ... Assuming that the mutual conductance of the differential circuit is gm and the current of the constant current source 315 is 2I _O , Ic ₁ ≒ I _O + 2V _IN gm Ic ₂ ≒ I _O + 2V _IN gm (however, as I _O >> V _IN gm).

Therefore, the equation is: 2V _B −2V _E = v _T ln ｛(I _O + 2V _IN gm) (I _O −2V _IN gm) /
I _S ² ｝ = v _T ln ｛(I _O ² / I _S ² ) (1-4V _IN ² gm ² / I _o ² )｝. Here, since I _O >> V _IN gm, an equation is obtained.

2V _B −2V _E ≒ 2v _T ln (I _O / I _S ) −v _T · 4V _IN ² gm ² / I _O ² ... Gm is represented by v _T and I _O , gm = 2I _O / 4v _T = because it is I _O / 2v _T, the common emitter potential V _E can be expressed by equation.

V _E = V _IN ² / 2v _T + V _B -v _T ln (I _O / I _S ) Next, V _IN is _a sine wave of amplitude Va (V _IN = V _a sinωt)
And V _E is given by the equation:

V _E = V _a ² sin ² wt / 2V _T + V _B -v _T ln (I _O / I _S ) Therefore, the amplitude detection output V _Ea after the smoothing circuit is: Becomes Therefore, the conventional amplitude detection output is
Proportional to the square of V _a, and inversely proportional to the thermal voltage v _T of the transistor, and a DC voltage DC component is indicated by _{V B -v T ln (I O} / I S).

And Thus, the amplitude detection output when the signal amplitude V _a is small, since a very small value, it can not be said that practically,
The circuit shown in FIG. 4 is generally used for an actual amplitude detection circuit.

In this figure, the same parts as those in FIG. 3 are denoted by the same reference numerals. In the circuit of FIG.
Is composed of a resistor 304 and a capacitor 311, and a signal having passed through the smoothing circuit is input to an input terminal 323 of an operational amplifier 317. The other input terminal 324 of the operational amplifier is connected to an output terminal of an emitter follower circuit 322 including a transistor 303 whose base is connected to a bias voltage source 312 and a constant current source 316. The resistors 306 and 308 and the bias voltage source 310 are connected between the input terminal 323 of the operational amplifier 317 and the ground, and the resistors 305 and 307 are connected between the input terminal 324 and the output terminal 320.

The voltage V ₃₂₄ input to the input terminal 324 of the operational amplifier is given by the following equation.

V ₃₂₄ = V _B −v _T ln (I _O / I _S ) Now, the potential difference between the input terminals 323 and 324 of the operational amplifier is Δ
V, the resistance of the resistors 305 and 306 is R ₃₀₀ , the resistance of the resistors 307 and 308 is R ₃₀₁ , and the voltage of the bias voltage source 310 is V _BO , the output voltage V _Ea ′ of the output terminal 320 is given by the following equation. Given.

V _Ea ′ = ΔV · R ₃₀₁ / R ₃₀₀ + V _BO ... Since the difference voltage ΔV is ΔV = V _Ea −V ₃₂₄ , ΔV = V _a ² / 4v _T. , The output voltage V _Ea formulas given in 'the ^{_{V Ea' = (V a 2}} / 4V T) · (R 301 / R 300) + V BO.

[Problem to be Solved by the Invention] In a conventional amplitude detection circuit, as shown in FIG.
Including the smoothing circuit and the operational amplifier significantly increases the number of elements. Therefore, it is difficult to make an IC with the conventional amplitude detection circuit, and the IC product becomes expensive.

[Means for Solving the Problems] In an amplitude detection circuit according to the present invention, a DC bias voltage and a first signal superimposed on the DC bias voltage are input to a base, and an emitter is connected via a first constant current source. A first transistor connected to a second power supply, and a DC bias voltage superimposed on the DC bias voltage and the DC bias voltage on a base;
A second transistor having a second phase opposite to the first signal and having a collector connected to a collector of the first transistor and an emitter connected to an emitter of the first transistor; A third transistor connected to the emitter of the first transistor;
One end is connected to the base of the third transistor, the other end is connected to a DC bias voltage source that generates the DC bias voltage, and one end is connected to the base of the third transistor; A second resistor having the other end connected to the output terminal; and a second resistor connected between the first transistor collector and the first power supply and / or between a collector of the third transistor and the first power supply. There is provided current control means for controlling the ratio of the sum of the collector current of the first transistor and the collector current of the second transistor to the collector current of the third transistor to be constant.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention,
This circuit consists of transistors of almost the same size
Differential circuit 13 composed of 101 to 104 and constant current source 111
0, current mirror circuit 131 composed of transistors 105 and 106, resistors 120 and 121, transistor 107, constant current source
Emitter follower 132 composed of 113 and resistor 10
8, 109, and a smoothing capacitor 110.

Signals having phases different from each other by 180 ° from input signal sources 115 and 116 are input to the bases of transistors 101 and 102 via input terminals 117 and 118, respectively.
The emitter of 04 is connected in common and one end is connected to a constant current source 111 grounded, and the collectors of transistors 101 and 102 are connected in common to form a current mirror circuit with the collector and base of transistor 105 and transistor 105. The base of the transistor 106 is connected, and the collectors of the transistors 103 and 104 are commonly connected to the power supply 150.

The collector of the transistor 106 is connected to a constant current source 112 whose one end is grounded, the base of the transistor 107 and a smoothing capacitor 110 whose one end is connected to a power supply 150. The emitters of the transistors 105 and 106 are respectively
The power supply 150 is connected via the resistors 120 and 121.

The emitter of the transistor 107 is connected to a constant current source 113 whose one end is grounded, one end of a resistor 109 and an output terminal 119, and its collector is connected to a power supply 150.

The other end of the resistor 109 is connected to a commonly connected base of the transistors 103 and 104 and one end of the resistor 108, and the other end of the resistor 108 is connected to a bias voltage source 114.

Next, the voltage value of the bias voltage source 114 is V _B , the signal change of the signal source 115 is V _IN , and the signal change of the signal source 116 is −V
_Assuming that _IN , the common emitter potential of the transistors 101 and 102 is V _E , and the collector currents of the transistors 101 and 102 are Ic ₁ and Ic ₂ respectively, the following equations and equations are obtained.

The addition of the _{V IN + V B -V E =} v T ln (Ic 1 / I S) ... -V IN + V B -V E = v T ln (Ic 2 / I S) ... Formula and Formula, 2V _B - 2V _E = v _T ln (Ic ₁ Ic ₂ / I _S ² ) where the current of the constant current source 111 is 4I _O and the current of the constant current source 112 is 2I _{O so that} Ic ₁ + Ic ₂ = 2I _O Then, assuming that the transconductance of the transistors 101 and 102 is gm, I
c ₁ and Ic ₂ are obtained as follows.

_{Ic 1 = I O + 2gmV IN} ... Ic 2 = I O -2gmV IN ..., to organize is an expression in the equation, the common emitter potential V _E
Solving for: V _E = V _B −V _T ln ｛I _O ² −4 gm ² V _IN ² ) / I _S ² ｝ / 2 = V _B −v _T ln ｛I _O ² (1-4 gm ² V _IN ^{2) _{/ I O 2) / I S}} 2} / 2 I O " assuming _{gmV IN, V E = V B} = v T ln (I O / I S) + (4v T gm 2 V IN 2) / 2I O ^{_{2 = V B -v T ln (}} I O / I S) + (2v T gm 2 V iN 2) / I O 2 ... gm = I O / 2v T are substituted into equation V _E = V _B -v _T ln (I _O / I _S ) + V _IN ² / 2v _T.

Here, the collector current of the transistors 101 and 102 is Ic
_{Since 1} + Ic ₂ = 2I _O , the sum of the collector currents of transistors 103 and 104 (Ic ₃ and Ic ₄ respectively) is 2I _O. Further, transistors 103 and 104
Are formed in the same size, and the base and the emitter are commonly connected, so that Ic ₃ = Ic ₄ = I _O.

Therefore, the common base voltage V of the transistors 103 and 104
_BF is given by the following equation.

V _BF = V _E + v _T ln (I _O / I _S ) By substituting the equation into this equation, the equation is obtained.

V _BF = V _B −v _T ln (I _O / I _S ) + V _IN ² / 2v _T + v _T ln (I _O / I _S )
= V _B + V _IN ² / 2v _T ... Also, the output voltage of the output 119 is v ₀ , the resistance of the resistor 108 is R ₁ ,
The resistance value of the resistor 109 R ₂ Tosureba the following equation holds.

(V ₀ −V _BF ) / R ₂ = (V _BF − (R ₂ ) / R ₁ ∴v ₀ = (1 + R ₂ / R ₁ ) V _BF − (R ₁ / R ₂ ) V _B. By substituting and rearranging, v ₀ = (1 + R ₂ / R ₁ ) V _IN ² / 2v _T + V _B .. Further, by sufficiently increasing the capacity of the capacitor 110, a smoothed output is output to the output terminal 119. The voltage _VEa is obtained by the following equation.

Assuming that V _IN = V _a sinωt and solving the above equation, V _Ea = Va ² (1 + R ₂ / R ₁ ) / 4v _T + V _B , and the output voltage is V _Ea , v ₀ ln (I _O / I no effect of _S), since the DC output voltage at no signal is only V _B, by temperature compensation bias voltage V _B, a stable amplitude detection output. Further, with respect to R _1, by setting a large R _2, it can be considerably large output.

Note that, in the circuit of FIG. 1, the transistor 107 is used as a buffer transistor, and plays a role of lowering the output impedance.

In the above embodiment, the transistors 103 and 104 are two transistors connected in parallel. However, the transistors 103 and 104 may be one transistor. In this case, the size of the combined transistor is determined by transistors 101 and 102.
To match the total size of Further, the transistor 105 constituting the current mirror circuit is replaced with the transistor 10
It can also be moved to the 3,104 side.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals in the last two digits, and duplicate explanations are omitted. In this embodiment, the transistor 206 and the resistor 221 forming the current mirror circuit are connected between the collectors of the transistors 203 and 204 and the power supply 250, and the constant current source for the current mirror is eliminated.

According to the present embodiment, the same effect as the previous embodiment can be obtained, and one constant current source can be reduced, so that the number of parts can be further reduced.

[Effects of the Invention] As described above, in the present invention, the third transistor is provided in parallel with the differential circuit to which the input signal is input, and the amplitude detection output signal is obtained from the base of this transistor. Therefore, according to the present invention, an output signal equivalent to that of a conventional circuit using an operational amplifier can be obtained without increasing the number of elements. That is, according to the present invention,
Same function as conventional amplitude detection circuit using about 30 elements 13 to
Since this can be achieved by a circuit of 14 elements, the number of elements used can be reduced to less than half of the conventional one. Therefore, according to the present invention, the amplitude detection circuit can be easily made into an IC.

[Brief description of the drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, FIG. 3 is a basic circuit diagram of a conventional example, and FIG. 4 is a circuit diagram of a conventional example. 101-107, 201-207, 301-303 ... Transistor, 108, 1
09, 120, 121, 208, 209, 220, 221, 304-308 ... resistance,
110, 210, 311 ... capacitors, 111-113, 211, 213, 31
5, 316 ... constant current source, 114, 214, 312 ... bias voltage source, 1
15, 116, 215, 216, 313, 314 ... input signal source, 117, 11
8, 217, 218, 318, 319 input terminals, 119, 219, 320 output terminals, 150, 250, 309 power supply.

Claims (3)

(57) [Claims] 1. A first transistor having a base to which a DC bias voltage and a first signal superimposed on the DC bias voltage are input, and having an emitter connected to a second power supply via a first constant current source. A DC bias voltage and a second signal superimposed on the DC bias voltage, which is superimposed on the DC bias voltage, are input to a base, a collector is connected to a collector of the first transistor, and an emitter is A second transistor connected to the emitter of the first transistor; a collector connected to a first power supply; and an emitter connected to the first transistor.
A third transistor connected to the emitter of the third transistor, a first resistor having one end connected to the base of the third transistor, and the other end connected to a DC bias voltage source that generates the DC bias voltage; A second resistor having one end connected to the base of the third transistor and the other end connected to the output terminal; one transistor connected between the collector of the first transistor and a first power supply; A current mirror circuit in which the other transistor is connected between the first power supply and the second power supply via a second constant current source. 2. A DC bias voltage and a first signal superimposed on the DC bias voltage are input to a base, a collector is connected to a first power supply via one transistor of a current mirror circuit, and an emitter is connected to a first power supply. A first transistor connected to a second power supply via one constant current source, a second transistor having a base opposite to the first signal, the second bias being superimposed on the DC bias voltage and the DC bias voltage, and A signal is input, a collector is connected to the collector of the first transistor, an emitter is connected to a second transistor whose emitter is connected to the emitter of the first transistor, and a collector is connected to the other transistor of the current mirror circuit. A first power supply, the emitter being connected to the first power supply;
A third transistor connected to the emitter of the third transistor, a first resistor having one end connected to the base of the third transistor, and the other end connected to a DC bias voltage source that generates the DC bias voltage; A second resistor having one end connected to the base of the third transistor and the other end connected to the output terminal. 3. The current mirror circuit has a base connected to the collector of the other transistor, a collector connected to the first power supply,
3. The amplitude detection circuit according to claim 1, further comprising a fourth transistor having an emitter connected to the output terminal.