JP2940078B2 - Scanning circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning circuit suitable for use in, for example, a horizontal scanning circuit in a liquid crystal display device.

[Summary of the Invention]

The present invention relates to a scanning circuit, and when a means for detecting the arrival of an input signal and the supply of a signal to the next stage and controlling the supply of a clock signal to an inverter is provided, a low-speed clock signal or a switch when desired. By resetting the circuit using the means, the operation of the circuit is ensured, the reliability of the device is improved, and a highly stable scanning signal can be obtained.

[Conventional technology]

As a scanning circuit used for horizontal scanning of a liquid crystal display device, for example, a circuit as shown in FIG. 6 has been conventionally used (see Japanese Patent Application Laid-Open No. 2-1222 and the like).

That is, in FIG., V _DD, device IP constituting the inverter I between the power supply line to V _SS, and IN, the switching element P driven by respective clock signals, the clocked inverter which is provided with N are prepared. In this example, the switching elements P and N are provided inside the elements IP and IN constituting the inverter I, but the operation is the same as that of the above-mentioned prior art circuit.

And for example, in the case of using the horizontal scan switching elements P, with the horizontal image clock signal H _C and ▲ ▼ supplied to N, the input start signal H _S is the clock signal
H _C, is supplied to the first stage of the clocked inverter I ₁₀ is driven in synchronism with ▲ ▼. Further the output of the inverter I ₁₀ is supplied to the next stage through an inverter I ₁₁ normal configuration, the output of the inverter I ₁₁ via the clocked inverter I ₁₂ driven by inverting the drive of the inverter I ₁₀ It is fed back to the output of the inverter I _10. This latch one clock period by the inverter I ₁₀ ~I ₁₂ is performed. The latched signal is taken as the output signal phi _H1, the output signal phi _H1 is supplied to the gate of the switching element S ₁ for performing for example a horizontal sampling of the input video signal V _IN.

Further, from the next stage onward, the above-described circuits are repeatedly provided, and the clock signals H _C , ▲
Is configured to be supplied inverted.

Thus FIG. 7 A, the clock signal H _C, as shown in B in this circuit, ▲ ▼ is supplied, the input start signal H _S as shown in C in the drawing is supplied, respectively the figure from each stage
Output signals φ _H1 , φ _H2 } as shown in D, E ‥‥ are taken out. And these signals are the switching elements S ₁ , S ₂ ‥‥
The input video signal is supplied to each gate of
V _1N horizontal sampling is performed.

However, in the conventional configuration described above, the clock signal
The signal lines to which H _C and ▲ ▼ are supplied are respectively H _C → (N ₁₀ , P ₁₂ ) (N ₂₂ , P ₂₀ ) (N ₃₀ , P ₃₂ ) (N ₄₂ , P ₄₀ ) ‥‥ ▲ ▼ → (N ₁₂ , P ₁₀ ) (N ₂₀ , P ₂₂ ) (N ₃₂ , P ₃₀ ) (N ₄₀ , P ₄₂ ) ‥‥ The gate of the switching element is connected.

Therefore, in this case, for example, the number of pixels in the horizontal direction is 480, and the size of each element is W / L = 50 [μm] / 7 [μm],
Assuming that the thickness of the gate is 600 °, the capacitance C formed by the above gate is Thus, an extremely large capacity is connected to each clock signal line.

On the other hand, the magnitude of each clock and | V _DD -V _SS |
If it is attempted to drive this at a frequency of, for example, 4.5 MHz, it is difficult to drive with a large-capacity described above using a general-purpose C-MOS driver or the like.

Further, such a drive becomes impossible at all if, for example, the number of pixels in the horizontal direction in an HDTV signal becomes 1000 or more, and the clock frequency is also increased.

[Problems to be solved by the invention]

On the other hand, the applicant of the present application first detects the arrival of the input signal and the supply of the signal to the next stage, and controls the supply of the clock signal, so that the supply of the clock signal to the scanning circuit is performed for each stage. A circuit has been proposed in which the load on the clock driver is reduced by performing this operation (Japanese Patent Application No. 1-2846 / 1990).
No. 91).

That is, in FIG. 8, the clock signal H _C , ▲ ▼
The signal path from the signal line supplied with
S switch elements C ₁₁ and C ₁₂ are provided. The signal supplied to the input signal and the next stage from the previous stage is supplied to the NOR circuit NR _1, to the gate of the N-type element of the signal from the NOR circuit NR ₁ is C-MOS switch elements C _11, C ₁₂ Supplied, and the P-levels of the C-MOS switch elements C ₁₁ and C ₁₂ via the inverter I _14.
It is supplied to the gate of the mold element. Further switching elements
The gate of the N ₁₀ is connected to the power supply line to V _SS through the switching element N _13, a gate of the switching element N ₁₃ is connected to the power supply line to V _DD, a gate switching element P of the switching element N ₁₂ V through ₁₃
It is connected to the power supply line to _DD, the switching element P
Gate ₁₃ is connected to the power supply line to the V _SS.

Although the figure shows only a single-stage configuration, the above-described circuits are repeatedly provided from the next stage onward, and the clock signals H _C and ▲ ▼ are inverted and supplied to these circuits for each stage. Be composed.

Accordingly, in this circuit, FIG. 9 A, the clock signal H _C, as shown in B, ▲ ▼ is supplied, the input start signal H _S as shown in C in the drawing is supplied, the input start signal H _S By the rise, the C-MOS switch elements C ₁₁ and C ₁₂ are turned on as shown in FIG. D, and a clock signal as shown in FIGS. E and F is supplied to the first stage circuit. As a result, this first stage circuit is driven, and an output signal φ _H1 as shown in FIG. Then, at the _fall of the output signal φ _H1 , the C-MOS switching elements C ₁₁ and C ₁₂ are cut off. At this time, the switching elements N ₁₃ and P ₁₃ are turned on, so that the gates of the switching elements N ₁₀ and P ₁₂ There is connected to the power supply line to the V _SS, the switching element
The gates of N ₁₂ and P ₁₀ are connected to the power supply line to V _DD , and the first-stage circuit is brought into an initial non-operation state.

Similarly, the circuit at the second stage is brought into an operating state as shown in FIG. H, a clock signal as shown in FIGS. I and J is supplied, and an output signal φ _H2 as shown in FIG. Be taken out. Thereafter, the circuits in the third and fourth stages are similarly driven, and the output signals φ _H3 and φ _H4 } are sequentially extracted.

According to this circuit, as is clear from the figure, the supply of the clock signal H _C , ▲ ▼ is always 2-3
Only the circuit of the stage is used, and the load on the clock driver is reduced, so that driving by a normal circuit becomes possible.

However, when this circuit is implemented, in this circuit, since each stage is in a floating state at the time of start-up or the like, a signal due to noise or the like may be in a latch state in an unspecified stage. If the number of such stages is equal to or more than a predetermined number, a clock driver originally designed with a reduced load becomes too large in load at that time and cannot be driven. Unless the state is accidentally cleared by activation or the like, the circuit may not operate forever.

This application is made in view of such a point, and aims at satisfactorily eliminating the above-mentioned state with a simple configuration.

[Means for solving the problem]

A first means according to the present invention is a series circuit of a first inverter I ₁₀ , I ₂₀ # driven by synchronizing an input signal with a clock signal and a second inverter I ₁₁ , I ₂₁ # having a normal configuration. Through the third inverter I ₁₂ , I ₂₂ } driven by the driving and inversion of the first inverter. In a scanning circuit which is fed back to the output of the inverter and latches for one clock period, the arrival of the input signal and the supply of the signal to the next stage are detected (NOR circuits NR ₁ , NR ₂ ‥‥).
Means for controlling the supply of the clock signal to the first and third inverters (C-MOS switch element C ₁₁ ,
C ₁₂ , C ₂₁ , C ₂₂ }) are provided, and means (switches (1), (2), (3)) for lowering the clock signal (for vertical scanning) at least during a predetermined period at the time of startup are provided. It is a scanning circuit characterized by being provided.

The second means is provided through a series circuit of a first inverter I ₁₀ , I ₂₀ # driven by synchronizing an input signal with a clock signal and a second inverter I ₁₁ , I ₂₁ # having a normal configuration. The signal supplied to the next stage and the signal supplied to the next stage are supplied to the first stage.
In the scanning circuit, the output of the first inverter is fed back through the third inverter I ₁₂ , I ₂₂ ‥‥ driven by the driving and inversion of the inverter to perform the latch for one clock period. The arrival of the input signal and the supply of the signal to the next stage are detected (NOR circuits NR ₁ , NR ₂ ‥‥) and the first signal is detected.
And means for controlling the supply of the clock signal to the third inverter (C-MOS switch elements C ₁₁ , C ₁₂ , C ₂₁ , C ₂₂ ‥
‥) is provided, and a switch means (switching elements P ₁₄ , P ₁₄ ) is provided between a signal path connecting the output terminals of the first and third inverters and the input terminal of the second inverter and one power supply terminal. ₂₄ ...), And the switch means is turned on for a predetermined period.

[Action]

According to this, when desired, a low-speed clock signal or switch means provided between a signal path connecting the output terminals of the first and third inverters and the input terminal of the second inverter and one power supply terminal is provided. Since the reset of the circuit is performed by using the circuit, the operation of the circuit at the time of start-up or the like is reliably performed, and the reliability of the device is improved, and a highly stable scanning signal can be obtained.

〔Example〕

FIG. 1 shows a first embodiment. The scanning circuit described in In FIG example above conventional art, the clock signal H _C of the scanning circuit (10), ▲ ▼ and each changeover switch to the input of the start signal H _S (1),
(2) and (3) are provided, and through these switches (1), (2) and (3), for example, clock signals V _C , ▲ used for vertical scanning of a crystal display device.
▼ and start signal V _S is supplied.

Furthermore, these switches (1), (2) and (3)
For example, when the power is turned on as shown in FIG. 2A or when the display device is started, for example, as shown in FIG.
V _C , ▲ ▼ and start signal V _S are supplied,
Subsequent horizontal scanning, as shown in Figure C clock signal H _C,
▲ ▼ and the start signal H _S is supplied to the input of the scanning circuit (10).

Therefore, in this circuit, when the power is turned on or the display apparatus is started, a vertical scanning clock signal is supplied to the scanning circuit (10), and the period of this signal is several hundred times slower than that of the horizontal scanning clock signal. Therefore, driving can be reliably performed even with a large load, whereby the circuit is reset, and thereafter, a normal operation can be performed even with a horizontal scanning clock signal.

Note Figure 3 is switch (1) when starting the above-described power-up or display device, shows a circuit for forming a control signal H _RS for switching (2) and (3), for example, FIG. As shown in A, a series circuit of a resistor and a capacitor is provided between the power supply lines to V _SS and V _DD, and a control signal _HRS is derived from the connection midpoint. According to this, for example, the control signal _HRS is changed as shown in FIG. B (b) in response to a change in V _DD as shown in FIG. Switch (1),
(2) and (3) are switched to the clock signal side of vertical scanning. Alternatively, the derived signal may be further subjected to waveform shaping as shown in FIGS. D (a) and (b) by two-stage inverters as shown in FIG.

In this way, the above-described circuit can be reset at the time of starting or the like.

FIG. 4 shows a configuration of another example. Inverter I ₁₀ ~I ₁₃ described above in FIG, I ₂₀ ~I ₂₃ ‥‥, NOR circuit N
R ₁ , NR ₂ ‥‥, C-MOS switch element C ₁₁ , C ₁₂ , C ₂₁ , C ₂₂ ‥
‥, in addition to the elements constituting the switching element _{N 13, P 13, N 23} , P 23 ‥‥ like, the inverter I _10, the signal path switching which connects an input terminal of the output terminal of the inverter I ₁₃ of I ₁₂ Element P
Is connected to the power supply line to V _DD through a _14, the control signal H _RS above the gate of the switching element P ₁₄ is supplied. In the following, the inverters (I ₂₀ , I ₂₂ ) are similarly applied to each stage.
The output terminal and the signal path connecting the input terminal of the inverter I ₂₃ ‥‥ is connected to the power supply line to V _DD through a switching element P ₂₄ ‥‥, the above-mentioned control gate of the switching element P ₂₄ ‥‥ A signal _HRS is provided.

Accordingly, in this circuit, by turning on the switching elements P _14, P ₂₄ ‥‥ by a control signal H _RS to a low potential when desired, it is possible to reset the circuit.

As shown in FIG. 5, the reset timing is performed during a horizontal blanking period using a horizontal synchronization signal (A) or performed during a vertical blanking period using a vertical synchronization signal (B). Or (C) when the power is turned on or when the display device is activated as in the first embodiment.

Thus, according to the above-described circuit, the low-speed clock signal or the output terminals of the first and third inverters are connected to the second terminal when desired.
The circuit is reset using the switch means provided between the signal path connecting the input terminal of the inverter and one of the power supply terminals, so that the operation of the circuit at the time of start-up and the like is reliably performed. In addition, it is possible to improve the reliability of the apparatus and obtain a scanning signal with high stability.

According to this, the driving can be performed by a TFT, and the driver can be built in the panel of the liquid crystal display device. In addition, if the level conversion is also performed by the TFT, it can be externally provided. It is possible to supply signals at the TTL level.

Further, according to this device, it is possible to easily realize a high resolution display.

In the above description, the specific configuration of the transfer means is not limited to the above-described example, and is particularly applied to a case where a circuit is driven by a clock signal and a single pulse is transferred to form a scanning signal. You can do it.

〔The invention's effect〕

According to the present invention, when desired, a low-speed clock signal or switch means provided between a signal path connecting the output terminals of the first and third inverters and the input terminal of the second inverter and one power supply terminal. Is used to reset the circuit, so that the operation of the circuit at the time of start-up or the like is performed reliably, the reliability of the device is improved, and a highly stable scanning signal can be obtained. became.

[Brief description of the drawings]

1 is a configuration diagram of an example of a scanning circuit according to the present invention, FIG. 2 is a timing chart thereof, FIG. 3 is a configuration diagram of a signal forming circuit, and FIG. 4 is a configuration of another example of the scanning circuit according to the present invention. FIG. 5, FIG. 5 is a timing chart thereof, FIG. 6 is a configuration diagram of a conventional scanning circuit, FIG. 7 is a timing chart diagram thereof, FIG. 8 is a configuration diagram of another conventional scanning circuit, and FIG. It is the timing chart figure. (1) (2) (3) switch, (10) scanning circuit, I is an inverter, P, N, S, C are switching elements, NR
Is a NOR circuit.

Claims (2)

(57) [Claims] An input signal is supplied to a next stage through a series circuit of a first inverter driven in synchronization with a clock signal and a second inverter having a normal configuration, and a signal supplied to the next stage. In a scanning circuit in which the output of the first inverter is fed back to the output of the first inverter through a third inverter driven by inversion and inversion of the first inverter to latch for one clock period. Means for detecting the arrival and the supply of the signal to the next stage and controlling the supply of the clock signal to the first and third inverters are provided, and the clock signal is supplied at least during a predetermined period at the time of startup. A scanning circuit, comprising: means for reducing the speed. 2. An input signal is supplied to a next stage through a series circuit of a first inverter driven in synchronization with a clock signal and a second inverter of a normal configuration, and a signal supplied to the next stage. In a scanning circuit in which the output of the first inverter is fed back to the output of the first inverter through a third inverter driven by inversion and inversion of the first inverter to latch for one clock period. Means for detecting the arrival and the supply of the signal to the next stage and controlling the supply of the clock signal to the first and third inverters are provided, and the output terminals of the first and third inverters are provided. A switch means is provided between a signal path connecting the input terminal of the second inverter and one power terminal, and the switch means is turned on for a predetermined period. circuit.