JP2940448B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a structure of an element isolation region.

[0002]

2. Description of the Related Art A conventional device isolation region of a semiconductor integrated circuit is formed almost flat so as not to adversely affect a subsequent lithography process. This will be described below with reference to FIG.

First, as shown in FIG. 2A, a thermal oxide film 2 is grown on a silicon substrate 1 to a thickness of 20 to 60 nm, and a nitride film 3 is grown thereon by a CVD method to a thickness of 100 to 300 nm. Next, after the photoresist film 4 is formed, patterning is performed, and the photoresist film in the element isolation region is removed. Next, after the nitride film 4 is etched using the photoresist film 4 as a mask, the thermal oxide film 2 in the opening and the surface of the silicon substrate 1 are further etched to a depth of 40 to 150 nm. Next, as shown in FIG. 2B, after removing the photoresist film 4, selective oxidation is performed to form an element isolation oxide film 5A with a length of 300 to 1000 nm in the opening. Thereafter, as shown in FIG. 2C, the nitride film 3 and the thermal oxide film 2 are removed to form a flattened element isolation region composed of the oxide film 5A.

[0004]

Since the conventional device isolation region is formed of a flattened oxide film, it is difficult to optically detect (detect) the isolation region at the time of the next process. There is a problem that alignment accuracy is reduced.

[0005] In a semiconductor integrated circuit, a protection circuit is generally inserted between an input terminal and an internal circuit to prevent an electrostatic breakdown, thereby absorbing an overvoltage. This protection circuit has MOS
An ESD (electrostatic discharge) protection element using a transistor is used, and a parasitic transistor generally formed in a peripheral circuit portion is used as the transistor. However, since the element isolation oxide film in the conventional semiconductor integrated circuit has one type of structure, the withstand voltage of a parasitic transistor used as an ESD protection element is the same as the withstand voltage of a parasitic transistor formed in another circuit area. There has been a problem that the protection capability of the element is insufficient and the ESD resistance of the integrated circuit is reduced.

An object of the present invention is to provide a semiconductor integrated circuit having improved alignment accuracy and ESD resistance at the time of alignment.

[0007]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention comprises an element formed of two types of insulating films, a first planarized insulating film and a non-planarized second insulating film having a convex cross section. An isolation region is formed, and in particular, the ESD protection element portion is separated by a second insulating film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1C are cross-sectional views of a semiconductor chip for explaining an embodiment of the present invention. Hereinafter, description will be made in the order of the manufacturing process.

First, as shown in FIG. 1A, after a thermal oxide film 2 is formed on a silicon substrate 1 to a thickness of 20 to 60 nm, a nitride film 3 having a thickness of 100 to 300 nm is formed by a CVD method. . Next, after forming a photoresist film 4 on the entire surface, patterning is performed to form an opening in an element isolation region. Next, the exposed nitride film 3 is etched by dry etching using the photoresist film 4 as a mask.
Next, it is desired to lower the withstand voltage of a parasitic transistor in a region where the insulating film constituting the element isolation region is not desired to be planarized, for example, a portion used as an alignment detection mark or a peripheral circuit region.
The SD protection element formation region 10 is covered with the photoresist film 4A. Next, the thermal oxide film 2 and the silicon substrate 1 in the region where the element isolation insulating film is to be planarized, for example, the element formation region 11 of the internal circuit or the region where the withstand voltage of the parasitic transistor is to be increased, are reduced by 40 to 40 μm.
Etch to a depth of 150 nm.

Next, as shown in FIG. 1B, the photoresist films 4 and 4A are removed and then oxidized to form element isolation oxide films 5A and 5B. At this time, the element isolation oxide film 5A in the portion where the surface of the silicon substrate 1 is etched is substantially flattened, whereas the cross-sectional shape of the element isolation oxide film 5B in the portion where the silicon substrate 1 is not etched is convex. Becomes

Next, as shown in FIG. 1C, by removing the nitride film 3 and the thermal oxide film 2, a silicon substrate having two types of element isolation oxide films is formed. Hereinafter, devices and the like are formed in regions separated by the device isolation oxide films 5A and 5B to complete a semiconductor integrated circuit.

According to the present embodiment having the above-described structure, the element isolation oxide film can be used for alignment, or the ESD protection film can be used.
When used as a means for lowering the withstand voltage of the protection element, the current path is shortened by forming the cross section into a convex shape, and the element isolation oxide film is flattened in other areas. The alignment accuracy at the time of alignment is improved without adversely affecting the process.
The withstand voltage of the SD protection circuit element can be reduced.

[0013]

As described above, the present invention provides a non-planarized element isolation oxide film by providing two types of oxide films, a flat oxide film and a convex oxide film, as an element isolation insulating film. Is effective in improving the alignment accuracy at the time of fitting, and improving the ESD resistance by using it in the ESD protection element portion in which the withstand voltage of the parasitic transistor is lowered. On the other hand, a portion having a flattened element isolation oxide film can maintain a margin such as the depth of focus at the time of alignment as in the conventional case, and can keep the breakdown voltage of the parasitic transistor high.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for describing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional method for manufacturing an element isolation oxide film.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Thermal oxide film 3 Nitride film 4, 4A Photoresist film 5A, 5B Element isolation oxide film 10 ESD element formation area 11 Circuit element formation area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 27/092 29/78 (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 21/76-21/765 H01L 21/31 H01L 27/088-27/092 H01L 29/78

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit having an internal circuit region formed on a semiconductor substrate, a peripheral circuit region including an ESD protection element, and an element isolation region for element isolation.
The isolation region is first insulating film and the cross-sectional shape which is flattened is formed and a second insulating film convex, ESD protection element portion
Is a semiconductor integrated circuit characterized by being separated by the second insulating film .