JP2943029B2 - Method of manufacturing semiconductor device for forming multilayer wiring - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel method of manufacturing a semiconductor device for forming a multi-layer wiring, and more particularly, to a method of selecting an interconnection hole for interconnection in a multi-layer wiring.
The present invention relates to an improvement in a technique implemented using the D method.

[0002]

2. Description of the Related Art In recent years, as the density of semiconductor integrated circuits has increased, wiring structures have been formed in multiple layers, and there is a tungsten CVD method as a technique for connecting the wirings.

In this tungsten CVD method, in the technology of filling a contact hole, consideration is given to the physical properties of having a low contact resistance as a buried conductor and having a coefficient of thermal expansion equivalent to that of silicon for preventing hillocks. It is, and electroporation MIG configuration effect of further related step coverage, used for reasons such as shallow diffusion layer (shallow junction) temperature process suitability for formation.
This method further employs a selective tungsten CVD method which eliminates the need for an etch bag and a mask alignment therefor and is effective for embedding a substantially equal hole depth.

The selective tungsten CVD method utilizes a reduction reaction of a substance which reacts specifically (selectively) with a WF ₆ (tungsten hexachloride) gas in a portion where tungsten is to be deposited. For example, Solid State Tech
nology (November 1986, pp. 117-126) states that tungsten C is inserted into a contact hole formed in an oxide film on a silicon substrate.
An example in which the VD method is performed is shown as follows.

First, reaction (1): 2WF ₆ (g) + 3Si (s) → 2W (s) + 3SiF ₄ (g) is carried out at a temperature of about 300 ° C. and a pressure of 1 Torr or less.
At a thickness of, a tungsten layer which has reached its self-limiting limit exhibits good adhesion and low contact resistance.

Then, reaction (2): WF ₆ (g) + 3H ₂ (g) → W (s) + 6HF (g) is carried out at the same temperature and pressure, and tungsten is reacted in reaction (1).
It proceeds at a slower rate and has no particular formation limit.

The selectivity of the reaction (2) is attributed to the fact that the reducing gas H ₂ is dissociated by the catalytic action of pure and clean tungsten. It is stated that the formation limit and rate of reaction (1) and the rate of reaction (2) are controlled by temperature and pressure.

Japanese Patent Application Laid-Open No. Sho 64-55861 discloses that a tungsten layer is formed at a contact with a diffusion region by utilizing the reactions (1) and (2).

The selective tungsten CVD method described above is formed on a silicon diffusion region, which is a lower layer. However, not only multilayer wiring but also general wiring materials such as Al or AlSi such as Al or AlSi are used because of their electrical conductivity and ease of handling. Is used, and various barrier materials are used for connection with the diffusion region. Rather, these materials are often used as the lower layer material (base).

When the underlayer is Al or an alloy with Al, unlike the above reaction (1), reaction (3): 2Al (s) + WF ₆ (g) → 2Al F ₃ (s) + W (g) There is a problem that F ₃ is formed at the interface between Al and W, which causes a large resistance and also acts as a barrier for the reaction itself.

As a countermeasure, it has been attempted to provide a metal or a silicide in an upper layer of Al, which is associated with suppression of hillock of Al and formation of an anti-reflection layer. However, there are the following problems.

That is, when the underlayer is made of tungsten W other than Al, molybdenum Mo, and a refractory metal such as silicide, titanium Ti, titanium nitride TiN and titanium tungsten, the same as in the above reaction (2). However, these metals are not pure W formed in the reaction (1) as in the case of the reaction (2). Due to the influence, uniform (smooth surface) W cannot be obtained, and there is a problem that it is difficult to obtain good contact with the upper wiring.

[0013] Naturally, in the case of the above reaction (1) as well, although silicon has the same contamination and adsorption as described above, silicon itself is consumed for the reduction of WF ₆ gas and W is generated instead of it. Is neglected and is good.

[0014]

As described above, when the selective tungsten CVD method is performed, for example, for burying a connection hole for a multilayer wiring, when the base is made of Al or its alloy, high resistance and reduction due to the formation of AlF ₃ are achieved. Even when the base is made of a high melting point metal, there is a problem that contamination of the etching gas and obstruction of W formation due to adsorption of moisture in the air occur.

In view of such circumstances, the present invention takes advantage of the inherent advantages of the selective tungsten CVD method, employs a technique that solves the above problem, and employs a novel method of manufacturing a semiconductor device in which connection holes for multilayer wiring are buried. It is intended to provide.

[0016]

In order to achieve the above-mentioned object, the present invention provides an interlayer insulating film in which amorphous silicon is interposed between an interlayer insulating film and a lower layer wiring at a portion to be a connection hole between multilayer wirings. When connecting holes are formed in the film by etching, the lower wiring is protected from external contaminant gases, and pure tungsten is formed in the upper layer by the reaction (1), and undesired formation such as the reaction formula (3) occurs. At least the wiring material immediately below the amorphous silicon is made of a high melting point metal in order to prevent the generation of an object.

For this purpose, the method of the present invention for forming a multi-layered wiring comprises using a refractory metal for the uppermost layer of a lower-layered wiring composed of multiple wirings or a lower-layered wiring composed of a single layer, forming an amorphous silicon layer on the upper surface thereof, Next, an interlayer insulating film is formed, a connection hole is opened in the interlayer insulating film, amorphous silicon is exposed at the bottom thereof, and a reduction reaction of WF ₆ gas by the amorphous silicon in the exposed portion is performed. forming a tungsten layer, then performing the reduction reaction of WF ₆ gas by reducing gas is allowed to proceed for an additional deposition of tungsten on the tungsten layer, it has the steps of performing the embedding of contact hole, the amorpha
Reduction reaction of WF ₆ gas by silicon and reduction gas
And the reduction reaction of WF ₆ gas by
It is characterized in that it is carried out in a room .

According to an embodiment of the present invention, is a double wire comprising multiple interconnection of a refractory metal and Al or an alloy thereof, and a reducing reaction of WF ₆ gas in accordance with yet amorphous silicon, WF ₆ gas by reducing gas Is carried out in separate reaction chambers.

[0019]

According to the above structure, selective tungsten CVD
Since amorphous silicon is formed in the underground layer where tungsten is to be deposited by the method, it is protected by this and the underlying layer does not suffer from gas contamination due to etching when opening the connection hole, forming pure tungsten by reaction (1) . In addition, since the underlayer is a refractory metal that does not directly reduce the WF ₆ gas, the reaction (3) does not occur. As a result,
The formation of AlF ₃ and the resulting high contact resistance are eliminated to provide good electrical continuity to the connection hole for multilayer wiring. Sa
Furthermore, by performing reactions (1) and (2) in separate reaction chambers,
Deposits tungsten by eliminating other reaction by-products
To ensure the stability and reproducibility of the reaction
You.

[0020]

An embodiment of the present invention will be described with reference to the drawings.
Fig. 1 shows the manufacturing process (a) ~
FIG. 2 is a cross-sectional view of the semiconductor device according to FIG. 1D, and FIG. 2 is a plan layout view of a CVD reactor having a reaction chamber divided into two chambers.

FIG. 1A shows an Al alloy (AlS) having a film thickness of 8000 mm.
i) Amorphous silicon 2 is deposited on the upper surface of the double wiring composed of layer 1 and refractory metal titanium layer 8 having a thickness of 200 ° by about 1000 ° by sputtering, and an oxide film 7 of about 7,000 ° is further laminated thereon by LPCVD. After that, etching is performed to open a connection hole 3 of 7000 mm x 7000 mm, and amorphous silicon is exposed at the bottom.

At this stage, the wafer 9 is subjected to the CVD shown in FIG.
Via the transfer chamber 11 from the load lock chamber 10 of the reactor to supply WF ₆ / Ar gas was carried into the reaction chamber 12, and 1Torr the partial pressure of WF ₆ gas, the reaction was carried out (1) at 300 ° C. Then, an initial tungsten layer 4 is formed on the bottom of the connection hole 3 as shown in FIG. At this time, if the titanium layer 8 does not exist, Al F ₃ is formed in the Al alloy layer 1 by the reaction (3), which is not preferable.

In FIG. 1C, the wafer 9 is carried into another reaction chamber 13 via the transfer chamber 11, and the WF ₆ / H is transferred to the reaction chamber 13.
By supplying _two gases, the reaction (2) is performed at a partial pressure of H _{2 of} 1 Torr and 300 ° C., and the formation of the tungsten layer 5 on the tungsten layer 4 proceeds.

Next, as shown in FIG. 1 (d), an upper layer wiring 6 of the same Al alloy as the lower layer wiring is formed by sputtering for 8000 minutes.
Å was formed.

As described above, the connection of the upper and lower wirings was performed by the selective tungsten CVD method.
The electrical conduction of the l-alloy-W-Ti-Al alloy was good, and stable contact resistance characteristics of about 1 ohm were obtained.

In the case where the reaction (2) is carried out in the reaction chamber 12 without using the reaction chamber 13, the stability of the electrical conduction state varies, particularly with time, Reproducibility tended to be affected.

When the reactions (1) and (2) are repeatedly performed in the same reaction chamber, the reducing gas H ₂ , the reaction by-product SiF ₄ and HF are adsorbed on the inner wall of the reaction chamber. Is affected by heterogeneous outgassing. Therefore, in the present invention, reactions (1) and (2) are performed in separate reaction chambers.
Have .

The amorphous silicon on the upper surface of the lower wiring is
The layer is formed by a processing method such as CVD or PVD, and the thickness of the layer is about 50 to 3000 °, preferably about 1000 °. If the thickness is too small, the formation of W by the reaction (1) is insufficient, and it is difficult to control the subsequent reaction (2) with good uniformity and reproducibility. Conversely, if it is too thick, the formation of tungsten W in the initial stage reaches the self-limit,
This self-limit is affected by temperature, WF ₆ concentration, pressure and Si surface condition (thickness of native oxide film, etc.)
Unreacted amorphous silicon is left.
The high melting point metal has no particular upper and lower limits in terms of the effect of suppressing the reduction of the WF ₆ gas to the reduction only by silicon.

In the present invention, since the selective tungsten CVD method is used to fill the connection holes, the amorphous silicon does not need to be provided over the entire lower wiring, but may be provided in a portion including the connection holes and the vicinity thereof. .

In the present invention, the selective tungsten CVD method is applied to the filling of the contact hole. Not only in this case, but also when the by-product obtained when the underlayer reduces the WF ₆ gas becomes an undesirable substance. Alternatively, when foreign substances (contamination) on the upper surface of the base interfere with tungsten formation by the reduction reaction of the WF ₆ gas, the present invention can be applied to an arbitrary region of the base.

[0031]

According to the present invention, an uneven surface of tungsten is prevented from being formed due to contamination of the upper surface of the underlying wiring with an etching gas or moisture in the air, so that the connection between the upper and lower wirings is stabilized. Further, the formation of AlF ₃ and the resulting high contact resistance can be eliminated, and the connection hole for multilayer wiring can be buried with tungsten that provides good electrical continuity. As a result, it is possible to eliminate processes such as HF cleaning for removing contamination and controlling the upper surface of the lower wiring.

The selective tungsten CVD method used in the present invention employs WF using amorphous silicon or a reducing gas.
_Since the reduction of each of the _six gases is performed in a separate reaction chamber, tungsten is deposited while excluding by-products of other reactions, so that stability and reproducibility of the reactions can be easily ensured.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method for manufacturing a semiconductor device according to the present invention in each of steps (a) to (c).

FIG. 2 is a plan view schematically illustrating a CVD reaction apparatus according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lower wiring 2 Amorphous silicon 3 Connection hole 4 Tungsten layer 5 Tungsten connection line 6 Upper wiring 7 Interlayer insulating film 8 High melting point metal 10 Load lock room 11 Transfer room 12,13 Reaction room

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/285 H01L 21/3205 H01L 21/768

Claims (2)

(57) [Claims] 1. A connection hole for a multilayer wiring is selected.
A method of manufacturing a semiconductor device in which a multilayer wiring is formed by embedding and connecting between wirings by a method D, wherein a refractory metal is used for an uppermost layer of a lower wiring composed of multiple wirings or a lower wiring composed of a single layer, After an amorphous silicon layer is formed, an interlayer insulating film is formed, a connection hole is opened in the interlayer insulating film, and amorphous silicon is exposed at the bottom thereof. Reduction of the WF ₆ gas by the amorphous silicon in the exposed portion the reaction carried out, a tungsten layer is formed on the bottom and then out the reduction reaction of WF ₆ gas by reducing gas is allowed to proceed for an additional deposition of tungsten on the tungsten layer, to embed the connection hole, each step With
And reduction reaction of WF ₆ gas by the amorphous silicon
And the reduction reaction of WF ₆ gas with the reducing gas
A method for manufacturing a semiconductor device, wherein the method is performed in separate reaction chambers . 2. The method according to claim 1, wherein the multiple wiring is a double wiring made of a high melting point metal and Al or an alloy thereof.