JP2943434B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller for realizing quick non-execution processing.

[0002]

2. Description of the Related Art Conventionally, a programmable controller (hereinafter abbreviated as a PC) has been used for various physical information at a work site or the like (for example, when the number of products passing through an outlet of a belt conveyor reaches a predetermined quantity, ie, a receiving port). Or the logical information (for example, a sensor that scans the danger area when the cutting machine is in operation detects a moving object), or the like. Can be programmed to perform predetermined output control (sequence control). Normally, the on-site aspects such as the progress of the process and the work procedure are fluid. For this reason, the sequence of the sequence control at the work site was not originally determined from the beginning, and changes and corrections were made according to the actual conditions of the site, whether during PC trial operation or actual operation. It is decided by the constant repetition. For this reason, the PC incorporates all necessary control elements so that these changes can be easily dealt with, and a plurality of processing elements that determine one output by combining those control elements are set in advance. In many cases, sequence control is performed at a site by repeatedly selecting and executing one of the processes from a user program.

[0003] The above description of the programming of the PC is an object from the beginning of the development of the PC to enable people in the field who were distant in hardware and software in the related art to easily build a control program without difficulty. , Usually involves a completely different description format than computer programming. That is, PC
The same thing as the development connection diagram (relay circuit diagram) using the symbol mark of the contact (limit switch) or coil (relay) used in the field before the change is used. PC
Then, the program described above is translated into a machine language, and is written as bit information in word units in a program storage memory such as a RAM in order of addresses. The PC sequentially reads the programs in the order of addresses by an address counter counted by a clock signal, analyzes the programs by a decoder, reads corresponding data from a data memory based on the analyzed signals, and performs a logical operation. One output signal is determined repeatedly. The output signal is written to the output data area of the data memory and then read out to the output section to become an output signal for sequence control. That is, this is the same as the final output of the conventional relay circuit. Then, the PC repeats the above operation.

[0004] As for a method of describing a program on a PC, a description format of an international standard (IEC SC65A / WG6) called SFC (Sequential Functiont Chart) has recently been known. FIG. 9 (a) is a conceptual diagram of the configuration of the SFC program description. As shown in FIG.
A description section called EP and a description section called TRANSITION are connected by a link, and are alternately S0, T
N0, S1, TN1, S2,...
The PC continues ST if TRANSITION is on.
EP is selected, and if TRANSITION is OFF, the next STEP is determined to be non-selected.

FIG. 1B shows a TRANSITION (TN).
0, TN1) and STEP (S0, S1, S2). ON / OFF of each TRANSITION
The OFF state is determined by the output values TN0 and TN1 of the result of the logical operation of each TRANSITION program. For example, if the output value TN0 of TRANSITION (A) is ON, STEP (D) is selected, and TRANSITION (A) is selected.
If the output value TN1 of ON (B) is off, STEP
(E) is not selected. Within a single STEP, there are a plurality of ACTIONs, each of which consists of a number of instructions that perform a series of logical operations with a single output or instruction word. And at the beginning of the ACTION,
ACTION-QUALIFIERS indicating the execution timing of ACTION in the step is described. By this instruction, the selected ACTION is executed, and the unselected ACTION is not executed.

FIG. 10 shows the ACTION-QUALILI.
The description example of FIERS is shown. FIG. 11 schematically shows an arrangement when the program described above is translated into a machine language and stored in a program memory. Such a program based on the SFC description is also sequentially read from the program memory and executed in the same manner as in the related art. In the figure, the PC first performs TRA based on on / off data automatically input from a sensor or the like or on / off data manually input from a switch or the like.
The program of the NSITION detail group is executed, and the ON / OFF information of each TRANSITION is output as described above. Next, a STEP transition program group is executed, and STEP transition instruction information (selection information) based on the ON / OFF information is provided.
Is output. In the example of the STEP transfer program group shown in FIG. 11, if TRANSITION (TN0) is on, S
From TEP (S0) to STEP (S1), TRANSI
If TION (TN1) is on, a transition instruction is output from STEP (S1) to STEP (S2). Subsequently, the ACTION-QUALIFIERS program group is executed, and the execution timing of each ACTION is output. Based on this execution timing and the shift instruction, the ACTI
ON detail group programs (C), (D), (E) ...
Are sequentially read and processed as execution or non-execution.
It reaches the end point of the CION detail group. From here, TRA again
Returning to the program of the NSITION detail group, the operation of outputting ON / OFF information of each TRANSITION based on the input data (information) is repeated.

[0007] Generally, the one round of processing is called one scan. When a standard general-purpose microprocessor is used for the arithmetic processing of the PC, execution of each action (ACTION),
The time required for non-execution is almost the same and there is no significant difference. This is because the program is sequentially read even in the case of non-execution, and it is determined by operation that the program is not executed. Therefore, it can be considered that the time required for one scan is almost constant. For example, there are 50 actions in the program memory of one scan,
Assuming that there are an average of 100 instructions in one action,
T is the time required for execution and non-execution, and
ON detail group, STEP transfer program group, and ACTI
If the total of the processing time of the ON-QUALIFIERS program group is defined as K, the time required for one scan is 1
It can be represented by 00T × 50 + K.

As described above, the PC performs the ACTION-QUALIFIER of the step (STEP) selected by the transition for each scan.
Execute the action selected in S. Then, due to the nature of sequence control in which adaptive control is performed from among a large number of preset control conditions based on currently generated input information, a large number of actions selected in one scan are prepared. One or several actions,
Many other actions that remain are not selected and are not performed.

[0009]

By the way, if the PC selects only one action in one scan, the time that the PC spends on an effective operation for executing the control is 100 × T (one action). Is the calculation time) + K, and the remaining time 100 × T × 49 during one scan is a wasteful time because there is no direct relation to the control and a problem remains.

In recent years, the condition of a site controlled by a PC is not as simple as in the past, and the conditions to be controlled in accordance with the automation are also various, and the actions to be prepared for one scan must be increased accordingly. As described above, the time required for one scan is constant irrespective of the execution or non-execution of an action. Therefore, if the number of actions is increased, the time of one scan is also increased, and the timing of a required control output cannot be adapted in time. Fear comes out. Further, even if the control conditions are the same, if the work speed at the site is improved by automation or the like, there is a possibility that the control output may not be enough in time.

An object of the present invention is to provide a programmable controller which performs one scan processing at high speed by reading only a program to be executed from a memory and not reading a non-executable program from the memory.

[0012]

FIG. 1 is a block diagram of the present invention. The present invention relates to an SFC (Sequential Functiont).
Chart) is applied to the programmable controller 1 which operates by setting execution or non-execution of an action based on the description. The action head data 2 has instruction number data in which the number of instructions from the action to the next action is set in advance. The action head data 2 is, for example, the head data of an action of a sequence program stored in a RAM (Random Access Memory) or the like.
When the action is set to non-execution, the address shift means 3 shifts to the head of the next action using the number of instructions indicated by the instruction number data of the action head data as an offset address. The means 3 comprises, for example, a general-purpose processor.

The storage means 2 stores action head data in which the number of instructions from the head of an action to the next action is set. The means 2 is, for example, a RAM (Random
Access Memory).

When the above action is set to non-execution, the address shift means 3 shifts to the head of the next action using the number of instructions of the action head data stored in the storage means 2 as an offset address. The means 3 comprises, for example, a general-purpose processor.

[0015]

According to the present invention, the address transfer means 3 sets the offset address to the number of instructions from the head of the action stored in the action head data to the next action of the action set as non-executable. Move to the top.

Therefore, a non-executed program is not read from the memory, and one-scan processing can be performed at high speed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. In the configuration of the present embodiment, the transition condition recording memory 22 and the step ON
A / OFF recording memory 32 and an ACTION execution / non-execution recording memory 52 are provided.

FIG. 2 shows the transition condition memory 22.
In the figure, a general-purpose processor of a PC (not shown) sequentially calculates the transition detail group 21 stored in the program memory, and outputs on / off data of each transition output as the calculation result, that is, “0”.
Alternatively, the bit data of “1” is sequentially written to the transition condition memory 22.

FIG. 3 shows the step ON / OFF recording memory 32. The general-purpose processor sequentially computes the step transition program group 31 stored in the program memory based on the on / off data of each transition written in the transition condition memory 22, and outputs each step outputted as the computation result. The on / off data of the transition program is sequentially written into the step ON / OFF recording memory 32.

FIG. 4 shows the transition condition recording memory 22 and the step ON / OFF recording memory 32 and the SFC description 4
This shows the relationship with 1. As shown in FIG.
In the FC description 41, calculations are sequentially performed in accordance with the flow of the description, and the calculation results are described so as to be sequentially output. However, in an actual program, first, transition condition calculations are collectively performed, The result is written to the transition condition recording memory 22. Then, the step ON / OFF conditions are collectively calculated, and the calculation result is written to the step ON / OFF recording memory 32.

FIG. 5 shows the ACTION execution / non-execution recording memory 52. The general-purpose processor stores the action qualifier program group 51 stored in the program memory in the step ON / OFF recording memory 32.
Each action is calculated sequentially based on the step on / off conditions written in
The qualifier on / off data is stored in ACTION
The data is sequentially written to the execution / non-execution recording memory 52.

FIG. 6 shows the above-mentioned transition condition recording memory 22,
Step ON / OFF recording memory 32 and ACTION
The relationship between the execution / non-execution recording memory 52 and the SFC description 41 'is shown.

In this way, the execution / non-execution of the action program of the ACTION detail group stored collectively at the end of the program memory is selected.

FIG. 7 shows the structure of action head data arranged at the head of each action, which is a feature of the present invention. As shown in the figure, the action head data is composed of a section 71 including a header part indicating that this is the head of the action and an instruction part, and an operand part 72 indicating the number of instructions up to the next action head data.

The operation of the general-purpose processor for processing the detailed action group stored in the program memory in the above configuration will be described with reference to the flowchart shown in FIG. In this process, the transition detail group 21, the step shift program group 31, and the action qualifier program group 51 stored in the above-described program memory are sequentially processed, and the output of the calculation result is output.
After writing in each memory area shown in FIG. 6 corresponding to each output, it is sequentially started for each action.

In the flowchart of FIG. 8, the general-purpose processor reads out the action head data and
The execution instruction bit information (on / off information) corresponding to the action of the head data that has just been read is read from the CION execution / non-execution recording memory 52, and it is determined whether or not the read bit information is turned on (step). S81). Thereby, based on the bit information of the ACTION execution / non-execution recording memory 52, it is determined whether the action of the currently read head data is to be executed or not to be executed.

If the bit information is ON, the action instruction following the currently read action head data is executed, and the process ends (step S82).
As a result, the operation of the action determined to be executed in the arithmetic processing from the transition detail group 21 to the action qualifier program group 51 is executed.

On the other hand, if the bit information is turned off in step S81, the number indicated by the operand section 72 of the head data just read is replaced by the current address
The data is added to the data to create the next address data, and the process proceeds to that address to end the process (step S83).
As a result, an action that has been made non-executed in the arithmetic processing from the above-mentioned transition detail group 21 to the action qualifier program group 51 is not immediately read out from the program storage memory, and the execution / non-execution of the next action is immediately determined. Is performed.

As described above, in this embodiment, the processing of step S81, S82 or S83 in FIG. 8 is repeated for each action, and the non-executed action is not read out from the program storage memory. Then, the process immediately shifts to the next action. Therefore, for example, when only one action is executed in one scan, for example, if there are 50 action programs in the program storage memory, and one action program consists of an average of 100 instructions, Assuming that the time required for executing an instruction or shifting an action is T, the calculation processing time from the transition detail group to the action qualifier program group is K, and the time required for one scan is “100 (execution) × T + 49 (migration) ) ×
T + K ”, that is,“ 149T + K ”. In the same manner as in the prior art, when a non-executed action is sequentially read out from an instruction and subjected to NOP (Non Operation) processing, “100 (execution) × T + 100 (NOP) × T × 49”
+ K ”, that is,“ 5000T + K ”, compared to“ (5000T + K) − (149T + K) ”, that is,“ 4851T ”.

[0030]

According to the present invention, since only the program to be executed is read from the memory and the non-executable program is not read from the memory, the processing of one scan can be performed at high speed. Therefore, even if the number of actions is increased, the processing time does not increase, and more complicated control can be constructed. In addition, it can sufficiently follow the improvement of work speed. Further, by utilizing the shortened time, the general-purpose processor can cause the general-purpose processor to perform processing other than the arithmetic processing of the control by the interruption, so that various control methods can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram illustrating a transition condition recording memory.

FIG. 3 is a diagram illustrating a step ON / OFF recording memory.

FIG. 4 is a diagram showing a relationship between an SFC description and a memory.

FIG. 5 is a diagram illustrating an ACTION execution / non-execution recording memory.

FIG. 6 is a diagram illustrating a relationship between an SFC description and each memory.

FIG. 7 is a configuration diagram of action head data.

FIG. 8 is a flowchart illustrating processing for executing or shifting an action.

FIG. 9 is a diagram illustrating an SFC description of a conventional PC.

FIG. 10 is a diagram illustrating an SFC description of a conventional PC.

FIG. 11 is a diagram illustrating a conventional program execution method of a PC.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Programmable controller 2 Storage means 3 Address transfer means

Claims (1)

(57) [Claims] 1. A SFC (Sequencial Functiont Chart) programmable controller that operates by setting the execution or non-execution of actions based on the description (1), from the beginning of the action to the head data of the action (2)
The instruction count data that sets the instruction count until the next action
Previously it has straight to the top of the next action the number of instructions indicated by the instruction number of data beginning data (2) of the A <br/> action as an offset address when the action is set to a non-execution
Program Lama Bull controller characterized by comprising an address transition means (3) to migrate to Chi, a.