JP2943491B2 - Delay design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay design method,
In particular, the present invention relates to a delay design method using a hierarchical design.

[0002]

Conventionally, the delay design scheme of this kind, all
The design is performed without setting the time at which the signal passes through the connection point of the signal between the lower hierarchy and the upper hierarchy .

As conventional techniques, Hasegawa et al., A technique for speeding up a large-scale timing analysis system HEART (1), Proceedings of the 35th IPSJ Annual Conference (late 1987), 1987, 7F-6. is there.

[0004]

In the above-described conventional delay design method, signals of signals between all lower layers and higher layers are transmitted.
Since the design is performed without setting the time at which the signal passes through the connection point , the timing in the upper hierarchy is not determined at the time of designing the lower hierarchy. For this reason, there is a disadvantage that a problem caused by the lower hierarchy may be found when the design of the lower hierarchy is completed and the design of the upper hierarchy is performed.

[0005] An object of the present invention is to define the timing between layers by the time storage means 1 so that all lower layers and upper layers are defined.
The above-mentioned disadvantages are solved by setting the time when the signal passes through the connection point of the signal between the layers and performing the design, and when the lower layer is designed, the timing in the upper layer is determined, so that the above disadvantages are solved. It is another object of the present invention to provide a delay design method in which a problem caused by the lower layer is not found when the design of the lower layer is completed and the design of the upper layer is performed.

[0006]

According to the first aspect of the present invention, there is provided a delay design system comprising: (A) all lower layers and upper layers when an output time from a flip-flop or a latch is set to time 0;
Time storage means for storing the time at which the signal passes through the connection point between the signals, and (B) reference time calculation means for obtaining a time allowed in a lower hierarchy than the time stored in the time storage means; (C) a reference time storage means for storing the time obtained by the reference time calculation means, (D) a basic delay information storage means for storing connection relations and delay times in circuit elements included in lower layers, and (E). And (F) information stored in the reference time storage means, the basic delay information storage means, and the lower hierarchy information storage means. A lower layer delay analysis means for performing delay analysis on a lower layer; and (G) a lower layer circuit designed based on the time stored in the time storage means to satisfy a condition relating to the time. It is assumed that virtual information creating means for obtaining the connection relation and delay time in the circuit, (H) virtual information storing means for storing information obtained by the virtual information creating means, and (I) contained in the upper hierarchy Upper layer information storage means for storing a connection relationship between circuit elements and a delay time,
(J) an upper layer delay analysis unit for performing a delay analysis on an upper layer from information stored in the virtual information storage unit and the upper layer information storage unit.

According to the delay design method of the second aspect of the present invention, (A) connection of signals between all lower layers and upper layers when the output time from a flip-flop or a latch is set to time 0.
Time storage means for storing the time at which the signal passes through the continuation point ;
(B) a reference time calculation means for obtaining a time allowed in a lower hierarchy than the time stored in the time storage means;
(C) a reference time storage means for storing the time obtained by the reference time calculation means, and (D) a basic circuit information storage means for storing connection information and logic information in circuit elements included in the lower hierarchy and delay time. (E) hardware description storage means for storing a hardware description relating to a lower hierarchy, and (F) a hardware description storage means for storing a reference time storage means, a basic circuit information storage means and a hardware description storage means. Assuming a logic synthesis means for performing logic synthesis in consideration of a delay time, and (G) a lower-layer circuit designed to satisfy a condition related to the time based on the time stored in the time storage means. (H) virtual information storage means for storing information obtained by the virtual information creation means, and (I) higher-level information storage means for storing information obtained by the virtual information creation means. And the upper layer information storage means for storing a connection relationship and the delay time between the circuit elements included in the layer,
(J) an upper layer delay analysis unit for performing a delay analysis on an upper layer from information stored in the virtual information storage unit and the upper layer information storage unit.

In the delay design method according to the third aspect of the present invention, (A) connection of signals between all lower layers and upper layers when the output time from a flip-flop or a latch is set to time 0.
Time storage means for storing the time at which the signal passes through the continuation point ;
(B) a reference time calculation means for obtaining a time allowed in a lower hierarchy than the time stored in the time storage means;
(C) a reference time storage means for storing the time obtained by the reference time calculation means, and (D) a basic implementation for storing connection relations and delay times in circuit elements included in the lower hierarchy and graphic information of the circuit elements. Information storage means; (E) lower layer information storage means for storing connection relationships between circuit elements included in the lower layer and delay time; and (F) floor plan storage means for storing floor plan information relating to the entire circuit. ,
(G) a reference time storage unit, a basic mounting information storage unit, a lower layer information storage unit, and a layout unit that performs a layout considering a delay time for a lower layer than information stored in the floor plan storage unit; Based on the time stored in the storage means, assuming a lower-layer circuit designed to satisfy a condition relating to the time, virtual information creating means for obtaining a connection relationship and a delay time in this circuit; Virtual information storage means for storing information obtained by the information creation means; (J) upper layer information storage means for storing connection relations and delay times between circuit elements included in the upper layer; and (K) virtual information. A storage unit and an upper layer delay analysis unit that performs a delay analysis on an upper layer based on the information stored in the upper layer information storage unit.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

First, a delay design method according to the first invention will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining the operation of the delay design system according to one embodiment of the present invention.

Here, an example of delay analysis of a hierarchically designed logic circuit will be described.

In FIG. 1, a time storage means 1 stores signal connection points between all lower layers and upper layers when the output time from a flip-flop or a latch is set to time 0. Stores the time when passes. Reference time calculation means 2
Finds the time allowed in the lower hierarchy than the time stored in the time storage means 1. The reference time storage means 3
The time obtained by the reference time calculation means 2 is stored.
The basic delay information storage means 4 stores connection relationships and delay times in circuit elements included in the lower hierarchy. The lower hierarchy information storage means 5 stores the connection relation between circuit elements included in the lower hierarchy and the delay time. The lower layer delay analysis means 6 includes the reference time storage means 3 and the basic delay information storage means 4
Then, the delay analysis is performed on the lower hierarchy from the information stored in the lower hierarchy information storage means 5. Virtual information creation means 7
Is based on the time stored in the time storage means 1, assuming a lower-layer circuit designed to satisfy the condition relating to the time, and obtains a connection relationship and a delay time in this circuit. The virtual information storage means 8 stores information obtained by the virtual information creation means 7. Upper layer information storage means 9
Stores a connection relation between circuit elements included in the upper hierarchy and a delay time. The upper layer delay analysis unit 10 performs a delay analysis on the upper layer based on the information stored in the virtual information storage unit 8 and the upper layer information storage unit 9.

Next, the operation of the delay design system according to the first embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing an example of a logic circuit of the delay design system according to the embodiment of the present invention.

1 and 2, a flip-flop a
The signal output from 21 is a combinational circuit a23, a terminal a25, a terminal b
26, The signal reaches the flip-flop b22 through the combination circuit b24. The time storage means 1 stores the time at which a signal passes through the terminals a25 and b26. The reference time calculation means 2 calculates the flip-flop a from the time stored in the time storage means 1.
The time allowed between the terminal 21 and the terminal a25 and between the terminal b26 and the flip-flop b22 are obtained and stored in the reference time storage means 3. The basic delay information storage means 4 stores connection relationships and delay times in circuit elements included in the flip-flop a21, the flip-flop b22, the combinational circuit a23, and the combinational circuit b24. Lower layer information storage means 5
Stores connection relations and delay times between circuit elements included in the lower hierarchy. The lower layer delay analysis means 6 performs a delay analysis on a lower layer than the information stored in the reference time storage means 3, the basic delay information storage means 4, and the lower layer information storage means 5. Based on the time stored in the time storing means 1, the virtual information creating means 7 assumes a lower-layer circuit designed to satisfy the condition relating to the time, obtains a connection relationship and a delay time in the circuit, and Information storage means 8
To be stored. The upper layer information storage means 9 stores the connection between the terminals a25 and b26 and the delay time. The upper layer delay analysis unit 10 performs a delay analysis on the upper layer based on the information stored in the virtual information storage unit 8 and the upper layer information storage unit 9.

In the above, the delay analysis of the upper layer by the upper layer delay analyzer 10 can be performed prior to the delay analysis of the lower layer by the lower layer delay analyzer 6. Thus, at the time of performing the delay analysis of the lower hierarchy, the condition regarding the timing of the upper hierarchy is determined.

Next, a delay design method according to the second invention will be described with reference to the drawings.

FIG. 3 is a block diagram for explaining the operation of the delay design method according to the second embodiment of the present invention.

Here, an example will be described in which logic circuits are hierarchized and logic synthesis taking into account delay time is performed.

In FIG. 3, the time storage means 31 stores signal connection points between all lower layers and upper layers when the output time from the flip-flop or latch is time 0. Stores the time when passes. Reference time calculation means 32
Calculates the time allowed in the lower hierarchy than the time stored in the time storage means 31. The reference time storage means 33,
The time obtained by the reference time calculation means 32 is stored.
The basic circuit information storage means 34 stores connection relationships, logic information, and delay times in circuit elements included in the lower hierarchy.
The hardware description storage means 35 stores a hardware description related to a lower hierarchy. The logic synthesizing unit 36 performs logic synthesis in consideration of the delay time of a lower layer than the information stored in the reference time storage unit 33, the basic circuit information storage unit 34, and the hardware description storage unit 35. Based on the time stored in the time storage unit 31, the virtual information creation unit 37 assumes a circuit of a lower hierarchy designed to satisfy the condition regarding the time, and obtains a connection relationship and a delay time in this circuit. The virtual information storage means 38 stores information obtained by the virtual information creation means 37. Upper layer information storage means
39 stores the connection relation between circuit elements included in the upper hierarchy and the delay time. The upper layer delay analysis unit 40 performs a delay analysis on the upper layer based on the information stored in the virtual information storage unit 38 and the upper layer information storage unit 39.

Next, the operation of the delay design method according to the second embodiment of the present invention will be described with reference to the drawings.

2 and 3, a flip-flop a
The signal output from 21 is a combinational circuit a23, a terminal a25, a terminal b
26, The signal reaches the flip-flop b22 through the combination circuit b24. The time storage means 31 stores the time at which a signal passes through the terminal a25 and the terminal b26. Based on the time stored in the time storage means 31, the reference time calculation means 32 calculates the time between the flip-flop a21 and the terminal a25 and the time between the terminal b26 and the flip-flop b.
The time allowed in each of the periods 22 is obtained and stored in the reference time storage means 33. The basic circuit information storage means 34 stores connection relations and delay times in circuit elements included in the flip-flop a21, the flip-flop b22, the combination circuit a23, and the combination circuit b24. The hardware description storage means 35 stores a hardware description related to a lower hierarchy. The lower layer logic synthesis means 36 is
3, the delay time of the combinational circuit a23 for the lower hierarchy than the information stored in the basic circuit information storage means 34 and the hardware description storage means 35 so as to satisfy the delay time allowed between the flip-flop a21 and the terminal a25, and The logic synthesis is performed so that the delay time of the combination circuit b24 satisfies the delay time allowed between the terminal b26 and the flip-flop b22. Based on the time stored in the time storage means 31, the virtual information creating means 37 assumes a lower-layer circuit designed to satisfy a condition related to the time, obtains a connection relationship and a delay time in this circuit, It is stored in the virtual information storage means 38. The upper layer information storage means 39 stores the connection between the terminals a25 and b26 and the delay time. The upper layer delay analysis means 40,
Based on the information stored in the virtual information storage unit 38 and the upper layer information storage unit 39, a delay analysis is performed for the upper layer.

In the above, the delay analysis of the upper layer by the upper layer delay analysis means 40 can be performed prior to the logic synthesis of the lower layer by the lower layer logic synthesis means 36. Thus, at the time of performing the logic synthesis of the lower hierarchy, the condition regarding the timing of the upper hierarchy is determined.

Next, a delay design method according to the third invention will be described with reference to the drawings.

FIG. 4 is a block diagram for explaining the operation of the delay design system according to the third embodiment of the present invention.

Here, an example will be described in which a hierarchical layout is performed in consideration of the delay time.

In FIG. 4, the time storage means 41 connects signals between all lower layers and upper layers when the output time from the flip-flop or the latch is set to time 0.
Stores the time when the signal passes through the point . Reference time calculation means
42 obtains the time allowed in the lower hierarchy than the time stored in the time storage means 41. Reference time storage means 43
Stores the time obtained by the reference time calculation means 42. The basic mounting information storage means 44 stores connection relations in circuit elements included in lower layers, delay times, and graphic information of circuit elements. The lower layer information storage means 45 stores the connection relation between circuit elements included in the lower layer and the delay time. The floor plan storage means 46 stores floor plan information relating to the entire circuit. The layout unit 47 performs a layout in consideration of the delay time of the lower layer than the information stored in the reference time storage unit 43, the basic mounting information storage unit 44, the lower layer information storage unit 45, and the floor plan storage unit 46. Based on the time stored in the time storage means 41, the virtual information creation means 48 assumes a lower-layer circuit designed to satisfy the condition relating to the time, and obtains a connection relationship and a delay time in this circuit. Virtual information storage means 49
Stores information obtained by the virtual information creating means. The upper layer information storage means 50 stores the connection relation between circuit elements included in the upper layer and the delay time. The upper layer delay analysis means 51 performs a delay analysis on the upper layer from the information stored in the virtual information storage means 49 and the upper layer information storage means 50.

Next, the operation of the delay design method according to the third embodiment of the present invention will be described with reference to the drawings.

In FIG. 2 and FIG.
The signal output from 21 is a combinational circuit a23, a terminal a25, a terminal b
26, The signal reaches the flip-flop b22 through the combination circuit b24. The time storage means 41 stores the time at which a signal passes through the terminals a25 and b26. The reference time calculating means 42 calculates the flip-flop a from the time stored in the time storing means 41.
The time allowed between the terminal 21 and the terminal a25 and between the terminal b26 and the flip-flop b22 are obtained and stored in the reference time storage means 43. The basic mounting information storage means 44 stores the connection relations among circuit elements included in the flip-flop a21, the flip-flop b22, the combinational circuit a23, and the combinational circuit b24, the delay time, and the graphic information of the circuit element. The lower layer information storage means 45 stores the connection relation between circuit elements included in the lower layer and the delay time. The floor plan storage means 46 stores the position where the lower hierarchy a27 and the lower hierarchy b28 are arranged in the entire circuit and the shape thereof. The layout unit 47 determines the delay time of the combinational circuit a23 between the flip-flop a21 and the terminal a25 based on the information stored in the reference time storage unit 43, the basic mounting information storage unit 44, the lower hierarchy information storage unit 45, and the floor plan storage unit 46. The layout taking into account the delay time of the lower hierarchy is performed such that the delay time of the combinational circuit b24 and the delay time of the terminal b26 to the flip-flop b22 are satisfied. The virtual information creating means 48 is based on the time stored in the time storage means 41, and assumes a lower-layer circuit designed to satisfy a condition related to the time,
The connection relationship and the delay time in this circuit are obtained and stored in the virtual information storage means 49. The upper layer information storage means 50 stores the connection between the terminals a25 and b26 and the delay time. The upper layer delay analysis unit 51 performs a delay analysis on the upper layer based on the information stored in the virtual information storage unit 49 and the upper layer information storage unit 50.

In the above, the delay analysis of the upper layer by the upper layer delay analysis means 50 is performed by the layout means 47.
Can be performed prior to the layout for the lower hierarchy. As a result, when the layout of the lower hierarchy is performed, the condition regarding the timing of the upper hierarchy is determined.

In the above description, in the first invention, the second invention, and the third invention, the same name but different item number means that the item number is changed so that each invention can be easily described. And the contents are the same.

[0033]

As described above, according to the delay design method of the present invention , signal connection between all lower layers and upper layers is performed.
The design of the lower layer is completed by setting the time at which the signal passes through the point and then designing the lower layer, so that the timing of the upper layer is determined, so that the design of the lower layer is completed and the design of the upper layer is completed. At this point, there is an effect that no problem due to the design of the lower hierarchy is found.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an operation of a delay design method according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a logic circuit of a delay design method according to an embodiment of the present invention.

FIG. 3 is a block diagram for explaining the operation of the delay design method according to one embodiment of the second invention.

FIG. 4 is a block diagram for explaining the operation of the delay design method according to the third embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Time storage means 2 Reference time calculation means 3 Reference time storage means 4 Basic delay information storage means 5 Lower hierarchy information storage means 6 Lower hierarchy delay analysis means 7 Virtual information creation means 8 Virtual information storage means 9 Upper hierarchy information storage means 10 Upper Hierarchical delay analysis means 21 Flip-flop a 22 Flip-flop b 23 Combination circuit a 24 Combination circuit b 25 Terminal a 26 Terminal b 27 Lower hierarchy a 28 Lower hierarchy b 31 Time storage means 32 Reference time calculation means 33 Reference time storage means 34 Basic Circuit information storage means 35 Hardware description storage means 36 Logic synthesis means 37 Virtual information creation means 38 Virtual information storage means 39 Upper layer information storage means 40 Upper layer delay analysis means 41 Time storage means 42 Reference time calculation means 43 Reference time storage means 44 Basic implementation information storage means 45 Lower layer information storage means 46 Floor plan storage means 47 Layout means 48 Virtual information Creating means 49 virtual information storage unit 50 upper layer information storage means 51 the upper layer delay analyzing means

Claims (3)

(57) [Claims] (A) All lower layers when an output time from a flip-flop or a latch is set to time 0 and
Time storage means for storing a time at which a signal passes through a connection point of a signal with an upper hierarchy, and (B) reference time calculation means for obtaining a time allowed in a lower hierarchy than the time stored in the time storage means (C) reference time storage means for storing the time obtained by the reference time calculation means,
(D) basic delay information storage means for storing connection relations and delay times in circuit elements included in the lower hierarchy;
(E) lower layer information storage means for storing a connection relationship between circuit elements included in the lower layer and a delay time;
(F) a lower-layer delay analysis unit that performs delay analysis on a layer lower than the information stored in the reference time storage unit, the basic delay information storage unit, and the lower layer information storage unit; and (G) the time storage unit. (H) virtual information creating means for assuming a circuit of a lower hierarchy designed to satisfy a condition relating to the time based on the time stored in the virtual information and obtaining a connection relationship and a delay time in the circuit; Virtual information storage means for storing information obtained by the creation means; (I) upper hierarchy information storage means for storing connection relations and delay times between circuit elements included in the upper hierarchy; and (J) the virtual information. A delay design unit comprising: a storage unit; and an upper layer delay analysis unit that performs delay analysis on the upper layer based on information stored in the upper layer information storage unit. Formula. (A) All lower layers when the output time from the flip-flop or the latch is set to time 0 ,
Time storage means for storing a time at which a signal passes through a connection point of a signal with an upper hierarchy, and (B) reference time calculation means for obtaining a time allowed in a lower hierarchy than the time stored in the time storage means (C) reference time storage means for storing the time obtained by the reference time calculation means,
(D) basic circuit information storage means for storing connection relationships, logic information, and delay times in circuit elements included in the lower hierarchy, and (E) hardware description storage means for storing a hardware description relating to the lower hierarchy. (F) a logic synthesizing unit that performs a logic synthesis in consideration of a delay time of a lower hierarchy than information stored in the reference time storage unit, the basic circuit information storage unit, and the hardware description storage unit; Virtual information creating means for assuming a lower-layer circuit designed to satisfy a condition related to the time based on the time stored in the time storage means, and obtaining a connection relationship and a delay time in the circuit; H) virtual information storage means for storing information obtained by the virtual information creation means; and (I) connection relation and delay between circuit elements included in the upper hierarchy. Upper level information storing means for storing the interval, and (J) upper level delay analyzing means for performing a delay analysis on the upper level from the information stored in the virtual information storing means and the upper level information storing means. A delay design method characterized by the following. (A) all lower layers when the output time from the flip-flop or the latch is set to time 0 ;
Time storage means for storing a time at which a signal passes through a connection point of a signal with an upper hierarchy, and (B) reference time calculation means for obtaining a time allowed in a lower hierarchy than the time stored in the time storage means (C) reference time storage means for storing the time obtained by the reference time calculation means,
(D) basic mounting information storage means for storing connection relations and delay times in circuit elements included in the lower hierarchy and graphic information of the circuit elements; and (E) connection between circuit elements included in the lower hierarchy. Lower hierarchy information storage means for storing relations and delay times; (F) floor plan storage means for storing floor plan information relating to the entire circuit; (G) the reference time storage means and the basic mounting information storage means; (H) a layout means for performing a layout in consideration of the delay time of the lower hierarchy from the information stored in the lower hierarchy information storage means and the floor plan storage means;
Based on the time stored in the time storage means, assuming a lower-layer circuit designed to satisfy a condition relating to the time, and a virtual information creating means for obtaining a connection relation and a delay time in this circuit; A) virtual information storage means for storing information obtained by the virtual information creation means;
(J) upper layer information storage means for storing connection relations and delay times between circuit elements included in the upper layer; and (K) information stored in the virtual information storage means and the upper layer information storage means. A delay design method, comprising: an upper layer delay analysis means for performing a delay analysis on an upper layer.