JP2944247B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2944247B2 JP2944247B2 JP3094168A JP9416891A JP2944247B2 JP 2944247 B2 JP2944247 B2 JP 2944247B2 JP 3094168 A JP3094168 A JP 3094168A JP 9416891 A JP9416891 A JP 9416891A JP 2944247 B2 JP2944247 B2 JP 2944247B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- conductive pattern
- plane
- terminal
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数の端子を有するＩ
Ｃチップを収納する半導体装置であり、特にリードフレ
ームの構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC having a plurality of terminals.
The present invention relates to a semiconductor device for accommodating a C chip, and particularly to a structure of a lead frame.
【０００２】[0002]
【従来の技術】従来の技術として特開昭６３−２４６８
５１号公報に開示されているものがあるが、以下、図３
断面図および図４平面図を参照して従来の技術を説明す
る。2. Description of the Related Art As a prior art, Japanese Patent Laid-Open Publication No. 63-2468
No. 51, there is a description of FIG.
The related art will be described with reference to a cross-sectional view and a plan view of FIG.
【０００３】従来の、リードフレームは、図３に示すよ
うに、平らな金属板から形成された電源プレーン３０１
と、その上に絶縁体３０３を介して配置される接地プレ
ーン３０５を有しており、電源プレーン３０１はベース
電極として機能し、接地プレーン３０５は、接地電極と
して機能する。また、接地プレーン３０５の中央部は、
ＩＣチップ３０７を配置するために、開口部を有してい
る。As shown in FIG. 3, a conventional lead frame has a power supply plane 301 formed of a flat metal plate.
And a ground plane 305 disposed thereon via an insulator 303. The power plane 301 functions as a base electrode, and the ground plane 305 functions as a ground electrode. The center of the ground plane 305 is
An opening is provided for disposing the IC chip 307.
【０００４】また、図４に示すように、電源プレーン３
０１に対応する電源リードＰ４０１は電源プレーン３０
１に、接地プレーン３０５に対応する接地リードＧ４０
３は接地プレーン３０５に、それぞれ、平行間隙溶接
法、超音波接合法など一般に用いられている接合法で接
合される。[0004] Further, as shown in FIG.
01 corresponding to the power supply plane 30
1 includes a ground lead G40 corresponding to the ground plane 305.
3 is joined to the ground plane 305 by a commonly used joining method such as a parallel gap welding method or an ultrasonic joining method.
【０００５】その後、図３および図４に示すように、接
地プレーン３０５の開口部の電源プレーン３０１上にＩ
Ｃチップ３０７を載置し、ボンディングワイヤー３０９
を用いて、ＩＣチップ３０７の電源端子を電源プレーン
３０１に、接地端子を接地プレーン３０５に信用用端子
を信号用リード４０５にそれぞれ接続する。[0005] Thereafter, as shown in FIGS. 3 and 4, an I
The C chip 307 is placed, and the bonding wire 309 is placed.
The power supply terminal of the IC chip 307 is connected to the power supply plane 301, the ground terminal is connected to the ground plane 305, and the credit terminal is connected to the signal lead 405, respectively.
【０００６】以上のように、電源プレーン３０１と接地
プレーン３０５を用いることにより、ＩＣチップ３０７
の電源端子および接地端子を電源リード、接地リードへ
それぞれ１対１で接続する必要がなくなり、さらには、
パッケージが小型化でき、リードの相互インダクタンス
が減少するので、集積回路の応答速度の低下やスイッチ
ングノイズの増大等の問題点が解決できる。As described above, by using the power supply plane 301 and the ground plane 305, the IC chip 307 is provided.
It is not necessary to connect the power supply terminal and the grounding terminal to the power supply lead and the grounding lead one by one, respectively.
Since the package can be reduced in size and the mutual inductance of the leads decreases, problems such as a reduction in the response speed of the integrated circuit and an increase in switching noise can be solved.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、従来の
リードフレームでは、電源リードと接地リードは電源プ
レーン、接地プレーンにそれぞれ溶接接続されており、
固定リードとなっている。そのため、１種類のリードフ
レームでの電源リード、接地リードの自由な選択が不可
能となる。すなわち、リード配置の異なる機種の場合に
は、新たにリードフレームを設計しなければならず、汎
用性がないという問題があった。However, in the conventional lead frame, the power lead and the ground lead are welded to the power plane and the ground plane, respectively.
It is a fixed lead. Therefore, it is impossible to freely select a power supply lead and a ground lead in one type of lead frame. That is, in the case of a model having a different lead arrangement, a new lead frame must be designed, and there is a problem that there is no versatility.
【０００８】[0008]
【課題を解決するための手段】本発明は、前記課題を解
決するために、ベース電極として機能する電源プレーン
上に絶縁体を介して、接地電極として機能する中央部に
開口部を有する接地プレーンを設け、さらにその上に絶
縁体を介して、信号用の導電体を設け、ＩＣチップの電
源端子、接地端子、信号用端子の各端子と電源リード、
接地リード、信号用リードの各リードを電源プレーンま
たは接地プレーンまたは導電体を介して接続するように
した。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a ground plane having an opening at a central portion functioning as a ground electrode via an insulator on a power supply plane functioning as a base electrode. And further, a signal conductor is provided thereon via an insulator, and a power terminal, a ground terminal, a signal terminal and a power lead of the IC chip are provided.
Each of the ground lead and the signal lead is connected via a power supply plane, a ground plane, or a conductor.
【０００９】[0009]
【作用】電源プレーン上に絶縁体を介し接地プレーンを
設け、その接地プレーン上に絶縁体を介し導電体を用い
ることにより、集積回路の電源端子、接地端子および信
号用端子と電源リード、接地リードおよび信号用リード
をそれぞれ各プレーンまたは導電体で、電気的に接続で
きる。A ground plane is provided on a power supply plane via an insulator, and a conductor is used on the ground plane via the insulator to provide a power supply terminal, a ground terminal, a signal terminal, a power supply lead, and a ground lead of an integrated circuit. And the signal leads can be electrically connected to each plane or conductor.
【００１０】[0010]
【実施例】以下、本発明の実施例を図１の断面図および
図２の平面図を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the sectional view of FIG. 1 and the plan view of FIG.
【００１１】本発明のリードフレームは図１に示すよう
に、平らな金属板、例えば銅、鉄とニッケルの合金（４
２アロイ）等から形成された電源プレーン１０１と、そ
の上に絶縁体１０３を介して配置される接地プレーン１
０５と、その上に絶縁体１０７を介して配置される信号
用リードおよび信号用端子接続のためのボンディングパ
ターン１０９を有している。このボンディングパターン
１０９は導電性のあるもので形成され、この場合は、銅
ハクで形成される。また、電源プレーン１０１はベース
電極として機能し、接地プレーン１０５は接地電極とし
て機能する。接地プレーン１０５の中央部はＩＣチップ
１０７を配置するために、開口部を有し、接地プレーン
１０５の外形および内形寸法は、電源リード２０１およ
び電源端子と電源プレーン１０１を接続するために必要
な領域を確保するため、電源プレーン１０１の各寸法よ
り、それぞれ１．０〜１．４mm小さくなるよう形成す
る。As shown in FIG. 1, the lead frame of the present invention is a flat metal plate such as copper, an alloy of iron and nickel (4).
2 alloy) and a ground plane 1 disposed thereon with an insulator 103 interposed therebetween.
And a bonding pattern 109 for connecting signal leads and signal terminals arranged thereon with an insulator 107 interposed therebetween. The bonding pattern 109 is formed of a conductive material. In this case, the bonding pattern 109 is formed of copper. The power plane 101 functions as a base electrode, and the ground plane 105 functions as a ground electrode. The central portion of the ground plane 105 has an opening for disposing the IC chip 107, and the outer shape and inner size of the ground plane 105 are necessary for connecting the power supply lead 201 and the power supply terminal to the power supply plane 101. In order to secure an area, the power supply plane 101 is formed to be smaller by 1.0 to 1.4 mm than each dimension.
【００１２】また、絶縁体１０３の内形および外形寸法
は、接地プレーン１０５と接地リード２０３および接地
端子を接続するために必要な領域を確保するため、接地
プレーン１０１の各寸法より、それぞれ１．０〜１．４
mm小さく形成する。そして、図３および図４に示すよう
に、接地プレーン１０５の開口部の電源プレーン１０１
上に、ＩＣチップ１１１を載置し、ボンディングワイヤ
ー１１３を用いて、ＩＣチップ１１１の電源端子は電源
プレーン１０１へ、接続端子は接地プレーン１０５へ、
信号用端子はボンディングパターン１０９の第１パッド
１１５へ、電源領域２０１は電源プレーン１０１へ接地
リード２０３は接地プレーン１０５へ、信号用リード２
０５はボンディングパターン１０９の第２パッド１１７
へそれぞれ接続される。The inner and outer dimensions of the insulator 103 are set to be 1. 0-1.4
mm. Then, as shown in FIG. 3 and FIG.
The IC chip 111 is mounted thereon, and the power terminals of the IC chip 111 are connected to the power plane 101, the connection terminals are connected to the ground plane 105, and the bonding wires 113 are used.
The signal terminal is connected to the first pad 115 of the bonding pattern 109, the power supply region 201 is connected to the power supply plane 101, the ground lead 203 is connected to the ground plane 105, and the signal lead 2 is connected.
05 is the second pad 117 of the bonding pattern 109
Respectively.
【００１３】以上のように、ＩＣチップ１１７の電源端
子、接地端子、および信号用端子は、電源プレーン１０
１、接地プレーン１０５、およびボンディングパターン
１０９、それぞれを介して、外部リードに接続される。As described above, the power terminal, the ground terminal, and the signal terminal of the IC chip 117 are connected to the power plane 10.
1, the ground plane 105 and the bonding pattern 109 are connected to external leads, respectively.
【００１４】[0014]
【発明の効果】以上、詳細に説明したように、本発明
は、リードフレームに電源プレーン、接地プレーン、信
号用ボンディングパターンを形成し、ＩＣチップの電源
端子、接地端子、信号用端子を電源プレーン、接地プレ
ーン、信号用ボンディングパターンを化して外部リード
に接続することにより、リード配置の異なる機種におい
ても電源リード、接地リード、信号用リードの各々のリ
ードを任意に選択することができ、設計の自由度が大き
く汎用性の高いリードフレームを得る。As described in detail above, according to the present invention, the power supply plane, the ground plane, and the signal bonding pattern are formed on the lead frame, and the power supply terminal, the ground terminal, and the signal terminal of the IC chip are connected to the power supply plane. By connecting the grounding plane and signal bonding pattern to external leads and connecting them to external leads, it is possible to arbitrarily select the power supply lead, the grounding lead, and the signal lead even in models with different lead arrangements. A lead frame with a high degree of freedom and high versatility is obtained.
【００１５】さらに、電源プレーン、接地プレーンを設
けているので、集積回路の応答速度の低下を防ぎ、スイ
ッチングノイズを低減するという効果もある。Further, since the power supply plane and the ground plane are provided, there is an effect that the response speed of the integrated circuit is prevented from lowering and switching noise is reduced.
【図１】本発明の構造を示す断面図FIG. 1 is a sectional view showing the structure of the present invention.
【図２】本発明の構造を示す平面図FIG. 2 is a plan view showing the structure of the present invention.
【図３】従来技術の構造を示す断面図FIG. 3 is a cross-sectional view showing a structure according to the related art.
【図４】従来技術の構造を示す平面図FIG. 4 is a plan view showing the structure of the prior art.
１０１ 電源プレーン １０３ 絶縁体 １０５ 接地プレーン １０７ ＩＣチップ １０９ 信号用ボンディングパターン １１１ ボンディングワイヤー ２０１ 電源リード ２０３ 接地リード ２０５ 信号用リード DESCRIPTION OF SYMBOLS 101 Power plane 103 Insulator 105 Ground plane 107 IC chip 109 Signal bonding pattern 111 Bonding wire 201 Power lead 203 Ground lead 205 Signal lead
Claims (1)
数のリードを備え、前記複数の端子と前記複数のリード
が各々電気的に接続された半導体装置において、 前記半導体チップと前記複数のリードとの間には、第１
の幅を有する第１の導電性パターンと、前記第１の幅よ
り狭い第２の幅を有し、前記第１の導電性パターン上に
第１の絶縁膜を介し、かつ前記半導体チップ側及び前記
複数のリード側に前記第１の導電性パターンの一部がそ
れぞれ露出するように配置された第２の導電性パターン
と、前記第２の幅より狭い第３の幅を有し、前記第２の
導電性パターン上に第２の絶縁膜を介して配置された第
３の導電性パターンとが設けられ、 前記複数の端子内の第１の端子は、前記半導体チップ側
の前記第１の導電性パターンの露出部分に第１の金属細
線により接続され、前記複数のリード内の第１のリード
は、前記リード側の前記第１の導電性パターンの露出部
分に第２の金属細線により接続され、 前記複数の端子内の第２の端子は、前記半導体チップ側
の前記第２の導電性パターンの露出部分に第３の金属細
線により接続され、前記複数のリード内の第２のリード
は、前記リード側の前記第２の導電性パターンの露出部
分に第４の金属細線により接続され、 前記複数の端子内の第３の端子は、前記第３の導電性パ
ターン上に第５の金属細線により接続され、前記複数の
リード内の第３のリードは、前記第３の導電性パターン
上に第６の金属細線により接続されたことを特徴とする
半導体装置。1. A semiconductor device comprising: a semiconductor chip having a plurality of terminals; and a plurality of leads, wherein the plurality of terminals and the plurality of leads are electrically connected to each other. In between, the first
A first conductive pattern having a width smaller than the first width, a second conductive film having a second width smaller than the first width, a first insulating film interposed on the first conductive pattern, A second conductive pattern disposed so that a part of the first conductive pattern is exposed on each of the plurality of lead sides, and a third width smaller than the second width; And a third conductive pattern disposed on the second conductive pattern via a second insulating film. A first terminal of the plurality of terminals is connected to the first terminal on the semiconductor chip side. An exposed portion of the conductive pattern is connected by a first thin metal wire, and a first lead of the plurality of leads is connected to an exposed portion of the first conductive pattern on the lead side by a second thin metal wire. Wherein a second terminal of the plurality of terminals is the semiconductor chip Is connected to an exposed portion of the second conductive pattern by a third thin metal wire, and a second lead among the plurality of leads is connected to an exposed portion of the second conductive pattern on the lead side by a fourth wire. A third terminal of the plurality of terminals is connected by a fifth metal thin wire on the third conductive pattern, and a third lead of the plurality of leads is A semiconductor device characterized by being connected on a third conductive pattern by a sixth thin metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3094168A JP2944247B2 (en) | 1991-04-24 | 1991-04-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3094168A JP2944247B2 (en) | 1991-04-24 | 1991-04-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04324648A JPH04324648A (en) | 1992-11-13 |
| JP2944247B2 true JP2944247B2 (en) | 1999-08-30 |
Family
ID=14102826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3094168A Expired - Fee Related JP2944247B2 (en) | 1991-04-24 | 1991-04-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2944247B2 (en) |
-
1991
- 1991-04-24 JP JP3094168A patent/JP2944247B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04324648A (en) | 1992-11-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990608 |
|
| LAPS | Cancellation because of no payment of annual fees |