JP2945865B2 - Card interrupt processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a magnetic card, relates to Luca over de interrupt processing apparatus is utilized such as the card reader to read the card data such as an ID card, interrupt especially based on the bit serial data read from the card about Luca over de reading processing apparatus to improve the constraint of the data processing speed and memory usage when creating character data over.

[0002]

2. Description of the Related Art Conventionally, there are many examples of use of a system using a card reader including a magnetic card, an ID card, and the like. It is considered that when a telephone is used by a student or an employee, the student or employee who is the user of the telephone is individually specified, and the telephone station side charges each person.

FIG. 8 is a schematic configuration diagram of a system using a card reader. In the figure, 101 is an exchange, 102
Is an interface, 103a is a telephone body, 103b is a handset, 104 is a card reader, 105 is a magnetic card, an ID card, etc. (hereinafter collectively referred to as a card).

In this system, when an employee picks up the handset 103b from the telephone body 103a and dials the other party's subscriber number, the dial signal is sent to the exchange 101 via the interface 102. In the exchange 101, it is confirmed whether or not the other party's telephone is used, and if it is not in use, a telephone line with the other party's telephone is connected, and charging information is stored in a charging memory.

At this time, after confirming the connection of the telephone line as shown in FIG. 9 (A), the employee holds his / her card 105 and runs along the card reading path of the card reader 104, and The reader 104 reads card data such as its own ID number, employee number, and telephone number from the card 105 (B), converts the card data into data that can be transmitted to the exchange (C), and sends the converted data to the exchange. Send (D). When a reading error or a transmission error occurs, an error state to that effect is displayed on the display unit (E). Here, the exchange 101 registers its own ID number and the like in the memory from the transmitted data, and charges the call charge sequentially according to the talk time between the caller and the other party. After the call is over, the handset 103
When b is set, the communication line is released (F), and the exchange stores charging information for each ID number or the like in a predetermined memory. Thereafter, each time the same employee makes a call, the billing information is updated based on his or her own ID number and the like, and the telephone usage fee is charged.

Therefore, as described above, the card reader 104
Reads the card data of the card 105. Since the card data is composed of 1-bit serial data, the card reader 104 generates an interrupt signal for each bit while sequentially reading the 1-bit serial data. Then, it is necessary to create character conversion data for each byte based on the card interrupt processing program.

[0007] A card handler such as a student or an employee holds the card 105 and manually operates the card reader 104.
It is difficult to read the card data while synchronizing at a predetermined cycle because the vehicle runs at an arbitrary traveling speed along the card reading path.

As a result, the following conditions must be satisfied for the above-described card interrupt processing. (1) After detecting 1-bit unit serial data,
The interrupt processing is executed by the interrupt processing program,
The interrupt processing time for each bit must be completed within 80 μsec. This is determined from the standard concerning the reading speed when reading card data. Therefore, the interrupt processing time for each bit is 80 μsec.
, The interrupt signal of the next bit cannot be detected, resulting in missing bits and abnormal data. (2) In addition, since the card reader 104 is used by an unspecified number of people, it is difficult to use the card reader 104 while loading the external storage device into the card reader main body. As a result, the built-in RAM of the card reader 104 must be used. I can't get it. At this time, a commercially available control chip RAM or a RAM that conforms to a standard in advance is often used in order to reduce the size of the card reader itself, the hardware configuration of the card reader itself, and further reduce the cost. However, such R
In the case of the AM, the memory capacity that can be actually used becomes very small, except for the storage area for the operation constants and other essential fixed data. Therefore, saving memory becomes very important.

However, in the conventional card reader 104, the following interrupt processing is performed. One is that, as shown in FIG. 10, when the card reader 104 reads the card data of the card 105, it determines whether or not there is serial data in bit units (S101). Start (S
102), an interrupt process is executed (S103), and the first bit serial data is stored in the first byte of the RAM. Then, when the interrupt processing is completed, the interrupt is released (S104). Subsequently, if the bit serial data of the second bit is detected, the third byte is added to the second byte of the RAM.
When the bit serial data of the bit is detected,... Are sequentially stored in the third byte of the RAM. This series of processing sequentially stores all the card data of the card 105 while changing the byte on the RAM for each bit. Thereafter, after all the card data is stored in the RAM, the process proceeds to a normal program process (S105), and the RA
The bit serial data is sequentially read from each M byte area and converted into transmittable character data for each 8-bit serial data.

The other one is as shown in FIG. 11 and FIG.
When the serial data of the 5th to 1st bit is detected (S1
11), after starting the interrupt processing (S11
2), RAM bit counter 106 (see FIG. 12a)
The bit is checked according to the contents of the above, and if it is the first bit, the process jumps to the interrupt process corresponding to the first bit (S113), and the interrupt process is executed by the interrupt program as the jump destination (S114 ₁ ). This interrupt processing is performed by storing 1-bit serial data in the bit shift counter 107 (see FIG. 12B) under the shift instruction. Then, after this interrupt processing, the interrupt is released (S115). Subsequently, when serial data of the next bit is detected, bit checking and jump processing are performed in the same manner. If the serial data is the second bit, a shift instruction is issued twice and the second bit of serial data is converted to the bit shift counter 107. To be stored. Each bit serial data is stored in the bit shift counter 107 in a similar manner. When the serial data is stored in all 8 bits of the bit shift counter 107, the serial data is converted into character data based on the contents, written into the corresponding character data area of the RAM, and the bit counter 106 and the bit shift counter 107 are cleared. Then, similarly, interrupt processing of the next bit serial data is executed.

[0011]

However, the following problems have been pointed out in the above interrupt processing method. First, the former interrupt processing method (FIG. 10)
Performs interrupt processing under the relationship of one entrance and one exit, so that the interruption processing of the serial data of the next bit is performed after the termination of the interruption processing of a certain bit serial data. As a result, the serial data of a certain bit may exceed 80 μsec while judging to what bit the serial data belongs and in what byte the bit serial data is stored. In this case, There is a problem that it is impossible to detect the interruption of the next bit.

Further, since the bit serial data is sequentially stored by changing the byte area of the RAM for each bit,
There is a problem that the method cannot be applied when the storage capacity of the AM is small.

Next, the latter interrupt processing method (FIG. 11)
In FIG. 12), similarly, the interrupt processing is performed under the relation of one entrance and one exit, so that the interrupt processing of the next bit can be performed only after the interrupt processing of the previous bit is completed. There are many processing procedures such as bit check, jump processing, shift processing, etc., and the bit shift instruction increases as the number of bits increases. Needs to perform eight bit shifts,
There is a problem that the interrupt processing time easily exceeds 80 μsec. Therefore, it cannot be applied when the interruption time is limited. Further, since the detection data and the data in the process of processing need to be sequentially stored in the RAM until the character data of all the card data is transmitted.
There is a problem that cannot be applied to a small-capacity RAM of 56 bytes.

[0014]

The present invention has been made in view of the above circumstances.
In is to provide a card interrupt processing apparatus for realizing high-speed processing at the time of creating data by the card-bit data. It is a further object of the present invention to provide a card interrupt processing device which enables a memory to be used efficiently when data is created using bit data of a card.

[0016]

[0017]

According to a first aspect of the present invention, there is provided a card interrupt process for executing an interrupt process of the bit data based on an interrupt signal generated each time the bit data of a magnetic card, an ID card or the like is read. In the apparatus, storage means for storing an address for specifying an interrupt processing program corresponding to a bit in advance and a calculation processing program for calculating a storage position of the address, a bit counter for counting bits each time bit data of the card is read, and And a means for specifying an address of the interrupt processing program that performs interrupt processing of each bit data by using the count value of the bit counter and the calculation processing program each time the bit data is read. is there.

Next, a second aspect of the present invention is a card interrupt processing apparatus for executing interrupt processing of the bit data based on an interrupt signal generated each time bit data of a magnetic card, an ID card, or the like is read.
First storage means for storing in advance an address for specifying a bit-corresponding interrupt processing program and a calculation processing program for calculating the storage location of this address; a bit counter for counting bits each time bit data of the card is read; A second storage unit having a character counter for storing data after the interrupt processing, and specifying the address of the interrupt processing program using the count value of the bit counter and the calculation processing program each time the bit data is read. Processing address specifying means, and executing the interrupt processing of the bit data using an interrupt processing program corresponding to the address specified by the processing address specifying means;
A card interrupt processing apparatus provided with an interrupt processing execution means for incrementing the byte data of the character counter by +1 after an interrupt processing of bit data for every 8 bits.

[0019]

[0020]

Therefore, according to the present invention, each time bit data is read, the address of the interrupt processing program is specified by using the count value of the bit counter and a predetermined calculation processing program, and the interrupt of each bit data is specified. Performs the processing, so the conventional bit check,
There is no jump instruction, and the processing time for the CPU to execute the programmed instruction can be greatly reduced.

Further, according to a second aspect of the present invention, each time each bit data is read, the address of the interrupt processing program is specified by using the count value of the bit counter and the calculation processing program, and the interrupt of the specified address is specified. The interrupt processing of the corresponding bit data is executed using the processing program, and the character data is created by sequentially incrementing the byte of the character counter for every 8 bits, so that the interrupt processing of each bit data and the data until the end of the processing are stored. The address of the interrupt processing program can be immediately specified without using the storage medium, and interrupt processing and character data can be created using a storage medium having a very small capacity.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a card interrupt processing method according to the present invention will be described below with reference to the drawings. In this card interrupt processing method, when bit serial data is detected from a card and a bit interrupt signal is received, the serial data of each bit is read as shown in FIG.
Which interrupt processing program is executed for the serial data of the bit, that is, the address of the bit interrupt processing program is calculated based on a predetermined calculation processing program. When the address of the bit interrupt processing program is obtained by this calculation, the process jumps to, for example, the interrupt processing 1 of FIG. 1 corresponding to the address, and executes the interrupt processing 1.

At this stage, the next bit serial data is read, the address of the bit interrupt processing program is calculated in the same manner, and the jump to the obtained address is performed to execute the interrupt processing. In this way, the address of the bit interrupt processing program is sequentially calculated based on the bit serial data, and the interrupt processing is executed by jumping to the address obtained by the calculation.

Therefore, this card interruption processing method
In contrast to a single interrupt processing entry side, the exit side has eight bits corresponding to one byte, that is, eight exits, executes interrupt processing for each bit, and terminates individually. I have.

Therefore, according to this processing method, there is no jump instruction as in the prior art, and the interrupt processing time for each bit data of the card data can be greatly reduced. next,
An embodiment of a card interrupt processing apparatus for realizing the above method will be described with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of a card interrupt processing device in a card reader. In FIG.
Is a card reader unit, which generates an interrupt signal every time the card data of the card 2, that is, serial data for each bit is read, and sends it to the data processing unit 3 composed of a CPU. The read bit serial data and other data are sent to the I / O port 4.

The data processing unit 3 has a function of executing interrupt processing based on an interrupt processing program or the like stored in the program memory 5 and storing the processing result in the processing data memory 6. On the other hand, I / O port 4
It has a function of taking in a card insertion / removal signal, clock data and serial data of each bit sent from the card reader unit 1 in parallel and sending them to the data processing unit 3.

The program memory 5 is constituted by a ROM as shown in FIG. 3, and has an interrupt processing program 1, an interrupt processing program 2,..., An interrupt processing program corresponding to the 0th bit, the 1st bit,. Program 8 (hereinafter, these interrupt processing programs are simply referred to as processing 1, processing 2,..., Processing 8), and data of various processing steps are stored in processing data memory 6 without being stored in processing data memory 6.
It is composed of a calculation processing program 11 capable of immediately specifying an address corresponding to the processing 2,..., And an address table 12 for sequentially storing addresses of the processing 1, processing 2,.

The processing data memory 6 is constituted by a RAM as shown in FIG. 4, and has a storage capacity of, for example, 256 bytes as a data storage area including a stack area. Have the number of digits of the card 105, for example, 70 digits, and the bit counter 1
4 and a character counter 15 are provided.
The bit counter 14 is incremented by +1 each time the serial data of each bit is detected, and is cleared at the end of the interrupt processing of the eight bit serial data. Further, the character counter 15 has a role of incrementing by +1 every time the interruption processing of eight bit serial data is completed.

As shown in FIG. 5, the data processing section 3 has a data reading means 31 for reading serial data from the I / O port 4 upon receiving an interrupt signal from the card reader section 1; Bit data reading means 32 for reading the bit data of the bit counter 14 provided in the data memory 6; and processing address specifying means 33 for specifying an address corresponding to each bit interrupt processing program based on the calculation processing program 11 in the program memory 5. And an interrupt processing stored in the address specified by the processing address specifying means 33, that is, an interrupt processing executing means 34 for executing an interrupt processing program.

Next, the operation of the apparatus configured as described above will be described. Generally, although not shown, the data processing unit 3 performs normal processing under a normal processing instruction.

In this state, when the card 2 runs along the card reading path of the card reader 1, the card reader 1 sends various data at the timing shown in FIG. FIG. 4A shows card insertion / removal data for notifying the insertion / removal state of the card 2, which is ON when the card is inserted and OFF when the card is removed. FIG. 2B shows a bit determination clock generated while rotating the card 2 while contacting the card 2, FIG. 2C shows bit serial data, and FIG. 2D shows an interrupt signal.

Here, the data processing unit 3 reads the bit serial data from the I / O 4 and stores it in the processing data memory 6 every time an interrupt signal is received as in step S1 of FIG. 7 (S2), while the bit counter 14 Is read out (S3), and the program memory 5
An address corresponding to the bit interrupt processing program shown in FIG. 3 is specified using the calculation processing program 11 (S4).

More specifically, when the 0th bit of serial data is read in response to the interrupt signal, the bit count value of the bit counter 14 is "0". Is the address of the address table + (bit count value x 2
From the above formula, 1000+ (0 × 2) = 1000, and the address data “0” stored in the address 1000 of the address table 12 is the same as the address of the interrupt processing 1 of the 0th bit. Become.

Also, even if the third bit serial data is read, the bit count value is "3". Therefore, if the address calculation is performed based on the calculation processing program, 1000+ (3 × 2) = 1006, the address data “300” stored at the address 1006 of the address table becomes the address of the interrupt processing 4 of the third bit.

When the address "0" of the interrupt processing 1 relating to, for example, the first bit of serial data is specified as described above, the specified processing 1 is executed (S5 ₁ ). If the bit is ON, this interrupt processing 1 turns ON the serial data of the first bit, that is, "1".
And stored in the character data area 13. After completion of the interrupt processing of the 0th bit serial data, the bit count value of the bit counter 14 is set to “0”.
→ Set to “1”. Thereafter, the interrupt processing address of the serial data of each bit is sequentially specified in the same manner from the next serial data of the first bit, and the interrupt processing 2, 3,... Is executed. After the interrupt processing is completed, the bit count value of the bit counter 14 is sequentially incremented by +1.

When the interrupt processing 8 of the seventh bit serial data is completed, the bit count value of the bit counter 14 is cleared to "0", while the count value of the character counter 15 is incremented by +1. As a result, 8-bit conversion data is stored in the first digit character data area 13, and character data constituting one character is stored. Thereafter, the same processing is repeatedly executed until all the card data is completed.

Therefore, according to the embodiment described above, the address of the interrupt processing for the bit serial data is calculated using the calculation processing program for each bit, and the interrupt processing of the address of the calculation result is executed. Calculates the address of the interrupt processing for the next bit of serial data, executes the interrupt processing of the address of the calculation result, and terminates the processing individually after each interrupt processing. Thus, interrupt processing of each bit serial data can be executed, the interrupt processing time can be greatly reduced, and each bit serial data can be reliably detected. As a result, the processing can be completed in about 40 μsec from the generation of the interrupt signal relating to the serial data of each bit until the completion of the interrupt processing.

Each time an interrupt signal is received, an address of an interrupt process relating to bit serial data is specified using a calculation processing program for each bit, an interrupt process corresponding to the address of the interrupt process is executed, and Since the set / offset data is stored in the area 13 for each bit data,
Since the number of processing steps can be reduced and required data can be reliably secured without leaving data in progress, the memory can be used efficiently.

[0040]

[0041]

According to the present invention as described above,
Various effects such as According to the first aspect of the present invention , the interrupt processing address is quickly specified for each bit data of the card, and the interrupt processing is executed. Therefore, there is no need to perform a bit check or a jump instruction, and it is possible to realize high-speed data creation using bit data.

Further, according to the second aspect of the present invention , since interrupt processing is executed for each bit data and set / offset data is stored for each bit data, the number of processing steps can be reduced and the memory can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a view for explaining an embodiment of a card interrupt processing method according to the present invention.

FIG. 2 is a configuration diagram showing one embodiment of a card interrupt processing device according to the present invention.

FIG. 3 is a view showing a data array of a program memory shown in FIG. 2;

FIG. 4 is a diagram showing a data array of a processing data memory of FIG. 2;

FIG. 5 is a functional block diagram of the data processing unit shown in FIG. 2;

FIG. 6 is a time chart of various data generated when card data of a card is read by a card reader unit.

FIG. 7 is a diagram for explaining an operation procedure of the card interrupt processing device according to the present invention.

FIG. 8 is a schematic configuration diagram of a system including a card reader for explaining a usage example of a conventional card reader.

FIG. 9 is a view for explaining an operation procedure of the system shown in FIG. 8;

FIG. 10 is a flowchart of an interrupt processing operation for bit data in a conventional system.

FIG. 11 is a flowchart of an interrupt processing operation for bit data for explaining another example of the conventional system.

FIG. 12 is a view for explaining a data storage state of bit data during the interrupt processing operation shown in FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Card reader part, 2 ... Card, 3 ... Data processing part,
5: Program memory, 6: Processing data memory, 12:
Address table, 13 ... Character data area, 1
4 ... bit counter, 15 ... character counter, 31
... data reading means, 32 ... bit data reading means, 33 ... processing address specifying means, 34 ... interrupt processing executing means.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/46 G06K 17/00 G06K 19/00 G06K 1/04 G06K 7/00 G06F 3/08 G06F 12/00 G06F 13 / 24 G11B 19/00 G11B 20/10 G11B 23/00 G11B 25/04 G11B 27/10

Claims (2)

(57) [Claims] 1. A card interrupt processing device for executing interrupt processing of bit data based on an interrupt signal generated each time bit data of a card is read, comprising: an address for specifying an interrupt processing program corresponding to a bit in advance; Storage means for respectively storing a calculation processing program for calculating a storage position; a bit counter for counting bits each time bit data of the card is read; a count value of the bit counter for reading the bit data; and the calculation program Means for specifying an address of the interrupt processing program that performs interrupt processing of each bit data by using the above. 2. A card interrupt processing apparatus for executing interrupt processing of bit data based on an interrupt signal generated each time bit data of a card is read, comprising: an address for specifying an interrupt processing program corresponding to a bit in advance; First storage means for respectively storing a calculation processing program for calculating a storage position; second storage means having a bit counter for counting bits each time bit data of the card is read and a character counter for storing byte data; A processing address specifying means for specifying an address of the interrupt processing program using the count value of the bit counter and the calculation processing program each time the bit data is read; and an address specified by the processing address specifying means. Interrupt processing of the bit data using a corresponding interrupt processing program, and an interrupt processing executing means for incrementing the byte data of the character counter by +1 after the interrupt processing of the bit data for every 8 bits. And a card interrupt processing device.