JP2946940B2 - Data transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit inside and at terminals of an electronic device.

[0002]

2. Description of the Related Art An electronic device has a group of signals to which data is transmitted at the same timing as represented by an address and data in an internal circuit and terminals. In a conventional electronic device, the logic level of these signals is statically set. For example, the logic level of the address signal group of the microprocessor is fixed to positive logic.

FIG. 5 shows an example of a data transmission circuit in a conventional static circuit. FIG. 6 is a timing chart showing the operation timing of the circuit diagram of FIG. In FIG. 5, 5
01 is data to be transferred next, 502 is a data transmission signal, and 503 is an output control signal which is a timing for outputting the next data to the data transmission signal. Also 50
Reference numeral 4 denotes a D flip-flop for storing the previous data during a period until the output of the next data is instructed by the output control signal 503.

In this example, the width of data to be transferred is five. First, data 501 to be transferred next is input to each D flip-flop 504 as five signals. Finally, D is synchronized with the rise of the output control signal 503.
The flip-flop 504 outputs the data as a data transmission signal 502.

Consider a case where all five data transmission signals 502 are at a high level, and all five data 501 to be transferred next are at a low level. When the output control signal 503 rises, all five data transmission signals 502 become low.
Change to level simultaneously.

[0006] FIG. 7 shows an example of the data transmission circuit in a conventional dynamic circuit. FIG. 8 is a timing chart showing the operation timing of the circuit diagram of FIG. In FIG. 7, 7
01 is data to be transferred next, 702 is a data transmission signal, 703 is an output control signal indicating the timing of outputting the next data to the data transmission signal, and 704 is a precharge indicating the timing of precharging the data transmission signal 702. Signal. Reference numeral 7 denotes a gate circuit including a combination of P-channel and N-channel transistors.

In this embodiment, the width of data to be transferred is five. First, data 701 to be transferred next is input to each gate circuit 7 as five signals. In parallel with this, a low level is input to the precharge signal 704, and the data transmission signal 702 is precharged and becomes a high level.

After that, the precharge signal 704 changes to a high level, but the data transmission signal 702 retains data by a parasitic capacitance on a wiring or a gate. Finally, a high level is input to the output control signal 703,
If the data 701 is at the high level, discharge is performed, and a low level is output as the data transmission signal 702. Otherwise, the discharge is not performed and the data transmission signal 702 is kept at the precharged high level. .

Next, consider a case where all five data 701 to be transferred are at low level. In this case, when the output control signal 703 goes high, the data transmission signal 70
2 are all discharged to a low level.

[0010]

When an electronic device attempts to change a signal from a high level to a low level or from a low level to a high level, a period until the charging or discharging of the capacitance parasitic on the signal line is completed. During this time, the current flowing to the output circuit increases, and accordingly, the current consumption of the electronic device increases.

This increase in current consumption increases with the parasitic capacitance of the signal lines, and further increases in proportion to the number of signal lines that change simultaneously.

In a conventional electronic device, for example, when the address terminal changes from all bits 1 to all bits 0, the potential of the ground terminal of the electronic device locally rises due to a temporary increase in current. A phenomenon called ground bounce occurs, which causes a malfunction of the system.

An object of the present invention is to solve the above-mentioned drawbacks, and to provide a data transmission circuit in which a temporary increase in current consumption is small and a ground bounce does not easily occur.

[0014]

In order to achieve the above object, a data transmission circuit according to the present invention has a signal line group, a determination unit, a signal line, and an output unit, and is provided inside or inside an electronic device. A circuit for transmitting a plurality of bits of data to the outside, wherein the signal line group transmits data, and the determining means sets a logical level of a signal output to the signal line group with target data as an input. The signal line indicates the logical level of the signal determined by the determining means, and the output means converts the logical level of the target data in accordance with the determination of the determining means, and outputs a signal line group. Each day
To the signal line group so that logical inversion does not occur
Outputs data . In addition, the data according to the present invention
The data transmission circuit includes a computing unit, a data output gate circuit,
A level indicating gate circuit, and the inside of the electronic device.
Or a circuit that transmits multiple bits of data to the outside
The arithmetic unit determines the logical level of each data to be transferred next.
And the logic of each data of the data transmission signal group during transfer corresponding to
Whether the number of pairs with different levels exceeds half
If the number of different pairs exceeds half,
Output logic level indication signal as low level
And the number of said different pairs does not exceed half
Output the logic level instruction signal as high level
It is those, wherein the data output gate circuit, the operation
The next transfer is performed based on the logic level instruction signal from the
It converts the logic level of the data
Signal until the next data is output
Stores the previous data and synchronizes with the output control signal.
The data whose logical level has been converted is used as the data transmission signal group.
The level indicating gate circuit,
A logic level instruction signal and an output control signal from the arithmetic unit;
Data input to the data transmission signal group
Signal indicating the logic level of the data
Output. In addition, the data transmission time according to the present invention
The path consists of a computing unit, a gate circuit for data output, and a level finger.
An indication gate circuit, inside or outside the electronic device.
A circuit for transmitting a plurality of bits of data to section, the
The arithmetic unit calculates the number of low level data to be transferred next.
To determine if the number of low levels exceeds half
Logic level indication signal is low when
Output as a level, and the number of the low levels is half
If not, the logic level indication signal is set to high level.
The data output gate.
The circuit is based on a logic level instruction signal from the arithmetic unit.
To change the logical level of the data to be transferred next,
In parallel with the precharge signal and output control signal
Precharge and discharge data transmission signals
And transmits the data with the converted logic level.
A signal group, and the level indicating gate
The circuit includes: a logic level instruction signal from the arithmetic unit;
Data transmission signal based on charge signal and output control signal
Signal representing the logic level of the data output to
It is output as a logic level instruction signal.

[0015]

A signal line group indicating the logical level of data output to the signal line group is provided separately from the signal line group for transmitting data, and the logical level of the target data is converted and output to the signal line group. The logic level is selected so that the signal lines for transmitting data do not invert more than half.

[0016]

Next, the present invention will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a diagram showing a data transmission circuit in a static circuit according to Embodiment 1 of the present invention. FIG. 2 is a timing chart showing the operation timing of the circuit diagram of FIG.

In FIG. 1, 101 is data to be transferred next, 102 is a data transmission signal group, 103
Is an output control signal indicating the timing of outputting the next data to the data transmission signal group 102.

Reference numeral 104 denotes a D flip-flop which stores previous data until output of the next data is instructed by the output control signal 103, and 105 denotes a conversion of the logical level of data to be transferred next. EXNOR, 1
Numeral 06 denotes an arithmetic unit for determining the logical level of data to be transferred next, 107 denotes a signal indicating the logical level of data to be transferred next, and 108 denotes a logical level indicating signal of transferred data. D flip flop 104, EXNOR10
Although some of the data output gate circuits 1 including 5 have an internal configuration omitted, all have the same configuration.
Also, a D flip-flop as a level indicating gate circuit is provided.
The rop 104a is a logical level instruction from the arithmetic unit 106.
The signal 107 and the output control signal 103 are input and data
Logic level of the data output to the data transmission signal group 102.
Output as a logic level instruction signal 108.
It has become so.

Next, the arithmetic unit 106 determines whether or not the number of pairs in which the content of the data 101 to be transferred next and the state of the corresponding data transmission signal group 102 are different is more than half. If the number of pairs exceeds half, the logic level instruction signal 107 is output as a low level,
Otherwise outputs a logical level indicating signal 107 as a high level.

Next, the arithmetic unit 106 determines whether or not the number of pairs in which the content of the data 101 to be transferred next and the state of the corresponding data transmission signal group 102 are different from each other is more than half. If the number of pairs exceeds half, the logic level instruction signal 107 is output as a low level,
Otherwise, the 107 logic level instruction signal is output as a high level.

The logic level instruction signal 107 indicates that data transmission is performed by positive logic at a high level, and that data transmission is performed by negative logic at a low level. next,
The EXNOR 105 converts the logic level of the input data 101 according to the logic level instruction signal 107.

Finally, in synchronization with the rise of the output signal 103, the D flip-flop 104 outputs the data whose logic level has been converted by the EXNOR 105 to the data transmission signal group 102, and the D flip-flop 104a
A signal indicating the logical level of the data output to data transmission signal group 102 is output as logical level instruction signal 108.

All five data transmission signal groups 102 are high.
It is assumed that all of the data 101 to be transferred next are at the low level. In this case, data 1
Since the number of pairs of 01 and the data transmission signal group 102 is different from each other and exceeds half, the arithmetic unit 106 outputs a logic level instruction signal 107 as a low level, and the next data transmission is performed by negative logic. Is shown. Row entered
The EXNOR 105 converts the level data 101 into negative logic. Therefore, even when the output control signal 103 rises, the five data transmission signal groups 102 remain unchanged at the high level.

The circuit that receives the data transmission signal group 102 can easily reproduce the data 101 by receiving the logic level instruction signal 108 at the same time.

[0026] (Embodiment 2) FIG. 3 is a diagram illustrating a data transmission circuit in the dynamic circuit according to the second embodiment of the present invention. FIG. 4 is a timing chart showing the operation timing of the circuit diagram of FIG.

In FIG. 3, reference numeral 301 denotes data to be transferred next; 302, a data transmission signal group; 303, an output control signal indicating the timing of outputting the next data to the data transmission signal group; This is a precharge signal that indicates the timing for precharging 302.

305 is an EXOR for setting the logical level of the data to be transferred next, 306 is an arithmetic unit for determining the logical level of the data to be transferred next, and 307 indicates the logical level of the data to be transferred next. A signal 308 is a logical level instruction signal of the transfer data. EXOR305, P
Some of the gate circuits 3 including the channel and the N-channel MOSFET have the same configuration, although the internal configuration is partially omitted. In addition, the level instruction gate circuit 3
a is a logic level instruction signal 307 from the arithmetic unit 306
Based on the precharge signal 304 and the output control signal 303.
The data output to the data transmission signal group 302
A signal indicating the logic level of the data
Output. For level indication
The gate circuit 3a has the same configuration as the gate circuit 3.
You.

In this example, the width of the data to be transferred is five. First, data 301 to be transferred next is input to the EXOR 305 as five signals. Next, the arithmetic unit 306 determines whether or not the number of low levels in the data 301 to be transferred next exceeds half, and if the number of low levels exceeds half, the logical level instruction signal 30
7 is output as a low level; otherwise, the logic level instruction signal 307 is output as a high level.

The logic level instruction signal 307 indicates that data transmission is performed by positive logic at a high level, and that data transmission is performed by negative logic at a low level. next,
The EXOR 305 converts the logic level of the input data 301 according to the logic level instruction signal 307. At the same time, the precharge signal 304 is input as a low level, and the data transmission signal group 302 is precharged and becomes a high level. Thereafter, the precharge signal 304 changes to a high level, but the data transmission signal group 302 holds data by a parasitic capacitance on a wiring or a gate.

Finally, when the output control signal 303 is input as a high level and the output of the EXOR 305 is at a high level, the discharge is performed and the data transmission signal group 30 is output.
2 is outputted as a low level, otherwise discharged along with the data transmission signal group 302 is not performed continuously held as the high level precharged, the logic of the data being output to the data transmission signal group 3 02 A signal indicating the level is output as a logic level instruction signal 308.

Next, consider a case where all five data 301 to be transferred are at the low level. In this case, data 30
The arithmetic unit 306 outputs the logic level instruction signal 30 as a low level since all five of the five are low.
7 is output, indicating that the next data transmission is performed with negative logic. The input low level data 301 is EXO
It is converted to negative logic by R305.

Therefore, even if the output control signal 303 is at the high level, none of the five data transmission signal groups 302 are discharged, and the precharged high level is maintained and does not change.

The circuit that receives the data transmission signal group 302 can easily reproduce the data of 301 by receiving the logic level instruction signal 308 at the same time.

Although the above description has been made with respect to five data transmission signal groups as an example, the present invention is not limited to this. It is apparent that similar effects can be obtained even if the number of data transmission signal groups is arbitrary. is there.

[0036]

As described above, according to the data transmission circuit of the present invention, the number of data transmission signal groups that change can be reduced, the current consumption is not increased temporarily, and the ground bounce is reduced. The effect that hardly occurs can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of a circuit diagram according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart of a circuit diagram according to a second embodiment.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a timing chart of a circuit diagram of a conventional example.

FIG. 7 is a circuit diagram showing a conventional example.

FIG. 8 is a timing chart of a circuit diagram of a conventional example.

[Explanation of symbols]

101 Data to be Transferred Next 102 Data Transmission Signal Group 103 Output Control Signal Instructing Data Output Timing 104 D Flip-Flops 105 Converting Logical Level of Data to be Transferred Next
XNOR 106 Arithmetic unit that determines logical level of data to be transferred next 107 Signal indicating logical level of data to be transferred next 108 Logical level instruction signal of transfer data 301 Data to be transferred next 302 Data transmission signal group 303 Data output control signal 304 Signal for instructing precharge of data transmission signal group 305 E for setting the logic level of data to be transferred next
XOR 306 Arithmetic unit 307 for determining logical level of data to be transferred next 307 Signal indicating logical level of data to be transferred next 308 Logical level indicating signal of transferred data

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 25/02 G06F 3/00 H04L 29/00

Claims (2)

(57) [Claims] 1. A circuit for transmitting a plurality of bits of data to the inside or outside of an electronic device, comprising: a signal line group, a determination unit, a signal line, and an output unit. The decision means decides the logic level of the signal output to the signal line group with the target data as input, and the signal line determines the logic level of the signal decided by the decision means. The output means converts the logic level of the target data according to the decision of the decision means, and outputs the data to the signal line group so that the logic inversion does not exceed half of each data of the signal line group. A data transmission circuit for outputting data. 2. An arithmetic unit, a data output gate circuit,
A circuit for transmitting a plurality of bits of data to the inside or outside of the electronic device, the arithmetic unit comprising: a logic level of each data to be transferred next; It is determined whether or not the number of pairs having different logical levels of each data of the transmission signal group exceeds half, and if the number of different pairs exceeds half, the logical level indication signal is lowered.・ Output as level,
If the number of said different pairs does not exceed half,
A logic level instruction signal is output as a high level.The data output gate circuit converts a logic level of data to be transferred next, based on a logic level instruction signal from the arithmetic unit, The previous data is stored during a period until the output of the next data is instructed by the output control signal, and the data whose logic level has been converted is output to the data transmission signal group in synchronization with the output control signal. The level instruction gate circuit receives a logical level instruction signal and an output control signal from the arithmetic unit as inputs, and uses a signal representing a logical level of data output to a data transmission signal group as a logical level instruction signal. A data transmission circuit for outputting data.