JP2947084B2 - Noise reduction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-precision noise reduction circuit for removing a noise component of an input video signal including a time axis fluctuation with a simple configuration.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram for explaining a conventional noise reduction circuit, and FIG. 10 is a diagram showing signal waveforms at various parts of the conventional noise reduction circuit.

As shown in FIG. 9, a conventional noise reduction circuit includes a synchronizing signal separating circuit 2 for separating a synchronizing signal from an input video signal supplied from a transmission line (not shown), and a synchronizing signal obtained by the synchronizing signal separating circuit 2. A PLL circuit 18 that outputs a clock signal synchronized with the signal (for example, a signal having a frequency that is N times the frequency of the synchronization signal) includes a clock signal output from the PLL circuit 18 and a synchronization signal obtained by the synchronization signal separation circuit 2. A frame memory control circuit 19 for generating and outputting a control signal for controlling the operation of the frame delay circuit 4 based on the video signal supplied by the control signal output from the frame memory control circuit 19, and a delayed video delayed by one frame period A frame delay circuit 4 for outputting a signal; a subtracter 5 for subtracting the delayed video signal from the input video signal; A motion detection circuit 7 for detecting a change in a signal, subtracting the detection result of the motion detection circuit 7 from the input video signal and supplying the subtraction result as an output video signal to a transmission path (not shown) and the frame delay circuit 4 described above. And a vessel 8.

Here, the PLL circuit 18 is a well-known phase-locked loop circuit. The PLL circuit 18 outputs a synchronizing signal supplied to a phase detector 18a and a signal supplied from a voltage control oscillator 18b via a 1 / N circuit 18c. The phase is compared, and the error voltage is supplied to the voltage control transmitter 18b.
Supplies a signal having a frequency N times the frequency of the synchronizing signal for reducing the error voltage to the frame memory control circuit 19 as a clock signal. At this time, the PLL circuit 1
The clock signal output by 8 is synchronized with the synchronizing signal, and is further supplied to the frame memory control circuit 19 as a signal having a frequency that is N times the frequency of the synchronizing signal. Based on the synchronization signal and the clock signal synchronized with the synchronization signal, the frame memory control circuit 19 performs writing and reading of the memory included in the frame delay circuit 4, and determines the phase between the delay time of the frame delay circuit 4 and the frame period of the video signal. Are synchronized.

A transmitted video signal is obtained as a moving image by continuously processing a still image that changes in a frame unit, and the still images in the preceding and following frame units have a correlation. At this time, a signal component having a correlation between the preceding and following still images is determined to be main information of the video signal, but a signal component having no correlation is a noise component (noise component) included in the video signal.

Therefore, the input video signal is stored in a frame memory constituted by the frame delay circuit 4, and a delayed video signal is output at a timing delayed by one frame period, and the subtractor 5 subtracts the delayed video signal from the input video signal. By doing so, correlated signal components cancel each other out, and uncorrelated signal components (that is, noise components) are obtained.
The noise component is removed by subtracting this from the input video signal in the subtractor 8 via the motion detection circuit 7.

At this time, if the input video signal contains jitter, the jitter causes a delay between the delay time of the frame delay circuit 4 and the frame period of the video signal.
As shown in FIG. 0, the correlation between the input video signal ((A) in the figure) and the delayed video signal ((B) in the figure) is lost, and the frame difference ((C) in FIG. It is supplied to the circuit 7.

Here, the frame difference has a signal component of "0" when there is no motion in the input video signal, and when there is motion, it is obtained as information corresponding to motion between the input video signal and the delayed video signal. . However, due to the jitter of the input video signal, a frame difference occurs even if the input video signal does not originally move. The above-described motion detection circuit 7 is a non-linear circuit that cuts signal components of a predetermined level or higher, but obtains a signal component near zero level from the frame difference (FIG. 3D).

When the protruding signal component shown in FIG. 10D is subtracted from the input video signal by the subtractor 8,
An uncorrelated signal component becomes an interference signal and overlaps with the current video signal, deteriorating the S / N of the video signal, or an interference signal that is not an original video signal such as a so-called ghost.

[0010]

At this time, the above P
The use of the LL circuit 18 has the disadvantage of increasing the cost in terms of the circuit configuration. In a current electronic device in which the circuit is becoming more and more LSI, a simple noise reduction circuit suitable for the LSI is provided by using the configuration without using the PLL circuit 18. Was required.

Also, since the jitter of the input video signal is included in the clock signal used in the system, for example, a digital signal processing circuit and a noise reduction circuit for processing a carrier chrominance signal with a clock signal multiplied by a carrier wave. There is a drawback that digital signals cannot be exchanged between digital devices.

In such a case, a circuit configuration is required to obtain a video signal by re-sampling based on a clock signal having no jitter, and there has been a disadvantage that the circuit configuration is costly.

Further, it is clear that the interference signal component shown in FIG. 10D increases in proportion to the jitter of the video signal, and the above-described interference signal is based on a clock signal irrelevant to a synchronization signal containing the jitter. There has been a demand for a noise reduction circuit that suppresses the effect of the noise.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a noise reduction circuit having the following configurations (1) and (2). (1) In a video signal noise reduction circuit that removes noise by a field / frame delay utilizing a field or frame correlation of an input video signal including time axis fluctuation, a field for storing and outputting a video signal in field / frame units / Frame delay means, motion detection means for detecting a motion of a video signal from a subtraction result of the input video signal and a signal output from the field / frame delay means, and a synchronization signal separated from the input video signal. Control means for controlling the field / frame delay means on the basis of a clock signal generated and output by clock signal generation means irrelevant to the input video signal; and an output signal of the motion detection means, An output video signal is obtained by subtracting the output video signal from A noise reduction circuit for supplying the noise to the frame / frame delay means. (2) The noise reduction circuit according to (1), wherein a filter means for removing a high-frequency signal component is provided at a stage preceding the motion detection means for detecting the motion of the video signal.

[0015]

1 is a block diagram for explaining a noise reduction circuit according to the present invention, FIG. 2 is a block diagram for explaining control means which is a main part of the present invention, and FIG. FIG. 4 is a timing chart for explaining the timing of address reset of the control means, FIG. 5 is an equalization circuit diagram for explaining the operation of the frame delay means, and FIG. 6 outputs a delayed video signal. FIG. 7 is a diagram for explaining the characteristics of the equalization circuit, FIG. 7 is a diagram showing signal waveforms of respective parts of the noise reduction circuit according to the present invention, and FIG. 8 is a diagram for explaining the overall characteristics of the noise reduction circuit according to the present invention. It is a block diagram.
The same components as those described above are denoted by the same reference numerals, and the description thereof will be omitted.

Now, the noise reduction circuit according to the present invention will be described with reference to the drawings. First, as shown in FIG. 1, the noise reduction circuit performs synchronization from an input video signal supplied from a transmission line (not shown). A synchronizing signal separating circuit 2 for separating signals, and a control means (frame, described later) for generating and outputting a control signal based on the synchronizing signal obtained by the synchronizing signal separating circuit 2 and the clock signal generated and output by the clock signal generating means 3 A memory control circuit) 1 for storing (writing) a video signal based on the control signal output from the frame memory control circuit 1 and outputting (reading) a delayed video signal delayed by one frame period to the frame memory control circuit 1 A frame delay means (frame delay circuit) 4 configured, a subtracter 5 for subtracting the delayed video signal from the input video signal, and an output of the subtractor 5 A low-pass filter 6 for removing an error signal component by removing a high-frequency component of the result (frame difference), a motion detection circuit 7 for detecting a change in a video signal from an output result of the low-pass filter 6, and a motion detection from the input video signal It comprises a subtraction unit 8 for subtracting the detection result of the circuit 7 and supplying the subtraction result as an output video signal to the frame delay circuit 4 and a transmission line (not shown).

The clock signal generated and output by the clock signal generating means 3 generates a clock signal independent of the synchronizing signal of the input video signal, and includes an oscillator (not shown). This clock signal is supplied to the frame memory control circuit 1 together with the synchronization signal obtained by the synchronization signal separation circuit 2 described above.

As shown in FIG. 2, the frame memory control circuit 1 generates a vertical / horizontal address reset signal and a vertical / horizontal enable signal from the supplied clock signal and synchronization signal. A generation circuit 11, a read address counter 13 for controlling a read operation of a frame memory of a frame delay circuit 4 described later by a logical product of a vertical / horizontal enable signal and a vertical / horizontal address reset signal, and a logical product of the above enable signal and the above Delay circuits 14a, 14b, 14 for respectively delaying the set address reset signal by a predetermined period.
c, a write address counter 15 for controlling a write operation of the frame memory by a logical product of enable signals output from the delay circuits 14a to 14c and a vertical / horizontal address reset signal.

Here, the delay circuits 14a to 14c
For example, a signal delay that occurs while an input signal is output as an output signal via a circuit, which reversely corrects the amount of signal transmission delay determined on the hardware that constitutes the circuit. Can be omitted.

Here, the above-mentioned frame delay circuit 4
Is shown as being configured in the frame memory control circuit 1, but it is a matter of course that the configuration is not limited to this.

As shown in FIG. 3, the timing generation circuit 11 converts a vertical synchronizing signal (FIG. 3B) from a supplied video signal (FIG. 3A) into a vertical address reset signal (FIG. 3B). C); output at an interval of two fields / one frame in synchronization with a vertical synchronizing signal interposed in the video signal), a vertical enable signal ((D) in FIG. 9; "H" level for a predetermined period after detection of the vertical synchronizing signal) Is generated and output, and a horizontal address reset signal (FIG. 10F) and a horizontal enable signal (FIG. 10G; horizontal synchronization signal) are obtained from the horizontal synchronization signal inserted in the video signal (FIG. 10E). "H" for a predetermined period after detection
Level) is generated and output.

The vertical / horizontal enable signal is supplied to the logic circuit 12 in synchronization with the input synchronizing signal, and a read instruction of the read address counter 13 is performed by a logical product of the enable signals. At this time, the above-described vertical enable signal is a signal for controlling the read operation of the read address counter 13 so that the signal components for the number of vertical lines transmitted during the field period of the video signal when "H" are read from the frame memory described later. When the horizontal enable signal is "H", the read address counter 13 counts a predetermined address so that signal components corresponding to the number of horizontal pixels of the video signal transmitted during the line period of the video signal are read from a frame memory described later. This is a signal to be controlled. Each of the vertical / horizontal enable signals is "H" during a period in which the video information is transmitted.

Here, the above-described logic circuit 12 performs an AND operation to suspend the operations of the above-described read address counter 13 and write address counter 15 during a period in which no video signal exists in the vertical and horizontal directions within the frame period. This is for efficiently transmitting the vertical and horizontal enable signals, and can be omitted theoretically.
The frame memory is a storage circuit of the video signal configured in the frame delay circuit 4 described above, and a digital memory circuit that stores and holds, as digital signals, signal components corresponding to the number of vertical lines and the number of horizontal pixels of the video signal, respectively. It is. That is, it writes and reads the video signal supplied in accordance with the instructions from the read address counter 13 and the write address counter 15, respectively.

These vertical / horizontal enable signals are supplied to the write address counter 15 at a timing delayed by a predetermined period by the delay circuit 14a, and a write instruction is issued. According to this instruction, the output video signal supplied to the frame delay circuit 4 at this time is stored.

On the other hand, a vertical address reset signal (FIG. 3D) is supplied to the read address counter 13 and the write address counter 15 in synchronization with the timing of the vertical synchronizing signal, and the vertical line of the video signal is switched. At this time, as described above, the timing of the vertical address reset signal supplied to the write address counter 15 is delayed by a predetermined period from the timing supplied to the read address counter 13 via the delay circuit 14b. If the delay circuit 14b is omitted, the read address counter 13 and the write address counter 15 are reset simultaneously by the vertical address reset signal.

Similarly, the horizontal address reset signal (FIG. 3 (F)) is supplied to the read address counter 13 and the write address counter 15 in synchronization with the timing of the horizontal synchronizing signal.
Supplied to At this time, when a vertical line to be read by the read address counter 13 is specified by the above-described vertical address reset signal, the read address counter 13
Starts reading and counting horizontal pixels on the vertical line, and when a vertical line to be written by the write address counter 15 is designated, the write address counter 15 starts writing and counting horizontal pixels on the vertical line.

Here, since the video signal read by the read address counter 13 is an output video signal stored in the frame delay circuit 4 before the video signal read by the write address counter 15, the output video signal is The output delayed video signal is always delayed by one frame period.

The delayed video signal output from the frame delay circuit 4 is added to the input video signal for one frame period (+
The control is performed at intervals following the delay periods of the delay circuits 14a to 14c). However, as shown in FIG. 4, since the synchronization signal obtained from the input video signal and the clock signal that is not synchronized have a time shift ΔΤ of one cycle or less of the clock signal, the delay time of the frame delay circuit 4 is also ΔΤ.
Will be included. That is, in FIG. 7, a delayed video signal (FIG. 7B) shifted from the input video signal (FIG. 7A) by a time ΔΤ is obtained.

Therefore, the delayed video signal output from the frame delay circuit 4 is subtracted from the input video signal in the subtracter 5, and as shown in FIG.
The frame difference is considerably reduced as compared with (ideally, the smaller the time axis fluctuation, the smaller the frame difference, so that the information related to the original video signal is maintained and the noise component having no correlation can be removed. it can).

A frame difference having an error of time ΔΤ is equivalent to the output of the circuit shown in FIG. This circuit obtains an output signal obtained by subtracting the input signal from the input signal delayed by the ΔΤ delay circuit 16, and has a high-pass filter as shown in FIG. That is, for example, the frequency of the input signal is 1 /
The error signal level increases up to the high-frequency component of 2ΔΤ (the S / N of the video signal is deteriorated, or a non-original video signal such as a so-called ghost is generated).

Therefore, as shown in FIG. 1, the output signal of the subtracter 5 is supplied to a low-pass filter 6. Therefore, FIG.
(D), the high-frequency error signal component output from the subtractor 5 is removed. Therefore, when the signal component of a predetermined level or more is cut by the motion detection circuit 7, the above-mentioned signal is reduced near zero level. Since the signal component can be suppressed, the S / N of the video signal is degraded, and at the same time, a disturbing signal other than the original video signal such as a so-called ghost can be prevented.

As described above, the present noise reduction circuit can reduce the noise of the input video signal in accordance with the error ΔΤ, which is a time-varying component. By shortening the interval of Δ を, noise can be more accurately removed.

Since the frequency distribution of the noise component has the same frequency distribution as the characteristic of the low-pass filter through the low-pass filter 6 described above, the degree of improvement of the noise component of the noise reduction circuit depends on the band of the low-pass filter 6. fc, and this band fc is determined according to the amount of the error signal caused by the error ΔΤ. Therefore, the overall characteristics of the present noise reduction circuit are to selectively remove noise components at relatively low frequency levels as shown in FIG. 8, but at signal frequencies exceeding the band fc, the error signal level increases and Since the S / N improvement of the present noise reduction circuit is low, the above interference signal can be removed by suppressing the influence of the jitter of the input video signal by not using a signal frequency higher than the band fc.

Although a cyclic noise reducer (noise reduction circuit) using a frame delay has been described here, a field delay may be used instead of a frame delay.

It should be noted that a noise reducer using a non-recursive frame / field delay may naturally remove noise of a relatively low frequency component of a video signal as in the present noise reduction circuit. is there.

[0036]

As described above, according to the configuration of the present invention, the frame is delayed by the clock signal independent of the synchronization signal of the input video signal.
Since noise removal using the frame correlation of the video signal can be performed irrespective of the jitter included in the input video signal, a noise reduction circuit having a simple configuration suitable for an LSI without using a PLL circuit can be realized. This has the effect.

Further, as described above, a video signal processing circuit that performs digital signal processing that does not allow jitter by performing frame delay by using a clock signal that is independent of a synchronization signal of an input video signal is intended to remove this jitter. Since the configuration for resampling the clock signal including jitter is not required, there is an effect that the digital signal can be transferred between the digital video signal processing circuit and the noise reduction circuit.

According to the second aspect of the present invention, in addition to the above-described effects, a relatively low frequency signal having a relatively low frequency can be used without using an interference signal of a high frequency component of a video signal generated by a frame delay error. By removing the noise component, there is an effect that the noise component of the video signal can be accurately removed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a noise reduction circuit according to the present invention.

FIG. 2 is a block diagram for explaining a control unit which is a main part of the present invention.

FIG. 3 is a timing chart for explaining an operation of a control unit which is a main part of the present invention.

FIG. 4 is a timing chart for explaining an address reset timing of a control unit which is a main part of the present invention.

FIG. 5 is an equalization circuit diagram for explaining the operation of the frame delay means.

FIG. 6 is a diagram for explaining characteristics of an equalization circuit that outputs a delayed video signal.

FIG. 7 is a diagram showing a signal waveform of each part of the noise reduction circuit according to the present invention.

FIG. 8 is a block diagram for explaining overall characteristics of the noise reduction circuit according to the present invention.

FIG. 9 is a block diagram for explaining a conventional noise reduction circuit.

FIG. 10 is a diagram showing signal waveforms of various parts of a conventional noise reduction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control means (frame memory control circuit) 3 Clock signal generation means 4 Frame delay means (frame delay circuit) 7 Motion detection means (motion detection circuit)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/14-5/217

Claims (2)

(57) [Claims] 1. A video signal noise reduction circuit for removing noise by a field / frame delay utilizing a field / frame correlation of an input video signal including a time axis fluctuation, wherein the video signal is stored in units of fields / frames and output. A field / frame delay unit that performs a motion detection; a motion detection unit that detects a motion of a video signal from a subtraction result of the input video signal and a signal output from the field / frame delay unit; and a synchronization separated from the input video signal. Signal and a clock signal generated and output by clock signal generation means irrelevant to the input video signal.
Control means for controlling a frame delay means; obtaining an output video signal obtained by subtracting the output signal of the motion detection means and the input video signal, and supplying the output video signal to the field / frame delay means A noise reduction circuit characterized in that: 2. The noise reduction circuit according to claim 1, wherein a filter means for removing a high-frequency signal component is provided before the motion detection means for detecting the motion of the video signal.