JP2950183B2 - Video signal receiving circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit for an EDTV2 signal transmitted in a letterbox format in which an identification signal and a video augmentation signal are multiplexed while being compatible with an existing NTSC signal.

[0002]

2. Description of the Related Art In recent years, with the spread of large-sized televisions, it has become essential to provide high-definition images, and EDTVs (Enhas) that perform high image quality processing on both the transmitting side and the receiving side are required.
nced Definition Telovios
n) are being studied.

At present, EDTV2, which supports a wider screen of 16: 9, is scheduled to start broadcasting in the summer of 1995.

[0004] The EDTV2 signal is the EDT on the 22nd line.
In addition to the V2 identification signal and the letterbox format video signal, a horizontal resolution enhancement signal is multiplexed in the video signal, and a total of three enhancement signal components of a vertical time resolution enhancement signal and a vertical resolution enhancement signal are multiplexed in upper and lower non-image portions. Have been. The EDTV2 receiving circuit adds the above three augmentation signals to the video signal and
Display on the screen of 6: 9.

[0005] The configuration of the EDTV2 receiving circuit is widely described in the Journal of the Institute of Television Engineers of Japan, etc. Here, a conventional example will be described with reference to FIGS. 3 and 4.

FIG. 4 is a block diagram showing a conventional example of an EDTV2 signal receiving circuit, wherein 1 is an EDTV2 signal input terminal, 2 is an identification signal demodulating circuit for demodulating an EDTV2 identification signal on the 22nd line, and 3 is an identification control signal. An output terminal 4, a Y / C separation circuit 4 for separating a luminance signal and a color signal, a HH reproduction circuit 5 for demodulating and adding an HH signal, a color signal demodulation circuit 6 for demodulating a color signal, and a scanning from a color difference signal 7. A scanning line interpolation circuit for generating a line interpolation signal, 8 is a vertical enlargement circuit for enlarging the screen position of the color difference signal, 9 is a double speed conversion circuit for converting to sequential scanning, 10 and 11 are output terminals for the color difference signal, and 14 is a vertical time. VT for demodulating, separating and reproducing resolution enhancement signal / VT
VH reproduction circuit, 13 is a scanning line interpolation circuit that generates a scanning line interpolation signal from a luminance signal, 20 is a first 1H line memory, 21 is a vertical low-pass filter that extracts a vertical low-frequency component, and 22 is a horizontal low-frequency filter. A low-pass filter for extracting components; 24, a first adder; 23, a second adder; 25, a second 1H line memory; 27, a horizontal high-pass filter for extracting horizontal high-pass components; 39 is the sixth 1H line memory, 40 is the seventh 1H line memory, 41 is the eighth 1H line memory
A line memory, 29 is an edge detection circuit for extracting a vertical edge component from the signal of three lines, 31 is a third adder,
Reference numeral 30 denotes a fourth adder, 16 denotes a vertical expansion circuit for expanding the screen position of a luminance signal, 33 denotes a VH expansion memory for expanding VH, 35 denotes a fourth 1H line memory, and 36 denotes a fifth line memory.
1H line memory, 37 is a vertical expansion circuit for generating an interpolation signal for expanding VH in the vertical direction, 38 is a vertical frequency shift circuit for restoring the transmitted vertical resolution enhancement signal shifted to a low frequency, and 18 Is the fifth adder, 19
Is a sixth adder, 17 is a double speed conversion circuit for converting a luminance signal into a sequential scan, 12 is an output terminal of a luminance signal, 46 is a VT addition circuit for superimposing a vertical time resolution enhancement signal on the luminance signal, and 45 is a luminance signal A V peaking circuit 15 for adding a vertical edge component of VH is a VH expansion circuit 15 for expanding the vertical resolution enhancement signal in the vertical direction.

A conventional example of the EDTV2 signal receiving circuit having such a configuration will be described. The signal input from the EDTV2 signal input terminal 1 is first demodulated and reproduced by the discrimination control signal demodulation circuit 2, and the chrominance signal multiplexed with the horizontal low-frequency component of the luminance signal by the Y / C separation circuit 4 and the horizontal resolution The VT / VH reproduction circuit 14 separates and reproduces the signal into a vertical time resolution reinforcement signal and a vertical resolution reinforcement signal. The multiplexed color signal and the horizontal resolution enhancement signal and the horizontal resolution enhancement signal of the luminance signal separated by the Y / C separation circuit 4 are separated by an HH reproduction circuit 5 into a luminance signal and a color signal whose band is extended by the horizontal resolution enhancement signal. Is done. The color signal separated by the HH reproduction circuit 5 is demodulated into a color difference signal by a color demodulation circuit 6, a scanning line interpolation signal is generated by a scanning line interpolation circuit 7, and a vertical enlargement circuit 8 enlarges a screen position in a vertical direction. The data is converted into sequential scanning by the double speed conversion circuit 9 and output from the color difference signal output terminals 10 and 11. The HH reproduction circuit 5
The luminance signal separated by is generated by the scanning line interpolation circuit 13 to generate a scanning line interpolation signal, and the VT addition circuit 46 superimposes the vertical time resolution reinforcement signal reproduced by the VT / VH reproduction circuit 14,
A V-peaking circuit 45 detects and adds a vertical edge component and adds a signal obtained by vertically expanding a screen position by a vertical enlargement circuit 16 and a vertical resolution enhancement signal reproduced by a VT / VH reproduction circuit 14 to a VH enlargement circuit. And the signal enlarged in the vertical direction is added by a fifth adder and a sixth adder 19,
The data is converted into a sequential scan by the double speed conversion circuit 17 and output at the luminance signal output terminal 12.

FIG. 3 is a block diagram showing a conventional example of a V peaking circuit. FIG. 3A is a schematic diagram of edge detection, and FIG. 3B is a V peaking circuit. The V peaking circuit has the same configuration as the V peaking circuit 45. As shown in FIG. 3A, a vertical edge component is detected by using the lines E and D for detecting the edge of the line C and the lines C and A for detecting the edge of the line D. Is detected and added. Figure 3
(B) A 3H line memory is required as shown in the V peaking circuit.

[0009]

Here, the V peaking circuit, which is not defined in the broadcasting system of EDTV2, has an effect of correcting blurring when vertically enlarged to a large screen, and is an indispensable technique. . Also, it is conceivable that the vertical resolution augmentation signal, which is the EDTV2 augmentation signal, is not sent by the broadcast station. Therefore, in the conventional configuration of the EDTV2 receiving circuit, a 2H line memory and a VH
The H enlargement circuit 15 requires a 2H line memory, and the V peaking circuit 45 requires a 3H line memory, that is, a total of 7H line memories.

The present invention has been made in view of the above-mentioned problems, and has the advantage that the line memory of the V peaking circuit is shared with the line memory of the VT addition circuit, and the line memory of the V peaking circuit is provided with a vertical resolution by a VH reproduction / V peaking switching signal. A video signal receiving apparatus which suppresses an increase in the amount of circuits by sharing the line memory of the VH expansion circuit without performing the reinforcement signal reproduction.
It is intended to provide a communication circuit .

[0011]

In order to achieve this object, the present invention relates to an input / output signal of a first 1H line memory for delaying an edge detection of a V peaking circuit by 1H from a current scanning line signal of a VT addition circuit. Based on the output of the second 1H line memory for delaying the scanning line interpolation signal by 1H and the output of the third 1H line memory for delaying the output of the second 1H line memory by 1H, add a vertical temporal resolution enhancement signal, V peaking , VH enlargement processing, and the edge detection of the V peaking circuit is performed without using the third line memory, by using the VH reproduction / V peaking switching signal, and without performing the vertical resolution enhancement signal reproduction. By having the first switching device sharing the output of the fourth line memory, the first switching device that delays the current scanning line signal of the VT adding circuit by 1H is provided.
1H line memory input / output signal and scanning line interpolation signal
A vertical edge component is detected based on the output of the second 1H line memory that delays by H, and a vertical time resolution reinforcement signal is added;
It has a configuration to make V peaking compatible.

[0012]

With this configuration, the present invention shares the line memory for edge detection of the V peaking circuit with the line memory of the VT addition circuit, thereby reducing the 2H line memory compared to the conventional EDTV2 reception circuit while reducing the VT addition circuit. , V
Peaking and VH enlargement processing are compatible, and the line memory for edge detection of the V peaking circuit is VH reproduction / VH
By having a switch shared with the line memory of the VH expansion circuit without reproducing the vertical resolution enhancement signal by the peaking switching signal, it is possible to reduce the 3H line memory while adding the vertical time resolution enhancement signal and V peaking. Can be done.

[0013]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 1 is an EDTV2 signal input terminal, and 2 is an EDTV on the 22nd line.
2 an identification signal demodulation circuit for demodulating an identification signal, 3 an identification control signal output terminal, and 4 a Y / C for separating a luminance signal and a chrominance signal.
A separation circuit, a HH reproduction circuit for demodulating and adding an HH signal, a color signal demodulation circuit for demodulating a color signal, a scanning line interpolation circuit for generating an interpolation scanning line from a current scanning line of a color difference signal, A vertical enlargement circuit that enlarges the screen position of the color difference signal,
9 is a double-speed conversion circuit for converting to sequential scanning, 10 and 11 are output terminals for color difference signals, 14 is a VT / VH reproduction circuit for demodulating, separating and reproducing VT / VH, 13 is interpolation scanning from the current scanning line of the luminance signal. A scanning line interpolating circuit for generating a line;
1H line memory, 21 is a vertical low-pass filter for extracting vertical low-pass components, 22 is a horizontal low-pass filter for extracting horizontal low-pass components, 24 is a first adder, 2
3 is a second adder, 25 is a second 1H line memory, 2
7 is a horizontal high-pass component filter for extracting a horizontal high-pass component, 26 is a third 1H line memory, 29 is an edge detection circuit for extracting a vertical edge component from a 3H signal, 31
Is a third adder, 30 is a fourth adder, 44 is a VT addition / V peaking circuit, 16 is a vertical enlargement circuit for expanding the screen position of the luminance signal, and 15 is a vertical enlargement of the vertical resolution enhancement signal. VH expansion circuit, 18 is a fifth adder, 19
Is a sixth adder, 17 is a double-speed conversion circuit for converting to sequential scanning, and 12 is an output terminal for a luminance signal.

The operation of the video signal receiving circuit configured as described above will be described. First, input EDTV
The two signals are separated by a Y / C separation circuit 4 into a luminance signal and a chrominance signal. Further, the HH reproduction circuit 5 reproduces the horizontal high-frequency luminance component and adds the luminance component to the luminance signal. The color signal C passes through a color demodulation circuit 6, a scanning line interpolation circuit 7, a vertical enlargement circuit 8, and a double-speed conversion circuit 9 to obtain a double-speed color signal vertically enlarged to 16: 9.

The scanning line interpolation circuit 13 generates an interpolation scanning line signal necessary for double-speed conversion from the luminance signal whose horizontal resolution has been enhanced by the HH reproducing circuit 5. Next, in a VT addition / V peaking circuit 44, a VT signal which is a vertical resolution reinforcement signal is added, and vertical contour correction is performed. In this block, first, in order to add a VT signal, the current scanning line signal is delayed in the first 1H line memory 20, and the SSKF filter processing for reinforcing the interpolation scanning line in the main image portion is vertically performed using the signals before and after the current scanning line signal. After performing the processing with the low-pass filter 21, the horizontal low-pass filter 22 extracts the horizontal low-pass component.
An interpolation scanning line reinforcement signal of 1 MHz or less is obtained. By adding this signal to the interpolated scanning line reinforcement signal reproduced from the non-image portion by the VT / VH reproducing circuit 14, the interpolated scanning line VT signal can be reproduced. Here, after the delay of the interpolated scanning line signal obtained by interpolating the scanning line in the second 1H line memory 25, the interpolated scanning line signal is passed through a horizontal high band component passing filter 27 for extracting a horizontal high band component of 1 MHz or more. Removes low frequency components. By adding the main image portion interpolation scanning line signal and the interpolation scanning line VT signal in the first adder 24, an interpolation scanning line signal reproduced by VT can be obtained.

The second adder 23 adds the current scanning line signal delayed by the first 1H line memory 20 and the current scanning line VT signal reproduced by the VT / VH reproducing circuit 14 so that VT is obtained. A reproduced current scanning line signal can be obtained.

Here, V peaking can be realized using the 1H line memory for reproducing the VT signal described above. The operation will be described below with reference to FIG.

First, the input and output signals of the first 1H line memory 20 used for VH addition are applied to the edge detection circuit 2.
Enter 9 This signal corresponds to the A and C signals in FIG. Next, the input and output signals of the newly added third 1H line memory 26 are input to the edge detection circuit 29. This signal corresponds to the D and E signals in FIG. Based on the above signals, the vertical edge components of the C and D signals are detected as shown in FIG.
V peaking can be realized by adding the signal to the VT-reproduced signal by the adder.

As described above, according to the present embodiment, the configuration is such that the vertical edge component is detected from the signal before VT addition, and the 1H line memory for VT addition can be used without adding two new 1H line memories. By also using them, VT addition and V peaking can be realized. VT
In the detection of the vertical edge component based on the signal before the addition, substantially the same characteristics as those of the conventional edge detection after the addition of the VT can be obtained.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings. In FIG.
1 is an EDTV2 signal input terminal, and 2 is an ED on the 22nd line.
An identification signal demodulation circuit for demodulating a TV2 identification signal, 3 is an identification control signal output terminal, and 4 is a Y for separating a luminance signal and a chrominance signal.
/ C separation circuit, 5 is an HH reproduction circuit for demodulating and adding an HH signal, 6 is a color signal demodulation circuit for demodulating a color signal, 7 is a scanning line interpolation circuit for generating an interpolation scanning line from the current scanning line of the color difference signal, 8 is a vertical enlargement circuit for enlarging the screen position of the color difference signal,
9 is a double-speed conversion circuit for converting to sequential scanning, 10 and 11 are output terminals for color difference signals, 14 is a VT / VH reproduction circuit for demodulating, separating and reproducing VT / VH, 13 is interpolation scanning from the current scanning line of the luminance signal. A scanning line interpolating circuit for generating a line;
1H line memory, 21 is a vertical low-pass filter for extracting vertical low-pass components, 22 is a horizontal low-pass filter for extracting horizontal low-pass components, 24 is a first adder, 2
3 is a second adder, 25 is a second 1H line memory, 2
7 is a horizontal high-pass component filter for extracting a horizontal high-pass component, 26 is a third 1H line memory, 29 is an edge detection circuit for extracting a vertical edge component from a 3H signal, 31
Is a third adder, 30 is a fourth adder, 42 is a VT addition / V peaking circuit, 16 is a vertical enlargement circuit for enlarging the screen position of a luminance signal, 32 is a VH reproduction / V peaking switching signal terminal, 33 Is a field memory for VH expansion,
34 is a first switch, 35 is a fourth 1H line memory, 36 is a fifth 1H line memory, 37 is a vertical enlargement circuit, 38 is a vertical frequency shift circuit, 47 is a second switch, and 48 is a second switch. 3 is a switcher, 49 is a VH expansion circuit that expands the vertical resolution augmentation signal in the vertical direction, 18 is a fifth adder, 19 is a sixth adder, 17 is a double speed conversion circuit that converts sequentially to scanning, and 12 is a double speed conversion circuit. Output terminal for luminance signal.

The operation of the video signal receiving circuit configured as described above will be described. First, input EDTV
The two signals are separated by a Y / C separation circuit 4 into a luminance signal and a chrominance signal. Further, the HH reproduction circuit 5 reproduces the horizontal high-frequency luminance component and adds the luminance component to the luminance signal. The color signal C passes through a color demodulation circuit 6, a scanning line interpolation circuit 7, a vertical enlargement circuit 8, and a double-speed conversion circuit 9 to obtain a double-speed color signal vertically enlarged to 16: 9.

The scanning line interpolation circuit 13 generates an interpolation scanning line signal required for double-speed conversion from the luminance signal whose horizontal resolution has been enhanced by the HH reproducing circuit 5. Next, the VT addition / V peaking circuit 43 adds the vertical resolution augmentation signal VT signal and performs vertical contour correction. In this block,
First, in order to add a VT signal, the current scanning line signal is delayed by the first 1H line memory 20, and the signals before and after the signal are passed through the SSKF filter processing for supplementing the interpolation scanning line in the main image area to pass the vertical low frequency component. After performing the filtering by the filter 21, the horizontal low-pass component is extracted by the horizontal low-pass
An interpolated scanning line reinforcement signal equal to or less than z is obtained. This signal and VT
The VT signal for the interpolation scanning line can be reproduced by adding the signal to the / VH reproduction circuit 14 with the interpolation scanning line reinforcement signal reproduced from the non-image portion. Here, after the interpolation scanning line signal obtained by performing the scanning line interpolation is delay-adjusted by the second 1H line memory 25,
The low frequency component of the interpolated scanning line signal is removed through a horizontal high frequency component pass filter 27 that extracts a horizontal high frequency component of 1 MHz or more. By adding the main image portion interpolation scanning line signal and the interpolation scanning line VT signal in the first adder 24,
An VT-reproduced interpolated scanning line signal can be obtained.

The second adder 23 adds the current scanning line signal delayed by the first 1H line memory 20 and the current scanning line VT signal reproduced by the VT / VH reproducing circuit 14 so as to obtain VT. A reproduced current scanning line signal can be obtained.

Here, using the 1H line memory for reproducing the VT signal and the 1H line memory for reproducing the VH signal,
Peaking can be realized, and its operation will be described below with reference to FIG.

First, the input and output signals of the first 1H line memory 20 are input to the edge detection circuit 29 by the VT addition circuit. This signal corresponds to the A and C signals in FIG. Next, a first switch 34 is provided in order to use the fourth 1H line memory 35 used in the VH expansion circuit 49 by V peaking. In the first switch 34, a VH reproduction / V peaking switching signal is used.
In the VH reproduction mode, the output signal of the VH expansion memory 33 is input, and in the V peaking mode, the output signal of the second 1H line memory 25 is switched so as to be input and output to the fourth 1H line memory 35. here,
The output of the second 1H line memory and the output of the fourth 1H line memory 35 are input to the edge detection circuit 29. This signal corresponds to the D and E signals in FIG. Based on the above signals, the vertical edge components of the C and D signals are detected as shown in FIG. 3A, and added to the VT-reproduced signal by the third and fourth adders, so that V Peaking can be realized.

In the V peaking mode, the VT is turned off by forcibly setting the VH additional signal to zero by the switches 47 and 48.

As described above, according to the present embodiment, 1
By using both the 1H line memory for adding VT and the 1H line memory for expanding VH without adding three H line memories, the VH signal is turned off, and VT addition and V peaking can be realized. The above processing is
This is effective for the EDTV2 signal to which the VH signal is not originally added, and the vertical resolution can be improved by the V peaking.

[0028]

As described above, according to the present invention, the line memory necessary for reproducing the vertical reinforcement signal is used together with or replaced by the V peaking processing, so that the line memory dedicated to the V peaking is not added, and It is also possible to reproduce a reinforcement signal at the same time, thereby realizing a video signal receiving circuit that has a cost merit and an image quality improving effect.

[Brief description of the drawings]

FIG. 1 shows a video signal reception cycle according to a first embodiment of the present invention.
Road block diagram

FIG. 2 is a block diagram according to a second embodiment of the present invention.

3A is a schematic diagram showing a conventional edge detection method, and FIG. 3B is a block diagram showing a conventional vertical peaking.

FIG. 4 is a block diagram of a conventional EDTV2 signal receiving circuit;

[Explanation of symbols]

 Reference Signs List 1 EDTV2 signal input terminal 2 Discrimination control signal demodulation circuit 3 Discrimination control signal output terminal 4 Y / C separation circuit 5 HH reproduction circuit 6 Color demodulation circuit 7 Scan line interpolation circuit 8 Vertical enlargement circuit 9 Double speed conversion circuit 10/11 Color difference signal output Terminal 12 Luminance signal output terminal 13 Scan line interpolation circuit 14 VT / VH reproduction circuit 15 VH expansion circuit 16 Vertical expansion circuit 17 Double speed conversion circuit 29 Edge detection circuit 32 VH reproduction / V peaking switching signal input terminal 33 VH expansion memory 37 Vertical expansion Circuit 38 Vertical frequency shift circuit 43 VT addition + V peaking circuit 44 VT addition + V peaking circuit 45 V peaking circuit 46 VT addition circuit 49 VH expansion circuit

Continued on the front page (72) Inventor Soichiro Katsuki 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 7/015

Claims (2)

(57) [Claims] An identification control signal demodulation circuit for separating and demodulating an identification control signal from an EDTV2 video input signal; a Y / C separation circuit for separating the video input signal into a luminance signal and a chrominance signal; VT / VH for demodulating / separating / reproducing the vertical time resolution enhancement signal and the vertical resolution enhancement signal
A reproduction circuit, a scanning line interpolation circuit for generating a scanning line interpolation signal from the luminance signal separated by the Y / C separation circuit, and a first 1H line for delaying the current scanning line output signal of the scanning line interpolation circuit by one line A memory, a vertical low-pass filter for extracting a vertical low-pass component from an input / output signal of the first 1H line memory, and a horizontal low-pass filter for extracting a horizontal low-pass component from an output of the vertical low-pass filter A second 1H line memory for delaying the interpolated scanning line output signal of the scanning line interpolating circuit by one line, a horizontal high-pass filter for extracting a horizontal high-frequency component from the output signal of the second 1H line memory, A first adder for adding a vertical time resolution enhancement signal for an interpolated scanning line of the VT / VH reproducing circuit and an output of the horizontal low-pass filter; and an output of the first 1H line memory. A second adder for adding serial VT / VH vertical time for the current scan line of the reproduction circuit and the resolution reinforcement signal,
A third 1H line memory for delaying the output of the second 1H line memory by one line, an input / output of the first 1H line memory, an output of the second 1H line memory, and the third 1H line memory And a third adder for adding the output of the first adder and the vertical edge component for the interpolated scanning line output from the edge detection circuit. And the second
And a fourth adder for adding the output of the adder and the vertical edge component for the current scanning line output from the edge detection circuit . 2. An identification control signal demodulation circuit for separating and demodulating an identification control signal from an EDTV2 video input signal; a Y / C separation circuit for separating the video input signal into a luminance signal and a chrominance signal; VT / VH for demodulating / separating / reproducing the vertical time resolution enhancement signal and the vertical resolution enhancement signal
A reproduction circuit, a scanning line interpolation circuit for generating a scanning line interpolation signal from the luminance signal separated by the Y / C separation circuit, and a first 1H line for delaying the current scanning line output signal of the scanning line interpolation circuit by one line A memory, a vertical low-pass filter for extracting a vertical low-pass component from an input / output signal of the first 1H line memory, and a horizontal low-pass filter for extracting a horizontal low-pass component from an output of the vertical low-pass filter A second 1H line memory for delaying the interpolated scanning line output signal of the scanning line interpolating circuit by one line, a horizontal high-pass filter for extracting a horizontal high-frequency component from the output signal of the second 1H line memory, A first adder for adding a vertical time resolution enhancement signal for an interpolated scanning line of the VT / VH reproducing circuit and an output of the horizontal low-pass filter; and an output of the first 1H line memory. A second adder for adding serial VT / VH vertical time for the current scan line of the reproduction circuit and the resolution reinforcement signal,
An enlargement memory for delaying the vertical resolution enhancement signal output from the VT / VH reproduction circuit for enlargement, and an output of the VH enlargement memory and an output of the second 1H line memory are output by a VH reproduction / V peaking switching signal. , A fourth 1H line memory for delaying the output signal of the switch by one line, and the first 1H line memory.
An edge detection circuit for extracting a vertical edge component based on an input / output of the H line memory, an output of the second 1H line memory, and an output of the fourth 1H line memory;
A third adder for adding the output of the adder and the vertical edge component for the interpolation scanning line output from the edge detection circuit;
A fourth adder for adding the output of the second adder and the vertical edge component for the current scanning line output from the edge detection circuit, and a fifth adder for delaying the output of the fourth 1H line memory by one line A 1H line memory, a vertical enlargement circuit for vertically interpolating a vertical resolution enhancement signal from an output of the VH enlargement memory, an output of the fourth 1H line memory, and an output of the fifth 1H line memory; A vertical frequency shift circuit for shifting the frequency of the output of the enlargement circuit from a low-frequency component to a high-frequency component, and a second / third switching circuit for switching the output of the vertical frequency shift circuit according to a VH reproduction / V peaking switching signal. A video signal receiving circuit, comprising: