JP2952020B2 - Semiconductor device - Google Patents

Description

The present invention relates to the manufacture of integrated circuits. More particularly, the invention relates to fabricating transistors in semiconductor-on-insulator.

BACKGROUND OF THE INVENTION Semiconductor-on-insulator structures are often used in applications where resistance to radiation effects is required. Semiconductor-on-insulation structures typically include a single-crystal semiconductor layer of silicon formed on an insulation structure such as sapphire or silicon dioxide. This single crystal layer is typically divided into discrete regions or mesas to provide complete electrical isolation between components formed in one mesa and components formed in another mesa. I have. Semiconductor-on-insulator structures are resistant to radiation effects because the electrical device is isolated from the substrate. When radiation particles, such as alpha (α) particles, irradiate a typical integrated circuit, errors occur in the operation of the integrated circuit due to the interaction between the electrical device and the substrate, especially the resulting electrical circuit. In semiconductor-on-insulator structures, this interaction is prevented by the insulating layer.

One problem with using semiconductor-on-insulator structures is that
Body effect on the channel of a field effect transistor. Field effect transistors operate by coupling a voltage to a channel, thereby causing conduction between the source and drain regions. The point where conduction occurs between the source and the drain is called a threshold voltage. As the channel is formed during isolated manufacturing, the trapped charge can cause a change in threshold voltage, which can cause inconsistent operation of the field effect transistor. A common approach to avoid this effect is to provide a ground contact on the channel. However, not all floating channel region effects are negative. For example, because of the floating channel region, a higher drive current through the channel can be obtained. This allows for faster operation of the integrated circuit using transistors with higher drive current. The present invention allows floating channel regions during the "on" state of the transistor when larger drive currents are useful, and when the transistor is to be turned off to obtain a consistent threshold voltage, It is an object to obtain a manufacturing and method adapted to supply a control voltage on a channel.

SUMMARY OF THE INVENTION The disclosed embodiments of the present invention provide a fabrication and method for actively controlling the voltage applied to the channel of a field effect transistor. In the embodiment described herein, a transistor connected to a channel region is made. This channel transistor is of a conductivity type opposite to that of a transistor using a main channel region. The source of the channel transistor is connected to the channel, and the drain of the channel transistor is connected to the reference voltage. The same gate is used for controlling the channel transistor and the main transistor. When a voltage is applied that causes the main transistor to conduct, the channel transistor is non-conductive, causing the channel to float and allow greater drive current. On the other hand, when a voltage for turning off the main transistor is applied, the channel transistor turns off, fixing the channel region to the reference voltage. Thereby, the threshold voltage control of the main transistor becomes consistent.

In one preferred embodiment, the channel of the main transistor is used as the source of the channel transistor, and the gate of the main transistor extends over the channel region of the channel transistor. A reference voltage is connected to a drain region formed on a channel region of the channel transistor on a side opposite to a channel of the main transistor. In another preferred embodiment, the drain region is located adjacent to the source region of the main transistor. Many non-pass (no
In an n-pass) transistor circuit, the source of the main transistor is fixed. In this embodiment, the source of the main transistor and the drain of the channel transistor are locally connected to each other, so that a simpler interconnect structure can be provided.

Embodiment FIG. 1 is a plan view of one embodiment of the present invention. FIG. 2 is an electric circuit diagram showing the operation of the embodiment shown in FIG. 3A and 3B show a cross section of the embodiment shown in FIG. 4A to 4K are schematic side views showing manufacturing steps of the embodiment shown in FIG.

The embodiment shown in FIG. 1 includes two coupled transistors. The first transistor is a main transistor 56 and the second transistor is a body or channel transistor 58. This structure is formed in the shape of a mesa 14 on the insulating layer 12. The insulating layer 12 may be silicon dioxide, sapphire, or any other insulating structure known in the art. Gate 42 controls the current between source 54 and drain 52 of main transistor 56. Source 54 and drain 52
Is connected to another device to perform the function of a field effect transistor in an integrated circuit including this embodiment of the present invention. The gate controls the current flowing through the channel region, thereby controlling the current from the drain 52 to the source. The channel region 34 is a p-type region and is formed so as to be self-aligned with the gate 42. P + source area 48
Are electrically connected to the channel region 34 because they have the same conductivity type. N-channel 38 is controlled by gate 42, which controls the current between drain region 46 and source region 48. These components constitute the body transistor 58. Generally the drain region 46
Is connected to a reference voltage, and supplies a fixed voltage to the channel region 34 when the body transistor 58 is turned on. The structure of FIG. 1 is designed such that when transistor 56 is on, channel region 34 floats and increased drive current can be used for the circuit including transistor 56. When transistor 56 is off, channel region 34 is tied to a reference voltage to provide a consistent threshold voltage useful for predictable and accurate operation of transistor 56 in circuits including transistor 56. Can be

FIG. 2 is an electric circuit diagram showing an electric operation of the structure of FIG. Source region 54 and drain region 52 are connected to other devices in the integrated circuit. Gate 42 controls both transistor 56 and transistor 58. Source area 48
Is connected to the channel 34 of the transistor 56. Drain region 46 is connected to a reference voltage. In this embodiment,
Transistor 56 is an n-channel transistor, and transistor 58 is a p-channel transistor. Gate 42
While a high voltage is applied, the transistor 58 is off and the transistor 56 is on. Thus, the channel region is allowed to float from above the transistor 56. While a low voltage is being applied to the gate 42, the transistor 58 is on and the transistor 56 is off.
Since transistor 58 is on, the voltage level on channel region 34 is controlled by the reference potential connected to drain region 46.

3A and 3B are cross-sectional views of FIG. 1 taken along lines AA and BB, respectively. As can be seen from FIG.
An insulating layer 12 is formed on the surface of the substrate. In this particular embodiment, substrate 10 is a single crystal silicon substrate and insulating layer 12 is a silicon dioxide layer formed by oxygen ion implantation. A description of oxygen ion implantation (SIMOX) may be found in US Pat. Nos. 3,855,009 and 4,241,359. Sidewall oxide regions 28 are provided on the sidewalls of the mesas 14 to stabilize conduction at the surface of the mesas. Gate 42 is insulated from channel regions 34 and 38 by silicon dioxide layer 30. Gate 42 controls the conductivity between source region 48 and drain region 46, as shown in FIG. 3A. Gate 42 also controls the conductivity between source region 54 and drain region 52, as shown in FIG. 3B.

4A to 4K are schematic side views, corresponding to FIG. 3, showing the manufacturing steps required to make the embodiment shown therein. Single crystal silicon substrate 10
Oxygen ions are implanted into the
12 is formed. Next, an epitaxial layer 14 is formed on the short-crystal silicon structure remaining on the silicon dioxide layer 12 as a nucleation type region. Substrate 10 and thus epitaxial layer 14 may be an n or p-type layer using, for example, a 100 crystal orientation. The doping concentration is n
It is 3 to 6 ohm-centimeters for the mold and 10 to 12 ohm-cm for the p-type. The steps described here assume that the epitaxial layer 14 is n-type.

Next, a silicon dioxide layer 16 is grown to a thickness of about 350 Å using a thermal oxidation method. Next, a silicon nitride layer 18 is deposited by low pressure vapor deposition to a thickness of about 1,700 angstroms. Next, silicon dioxide layer 20 is deposited on silicon nitride layer 18 by low pressure vapor deposition to a thickness of about 3,200 angstroms. Next, a photoresist layer 22 is applied over the surface of the silicon dioxide layer 20. The photoresist layer 22 is exposed and processed using a known lithography technique. Using the photoresist layer 22 as an etch mask, the silicon dioxide layer 20, the silicon nitride layer 18, and the silicon dioxide layer 16 are etched. Using reactive ion etching techniques well known to those skilled in the art to exhibit isotropic etch properties, the layers 16,18,
20 is etched.

Next, the photoresist layer 22 is removed using a usual wet removal method. Next, two-stage ion implantation is performed on the structure of FIG. 4B. The first step is to implant elemental ions with an energy of about 30 kiloelectron volts at a density of about 3 × 10 ¹² ions / cm ² . The second step is to implant boron ions having an energy of about 80 kiloelectron volts at a density of about 5 × 10 ¹² ions / cm ² . This forms a channel stop region 14 'as shown in FIG. 4B. Next, the silicon dioxide layer 20 is removed using an arbitrary etching technique such as a wet deglazing method using hydrofluoric acid. Next, using low pressure vapor deposition, about 1,000
A silicon dioxide layer 24 is deposited to a thickness of Å. Next, the silicon dioxide layer 24 is etched using an anisotropic etching process such as reactive ion etching (such as carbon tetrachloride) using a chlorine-based gas,
A sidewall oxide region 26 is formed as shown in FIG. 4D. Next, the silicon nitride layer 18, the silicon dioxide layer 16, and the sidewall silicon oxide layer 26 are used as an etch mask for etching the epitaxial silicon layer 14. The epitaxial silicon layer 14 is etched using reactive ion etching with hydrochloric acid, resulting in the structure shown in FIG. 4E. FIG. 4E includes a sidewall protection layer 14 'that blocks unwanted conduction along the edges of the mesa 14. The formation of such a sidewall protection layer has been assigned to the assignee of the present application, 19
Matloubian U.S. Patent No. 4,753,896 dated June 28, 1988
No. Next, the structure of FIG. 4E is oxidized,
Approximately 250 Å thick silicon dioxide is mounted on the sidewalls of the mesas 14. Further, a silicon dioxide layer approximately 2,500 angstroms thick is deposited by low pressure vapor deposition and etched by a reactive ion etch,
A sidewall silicon dioxide layer 28 as shown in FIG. 4F is obtained. In the following drawings, the protection region 14 'is omitted from the drawings for clarity.

Silicon nitride layer 18, silicon dioxide layer 16, and sidewall region 26 are removed by a two-step etching process. That is, the silicon nitride layer 18 is etched using hot phosphoric acid, and the silicon dioxide layer 16 and the sidewall silicon dioxide layer 26 are removed by anisotropic etching in a fluorine-based chemical atmosphere. Due to the anisotropy of the reactive ion etching, the silicon dioxide layer 28 remains. Next, a silicon dioxide layer 30 is grown by thermal oxidation of the surface of the mesa region 14, and as shown in FIG.
30 is obtained. Next, the photoresist layer 32 is applied and patterned using a normal photolithography technique to obtain the structure of the photoresist layer 32 shown in FIG. 4G. Next, for the structure of FIG. 4G, boron ions having an energy of about 80 k
The ions are implanted at a density of × 10 ¹² ions / cm ² . As a result, the rear surface threshold voltage of p region 34 is set to 25 volts or more. Adjustment of the front surface threshold voltage of the p region 34 is as follows.
This is performed by implanting boron ions having an energy of about 25 kiloelectron volts at a density corresponding to the selected threshold voltage. Photoresist layer 32
Are selected to fit in the region Δ, which is the overlap region where the p + source region 48 is formed. Since the p + region 48 is formed in this region, the alignment of the photoresist within the region Δ is not strict.

Next, the photoresist layer 32 is removed, and a second photoresist layer 36 is applied and patterned as shown in FIG. 4H. Next, for the structure shown in Fig. 4H, boron ions with an energy of about 25 kiloelectron volts form about 1.
Ions are implanted at a density of 0 × 10 ¹² ions / cm ² . This sets the front threshold voltage to about -1 volt. Next, a second ion implantation of phosphorus ions having an energy of about 180 kiloelectron volts at a density of about 1.2 × 10 ¹² ions / cm ² is performed, and the threshold voltage on the back surface is about −
Set to 13 volts. As is well known in the art, these ion implantation energy and density combinations are chosen to obtain specific properties in a specific environment. In the structure shown in FIG. 4H, this ion implantation leaves a gap 40 between the n-channel region 38 and the p-channel region 34. This is a region within the region Δ shown in FIG. 4G, and the n-channel region 38 and the p-channel region 34
It creates voids as shown in the 4H diagram or has overlaps without adverse effects on the operation of the integrated circuit.

Next, the photoresist layer 36 is removed, the silicon dioxide layer 30 is stripped, and a second silicon dioxide layer 31 is formed using a thermal oxidation method to a thickness of about 250 angstroms. Next, a polysilicon layer 42 is applied to a thickness of about 4,500 angstroms, patterned and
The structure shown is obtained. Next, the photoresist layer
44 is attached and patterned as shown in FIG. 4J. Next, boron ions having an energy of about 20 kiloelectron volts are applied to the structure of FIG.
^The ions are implanted at a density of ¹⁵ ions / cm ² . By this ion implantation, a source region 48 and a drain region 46 are formed as shown in FIG. 4J. Next, the photoresist layer 44 is removed and a photoresist layer 50 is applied over the surface of the structure, as shown in FIG. 4K. Next, a density of about 5 × 10 ¹⁴ ions / cm ² of phosphorus ions having an energy of about 140 kiloelectron volts with respect to the structure of FIG.
Arsenic ions having an energy of about 150 kiloelectron volts are further implanted, and about 3.5 × 10 ¹⁵ ions / cm ²
Density, ion implantation. The first in these ion implantations
As shown, a source region 54 and a drain region 52 are formed. Thus, the embodiment shown in FIG. 1 is manufactured.

A plan view of the second preferred embodiment is shown in FIG.
FIG. 6 is an electric circuit diagram showing the operation of the embodiment shown in FIG.
It is shown in the figure. Cross sections along AA and BB are shown in FIGS. 7A and 7B. The manufacturing steps required to make the embodiment shown in FIG. 5 are shown in FIGS. 8A and 8B.

The embodiment of FIG. 5 includes two transistors, a main transistor 156 and a body transistor 158. In main transistor 156, gate 142 controls the current between source 154 and drain 152. This is achieved by controlling the conductivity of the channel region 134. Channel region 134
Is adjacent to the n-channel region 148. P channel region 1
34 functions as the source of the body transistor, and the p + region 146 functions as the drain. The conductivity between the p-channel region 134 and the p + drain region 146 is controlled by the gate 142 by controlling the conductivity of the n-channel region 148. This constitutes a body transistor.

An electric circuit having the structure shown in FIG. 5 is shown in FIG. Gate 142 controls the conductivity of n-channel transistor 156 and p-channel transistor 158. When a high voltage is applied to the gate 142, the p-channel transistor 158 turns off and the n-channel transistor 156 turns on. p
Since the channel transistor 158 is off, the channel region 134 is allowed to float, and the maximum drive current is supplied by the transistor 156. When a low voltage signal is supplied to the gate 142, the p-channel transistor turns on and the n-channel transistor 156 turns off. Since p-channel transistor 158 is on, channel region 134 is fixed to a reference voltage, and transistor 156 provides a consistent threshold voltage and controllable on / off characteristics.

7A and 7B are cross-sectional views along AA and BB of FIG. 5, respectively. As can be seen in FIG.
2 is the conductivity of channel region 148, and
+ Controls the conductivity to and from the region 146. As can be seen in FIG. 7B, gate 142 also controls the conductivity of p region 134, and thereby controls the conductivity between source region 154 and drain region 152.

FIG. 8A is a side view showing an intermediate step for fabricating the embodiment shown in FIG. FIG.8A corresponds to the stage shown in FIG.4G, and the steps used to make the structure shown in FIG.4G are also used to make the structure shown in FIG.8A. 4G, where 100 is added to the reference number corresponding to the component in FIG. 4G (e.g., sidewall oxide region 128 corresponds to the sidewall oxide in FIG. 4G). Corresponding to region 28).

The structure of FIG. 8A is subjected to a first ion implantation of phosphorus ions having an energy of about 180 kiloelectron volts and a density of about 1.2 × 10 ¹² ions / cm ² . As a result, the rear surface threshold voltage and the partial front surface threshold voltage are adjusted. The front threshold voltage further has an energy of about 25 kiloelectron volts and is about 1.45 × 10 ¹² ions / cm ²
Is adjusted by performing boron ion implantation. Next, a photoresist layer 132 is applied and patterned as shown in FIG. 8B. Next, the structure in Figure 8B has approximately 85 kiloelectron volts of energy,
Implantation of boron ions at a density of about 3.7 × 10 ¹² ions / cm ² is performed. This counteracts the backside threshold injection used to form n region 138. In order to adjust the front surface threshold voltage of the p region 134, boron ions having an energy of about 25 kiloelectron volts are additionally implanted at a density selected to obtain a desired threshold voltage. Is also good. The photoresist layer 132, like the silicon dioxide layer 130, is then removed. The silicon dioxide layer 130
Etching can be performed using any silicon dioxide etching method, such as reactive ion etching in a fluorine-based chemical atmosphere.

Next, thermal oxidation is used to thermally grow a gate oxide to a thickness of about 250 Å, as shown in FIG. 8C. Next, as shown in FIG. 8C, the polysilicon layer 142
Is attached and patterned. Next, a photoresist layer 136 is applied on the surface of the patterned layer 142 and patterned to obtain a structure as shown in FIG. 8C. Next, the structure of FIG. 8C has an energy of about 20 kiloelectron volts and is about 2 × 10 ¹⁵ ions / cm ^2.
Is implanted to form a p + region 146 as shown in FIG. 8C. Next, after the photoresist layer 136 is removed, a photoresist layer 150 is applied and patterned as shown in FIG. 8D. No.
The structure in the 8D diagram, in turn, has an energy of about 140 kiloelectron volts, an ion implantation of phosphorus at a density of about 5 × 10 ¹⁴ ions / cm ² , and an energy of about 150 kiloelectron volts and about 3.5 A second ion implantation of arsenic ions at a density of × 10 ¹⁵ ions / cm ² was performed and, as shown in FIG. 5, p + source and drain regions, 154 and 1
52 are formed.

9 and 10 are plan views of another preferred embodiment of the present invention. In FIG. 9, a main transistor 256 includes a drain 252, a source 254, a channel 234, a gate 2
Contains 42. The channel transistor is the main channel
234, a channel transistor channel 248, and a channel transistor drain 246. In addition to a more compact arrangement, the structure of FIG.
246 and the source 254 of the main transistor. In many circuits, the source 254 of the main transistor and the drain 246 of the channel transistor are tied to the same reference voltage. The structure of FIG. 9 allows these regions to be easily connected to one another by silicide layers of titanium, molybdenum, or other refractory metals, or by local interconnects such as titanium nitride interconnects. . This achieves a very compact structure by limiting the necessary connections to the transistors. In Figure 10,
The main transistor 356 includes a drain 352, a source 354, a channel 334, and a gate 342. The channel transistor includes a main channel 334, a channel transistor channel 348, and a channel transistor drain 346. The structure in Figure 10 has the same features,
The arrangement is slightly more compact than the structure of FIG.

Although specific embodiments of the present invention have been described herein, they are not intended to limit the scope of the invention. Numerous modifications to the present invention will be apparent to those skilled in the art from the present specification. For example, it is possible to use a transistor having a conductivity type opposite to that shown in the specification or a region of the opposite conductivity type. Further, the structure used here can be applied to structures other than the silicon-on-insulator structure. For example, if the field effect transistors are formed in separate wells in a BiCMOS integrated circuit, or if the wells are completely separated by buried regions under the wells, this sophisticated contact scheme may be used. It could be used to advantage. The scope of the present invention is limited only by the claims.

 The following items are further disclosed with respect to the above description.

(1) A semiconductor device, comprising: a substrate having a first conductivity type; a first source region having the first conductivity type formed in the substrate; and a first source region formed in the substrate. A drain region having the first conductivity type, spaced from the first source region, and having a common first channel region of a second conductivity type and a second A first drain region defining a source region of the first region; a second channel region formed adjacent to the common region and having the first conductivity type; formed adjacent to the second channel region. A second drain region having the second conductivity type; a gate formed adjacent to the first and second channel regions, wherein a current between the first source and drain regions and 2 controls the current between the drain and the common region A gate for controlling so that when one of the first and second channel regions is non-conductive, the other is conductive; and when the one channel is conductive, the other channel is non-conductive. A semiconductor device comprising:

(2) The device according to (1), wherein the substrate is formed on an insulating layer.

(3) The device of paragraph (2), wherein the substrate is electrically isolated from other components formed on the same insulating layer.

(4) The apparatus according to (3), wherein the substrate includes a mesa structure.

(5) The device of paragraph (1), wherein the substrate comprises crystalline silicon.

(6) The device of paragraph (1), wherein the second drain region is connected to a reference voltage.

(7) The apparatus according to (1), further comprising: the substrate;
A device comprising a dielectric layer sandwiched between said first and second channel regions.

(8) The device according to (1), wherein the second drain region is formed adjacent to the second channel region and the first source region.

(9) The device according to item (8), wherein the first source region and the second drain region are electrically connected.
apparatus.

(10) The device according to (9), wherein the electrical connection between the first source region and the second drain region is made of conductive silicide.

(11) The device according to (1), wherein the first conductivity type is N-type and the second conductivity type is P-type.

(12) The device according to (1), wherein the second channel region is not common to either the first source region or the drain region.

(13) The semiconductor device according to (1), wherein the first source region, the first drain region, and the first channel region are all formed at the same depth in the substrate. .

(14) A method for manufacturing a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a first source region having a first conductivity type in the substrate; Forming a first drain region having a first conductivity type in the substrate, wherein the drain region is formed at a distance from the first source region and a second drain region therebetween. Forming a first drain region to define a common first channel region and a second source region having a conductivity type, having the first conductivity type adjacent to the common region; Forming a second channel region; forming a second drain region having the second conductivity type adjacent to the second channel region; adjacent to the first and second channel regions. To form a gate The gate controls the current between the first source and drain regions and between the second drain and the common region, such that when one of the first and second channel regions is non-conductive, Forming a gate to cause the other channel to be conductive and to control the other channel to be non-conductive when the one channel is conductive.

(15) The method according to (14), wherein the substrate is formed on an insulating layer.

(16) The device manufacturing method according to (15), wherein the substrate is electrically separated from other components formed on the insulating layer.

(17) The method according to (16), wherein the substrate includes a mesa structure.

(18) The method according to (14), wherein the substrate includes crystalline silicon.

(19) The method according to (14), further comprising the step of connecting the second drain region to a reference potential.

(20) The method according to (14), further comprising the step of forming a dielectric layer sandwiched between the gate and the first and second channel regions.

(21) The method of manufacturing a device according to (14), further comprising the step of forming the second drain region adjacent to both the second channel region and the first source region. ,Method.

(22) The method according to paragraph (21), wherein the first conductivity type is N-type and the second conductivity type is P-type.

(23) The method of paragraph (14), further comprising the step of forming an electrical interconnect between the first source region and the second drain region.

(24) The method of paragraph (23), wherein the electrical interconnect is a conductive silicide layer.

(25) The described embodiments of the present invention provide structures and methods for actively controlling the voltage applied to the channel of a field effect transistor. In the embodiment described here, a transistor connected to a channel region is made. Channel transistor 258 has a conductivity type opposite to that of transistor 256 using the main channel region. The source of channel transistor 258 is channel 2
34, drain 2 of channel transistor 258
46 is connected to the reference voltage. Channel transistor 258
Uses the same gate 242 to control the main transistor 256. When a voltage that turns on the main transistor 256 is applied, the channel transistor 258 turns off, allowing floating of the channel 234, and allowing a large drive current. On the other hand, when a voltage that turns off the main transistor 256 is applied, the channel transistor 258 turns on, fixing the channel region 234 to the reference voltage.
This allows for consistent threshold voltage control of main transistor 256.

In another embodiment, the channel 234 of the main transistor 256 is used as the source of the channel transistor 258, and the gate 242 of the main transistor extends over the channel region 248 of the channel transistor 258. Then, the reference voltage is applied to the channel region 248 of the channel transistor.
To the drain region 246 formed on the side opposite to the main transistor channel 234.

In a preferred embodiment, the channel 248 of the channel transistor 258 is formed below the gate 242 of the main transistor, and the drain region 246 of the channel transistor 258 is formed at the corner of the region where the source 254 of the main transistor 256 is formed. This provides a more compact arrangement and allows the source 254 of the main transistor 256 to be shorted to the drain 246 of the channel transistor 258. As a result, a very compact arrangement is obtained, and for transistors other than the pass transistor, the side portion of the main transistor, which is the source, is often fixed, so that this method can be used.

[Brief description of the drawings]

FIG. 1 is a plan view of one embodiment of the present invention. FIG. 2 is an electric circuit diagram showing the operation of the structure of FIG. FIGS. 3A and 3B are cross-sectional views of AA and BB, respectively, of FIG. FIGS. 4A to 4K are schematic side views showing processing steps required to fabricate the embodiment shown in FIG. FIG. 5 is a plan view of one preferred embodiment of the present invention. FIG. 6 is an electric circuit diagram showing the electric operation of the embodiment of FIG. 7A and 7B are cross-sectional views along AA and BB of FIG. 5, respectively. 8A to 8D are schematic cross-sectional views showing processing steps required to manufacture the embodiment shown in FIG. 9 and 10 are plan views of a preferred embodiment of the present invention. "Reference number" 10 ... substrate 12 ... insulating layer 14 ... mesa 16 ... silicon dioxide layer 18 ... silicon nitride layer 20 ... silicon dioxide layer 22 ... photoresist layer 24 ... silicon dioxide layer 26 ... Side wall silicon dioxide layer 28 ... Side wall silicon dioxide layer 30 ... Silicon dioxide layer 32 ... Photoresist layer 34 ... Channel region 36 ... Photoresist layer 38 ... n channel region 40 ... Void 42 ... Polycrystalline silicon Gate 44 Photoresist layer 46 Drain region 48 Source region 50 Photoresist layer 52 Drain region 54 Source region 56 Main transistor 58 Channel transistor 128 Side wall oxide region 130 silicon dioxide layer 132 photoresist layer 134 channel region 136 photoresist layer 138 n region 142 polycrystalline silicon gate 146 drain region 148 n channel region 150 photoresist layer 152 drain region 154 source region 156 main transistor 158 body transistor 234 channel region 242 gate 246 drain region 248 channel Region 252 Drain region 254 Source region 256 Main transistor 258 Channel transistor 334 Main channel 342 Gate 346 Drain region 348 Channel region 352 Drain region 354 Source region 356 …… Main transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/088 H01L 29/786

Claims (2)

(57) [Claims] 1. A semiconductor device, comprising: a substrate having a first conductivity type; a first source region having the first conductivity type formed in the substrate; and a first source region formed in the substrate. 1 the drain region,
Having a first conductivity type and spaced from the first source region to define a common first channel region and a second source region of a second conductivity type therebetween; ,
A first drain region; a second channel region formed adjacent to the common region and having the first conductivity type; a second channel region formed adjacent to the second channel region;
A second drain region having a conductivity type of: a gate formed adjacent to the first and second channel regions, wherein a current between the first source and drain regions and the second drain Controlling the current between the common region and the first channel region so that when one of the first and second channel regions is non-conductive, the other is conductive; and when the one channel is conductive, the other channel is A semiconductor device that controls the device to be non-conductive. 2. A method for manufacturing a semiconductor device, comprising: providing a substrate having a first conductivity type, forming a first source region having a first conductivity type in the substrate. Forming a first drain region having a first conductivity type in the substrate, wherein the drain region is formed at a distance from the first source region, and a first drain region is formed therebetween. Forming a first drain region to define a common first channel region and a second source region having a second conductivity type; and adjacent to the common region, the first conductivity type. Forming a second drain region having the second conductivity type adjacent to the second channel region; and forming the first and second channel regions. Forming a gate adjacent to The gate controls current between the first source and drain regions and between the second drain and the common region so that one of the first and second channel regions is non-conductive. Forming a gate to control the other channel to be conductive at the time of, and to control the other channel to be non-conductive when the one channel is conductive.