JP2952876B2 - AD converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter, and more particularly, to a large-scale control circuit (for example, a 4-bit or 8-bit microcomputer) using a semiconductor integrated circuit technology on the same substrate. The present invention relates to an AD converter integrated in a semiconductor device.

[Conventional technology]

Conventionally, as an example in which such a large-scale control circuit and an AD converter are integrated on the same substrate, for example, an AD converter having an 8-input multiplexer and employing a successive approximation method has been realized.

[Problems to be solved by the invention]

When realizing the above-mentioned conventional AD converter and a large-scale control circuit as an integrated circuit on the same substrate, with the progress of process technology, the speeding up of the operation clock is promoted. Conversion accuracy is likely to be reduced due to increased noise.

Y.Tsivid is an example of what kind of noise occurs
“DESIGN OF MOS VLSI CIRCUITS FOR TELECO
MMUNICATIONS "Prentice-Hall Inc. 1985 pp321-324. The summary is summarized as follows. When the 8-bit output buffer operates at the same time, about 25mA current flows and the lead inductance is 50nH. On 25
It is disclosed that 0 mV noise is generated.

As described above, the noise generated on the same substrate is further increased in order to improve the driving capability of the MOS transistor and the bipolar transistor by making the process finer. To increase the speed of the internal gate, the driving capability is improved, and the noise accompanying the charging and discharging of the load capacitance is increased.

Conventionally, as a countermeasure against this power supply noise, 1) Connect the power supply wiring with a control circuit (microcomputer).
A method to prevent mutual interference by performing it separately from the AD converter.

2) Terminating the substrate potential and well potential with low impedance to prevent noise induction.

3) A method in which a fully differential circuit is used as the circuit configuration to be used and the circuit configuration is highly suppressed with respect to power supply noise.

And so on.

However, an increase in the clock speed and an increase in the driving capability of the transistor for the purpose of increasing the degree of integration and the operation speed tend to further increase the generation of noise. Further, the demand for higher accuracy of the AD converter is more likely to cause deterioration in accuracy due to power supply noise than ever before.

[Means for solving the problem]

The AD converter of the present invention has a control circuit on the same semiconductor substrate, a clock terminal for operating the control circuit, a reset terminal for resetting the control circuit, and an AD converter in the control circuit. A clock supply circuit that can vary the amount of delay in the clock for operating the converter, and the input of the AD converter is fixed at a certain potential during the reset period set by the reset signal from the reset terminal,
A circuit that stores the clock delay amount that minimizes the AD converter error by changing the operation clock delay amount of the AD converter while observing the in-band noise power of the converter, and the stored clock after the reset period ends. A clock supply circuit for operating the AD converter with the delay amount, an analog input terminal for inputting an analog signal, a digital input / output terminal used for inputting and outputting a digital signal, a digital input terminal, and a digital output terminal.

That is, in the present invention, in addition to the conventional measures, the system reset period (from the external reset signal to the start of operation)
An additional function of detecting a clock delay that minimizes the in-band noise power of the AD converter during power-on to operation start) and supplying a clock using the clock delay amount to the AD converter is added. An AD converter according to the present invention includes a clock supply circuit that receives a clock signal and outputs the signal with a delay amount that can be set, and an AD conversion circuit that performs AD conversion based on a clock output from the clock supply circuit. Means for detecting in-band noise power of noise power folded by the sampling frequency and clock noise of the AD conversion circuit from the output of the AD conversion circuit, and inputting a known analog signal to the AD conversion circuit in a test mode. The delay amount of the clock supply circuit is variably set and the delay amount at which the in-band noise power is minimized is detected from the detection result of the detecting unit and stored in the storage unit. In the normal mode, the delay amount is stored in the storage unit. A control circuit for setting a delay amount in the clock supply circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory diagram of a block circuit according to a first embodiment of the present invention. A plurality of analog signals are input from an analog input terminal 1, selected by a multiplexer (not shown) built in a control circuit 8, and guided to an AD converter 9. The AD converter 9 starts the AD conversion operation by the clock from the clock supply circuit 7, completes the conversion after a predetermined period, and sends out a digital signal as a result to the control circuit 8.

In this example, the handling of digital signals is all described in parallel (for example, an 8-bit AD converter has eight buzzers), but this is for the purpose of speeding up the processing. Yes, in applications that do not require much speed, the digital signal lines may be reduced as a serial signal format.

The control circuit 8 is provided with a digital input / output terminal 2, a digital output terminal 3 and a digital input terminal 4.
Used for data transfer and connection with external memory.

The clock terminal 6 is an input of an operation clock. If the clock generation circuit is built in the control circuit 8,
External parts such as crystal oscillator, ceramic oscillator and resistor
It functions as a terminal for attaching a capacitor, and usually requires two terminals.

The reset terminal 5 is an input terminal for a reset signal. When a reset signal is input, normal operation starts through a sequence called a reset period.

The first reset period is an initialization period of each register or logic circuit, and ends in a relatively short period. This period is for surely executing initialization of each register and logic circuit.

In the second reset period, the input of the AD converter 10 is connected to a certain potential (for example, a ground potential). This method can be easily realized by preparing an extra channel in an input multiplexer for analog signals, selecting an extra channel at the time of the second reset time, and connecting one side of the extra channel to, for example, a ground potential. .

In the third reset period, the control circuit 8 controls the clock supply circuit 9 to cause the AD converter 10 to execute the AD conversion operation. The clock supplied at this time controls the amount of delay. For example, a circuit as shown in FIG. 2 can be considered. A clock is applied to an input 21 and four delay circuits 23 each composed of two inverters are provided. The clock delay circuit is connected to the input 21 and the output of each delay circuit 23 via a transfer gate 24 and taken out from the output 22. Can be considered. For example, if the delay amount of one stage of the inverter is 2 ns, delay amounts of 0 ns, 4 ns, 8 ns, 12 ns, and 16 ns can be selected.

By controlling the transfer gate 24 from the control circuit 8 using such a clock delay circuit, the AD converter 10
Can be AD-converted with five delay amounts. The AD conversion result at this time is stored in the control circuit for each delay amount.

The fourth reset period determines the third reset period. The AD conversion output stored in the third reset period is subjected to, for example, FFT processing in the control circuit 8 to determine the clock delay amount at which the in-band noise power is minimized. By determining and storing the clock delay amount, the AD converter 10 operates at the clock timing that minimizes the noise in the desired band of the digital noise and the noise folded at the sampling frequency of the AD converter.

In this way, the delay amount of the clock delay circuit can be determined so that the in-band noise power of the noise power folded by the sampling frequency and clock noise of the AD converter is minimized. Noise ratio (S / N
Ratio) can be improved. The operation of the control circuit 8 during the third reset period can use the mode often used in the normal mode operation as the test mode, and can also emulate the actual operation. By doing so, it is also possible to improve the effective signal-to-noise ratio of the AD converter.

The fifth reset period overlaps with the normal operation. That is, the analog input multiplexer is controlled by the control circuit 8, and the amount of delay of the clock supply circuit is set to the value stored in the control circuit 8.

By obtaining and storing the amount of clock delay that minimizes in-band noise power during such a reset period, the AD converter can be operated with an optimal clock delay for system clock noise.

It is important for application to use a power detection circuit together with an external forced reset signal as the reset signal. FIG. 3 shows an example of the power supply detection circuit. The power detection circuit is a resistor
The time constant circuit consisting of 33 and capacitance 34 is connected to the power supply terminal 31 and the ground terminal
The output 36 of the inverter 35 is provided between 32. With this configuration, when power is turned on, the inverter
The output 36 of the output 35 goes to the L level after outputting the H level for a certain period (time determined by the time constant of the resistance and the capacitance and the threshold value of the inverter). By taking the logical sum of the power detection circuit and the external reset signal and inputting the logical sum to the reset terminal, both the external reset signal and the power-on can start the normal operation through the reset period.

In the description, the AD converter 10 performs 8 bits and the clock delay circuit performs 4 stages, then the resolution may be any number of bits, the delay amount may be any number of stages, and the system clock frequency and the delay amount per two stages of the inverter. The number of stages may be determined from.

FIG. 4 is an explanatory diagram of a block circuit according to a second embodiment of the present invention. In FIG. 4, the same parts as those in FIG.

FIG. 4 shows, by broken lines, an AD / DA converter 43 having an interface with an external signal by the control circuit 41. Through the reset period sequence similar to that of the first embodiment, the clock supply circuit 42 supplies a clock with an optimized delay amount that minimizes in-band noise power.

The AD converter 43 is an example using a successive approximation method suitable for medium accuracy at medium speed. Successive comparison method uses DA converter 46 and comparator
44 and a register 45. Compare this successively
The DA converter 46 is used as a DA converter when AD conversion is not performed. In order to multiplex AD conversion and DA conversion, the multiplexer 47 switches between operating the DA converter 46 from the register of the AD converter and operating the DA converter 46 based on a digital signal from the control circuit 41.

Similarly, the output of the D / A converter
Connected to the comparator 44 at the time of conversion, and connected to the control circuit 42 at the time of DA conversion.

It is necessary to supply a signal including control of AD conversion and DA conversion from the clock supply circuit. Usually, the priority of AD conversion and DA conversion is often given priority to DA conversion that is completed in one operation. Thus, when DA conversion is started during the AD conversion operation, the intermediate result of the AD conversion is held in the register 45,
Starting the A / D conversion again halfway after the completion of the D / A conversion is a preferable configuration for maintaining the operation speed.

As described above, in the successive approximation method, since the DA conversion operation can be realized using the DA converter 46 for AD conversion, an improvement in the degree of integration can be expected.

〔The invention's effect〕

As described above, the present invention starts a normal operation via a reset period for detecting and storing a clock delay amount at which the in-band noise power of the AD converter is minimized when a reset signal or power is turned on. Minimizes the effect of power supply noise generated by large-scale control circuits, minimizes the effect of beat noise in the sampling cycle and clock cycle, and realizes an AD converter with excellent accuracy that suppresses sensitivity to impulse noise. it can.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a first embodiment of the present invention, and FIG.
FIG. 3 is a clock delay circuit diagram, FIG. 3 is a power supply detection circuit diagram, and FIG. 4 is a block circuit diagram of a second embodiment of the present invention. 1 analog input terminal, 2 digital input / output terminal, 3 digital output terminal, 4 digital input terminal, 5 reset terminal, 6 clock terminal, 8, 41
…… Control circuit, 7,42 …… Clock supply circuit, 9,43 …… AD
Converter, 21 ... input, 22, 36 ... output, 23 ... delay circuit, 24 ... transfer gate, 31 ... power supply terminal, 32 ...
… Ground terminal, 33… resistor, 34… capacitance, 35 …… inverter, 44… comparator, 45 …… register, 46 …… DA converter,
47, 48: Multiplexer, 49: Analog output terminal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] A clock supply circuit that receives a clock signal and outputs the signal after delaying the signal by a settable delay amount; an AD conversion circuit that performs AD conversion based on a clock output from the clock supply circuit; Means for detecting the in-band noise power of the noise power folded back by the sampling frequency and clock noise of the AD conversion circuit from the output of the AD conversion circuit;
Input to a conversion circuit, variably set the delay amount of the clock supply circuit, detect the delay amount at which the in-band noise power is minimum from the detection result of the detection unit, and store the delay amount in the storage unit;
An A / D converter comprising a control circuit for setting the amount of delay stored in the storage means in the clock supply circuit in the normal mode.