JP2952931B2 - A / D converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly, to an A / D converter having a plurality of groups of capacitive elements.

[Conventional technology]

Conventionally, this type of A / D converter has a switch and a capacitor,
And a comparator and a logic circuit.

FIG. 4 is a circuit diagram of an A / D converter showing an example of such a prior art.

As shown in FIG. 4, the A / D converter has a 3-bit D
/ A conversion unit, comparator unit 1, and logic circuit (L)
And a 2, D / A conversion unit are each 2 ^0: 2 ^0: 2 ^1: 2 capacitive element C ₁ as a volume ratio of _2, C _2, C _3, and a C _4. One of the electrodes of these capacitive elements C _{1 to} C ₄ is connected in common to become the output of the D / A converter, and the other electrode is connected to the switch S
_{21, S 22, S 23,} S 24 are connected. These switches S
₂₁ to S ₂₄ is the movement which is predetermined by the A / D conversion operation, the input voltage V _IN and the reference voltage V _F ⁺ and V _F ^- is controlled so as to select one of the potential of.

On the other hand, the comparator unit 1 is supplied with a differential input. That is, the switch S ₁₀ is connected between the one input the output of the D / A converter comprising a capacitor element as described above is supplied and the ground. The other inputs are capacitive elements C ₁ , C ₂ ,
Capacitance element C having a capacitance value equal to the sum of the capacitance values of C ₃ and C _4
11 and the switch S ₉ is connected in parallel between the ground. The output O of the comparator 1 is supplied to the logic circuit 2, or V _F the value of the output O logic circuit 2 connects the switch S _22, S _23, S ₂₄ to the reference voltage V _F ^{+ -}
A signal D ₁₁ to determine where to connect to, and outputs the A / D conversion result D _2.

 Next, the operation of the A / D converter will be described.

First, the switches S ₉ and S ₁₀ are turned on, the differential input is biased, and all the switches S _{21 to} S ₂₄ are connected to the input V _IN . At this time, the comparator 1 (-) of the charge stored in the side sum Q _{1 is, Q 1 = (V IN -V} C) C 1 + (V IN -V C) C 2 + (V IN -V C ) C ₃ + (V _IN −V _C ) C ₄ (1) (However, V _C is a ground (common) voltage, and stray capacitances other than C _{1 to} C ₄ are ignored.) Then, the switches S ₉ and S ₁₀ are turned off, and the switch S ₂₁
Is connected to the V _F ^- side, and switches S ₂₂ , S ₂₃ , and S ₂₄ are connected to the V _F ⁺ or V _F ^- side. At this time, a search that is determined in order from the most significant bit of the bit length to be converted, that is, a so-called binary search is performed.

FIG. 5 is a drive signal waveform diagram of the switch shown in FIG.

As shown in FIG. 5, V _F to the input voltage V _IN ^- the voltage near is input, the switch S _22, S ₂₃ is V _F ^-, switch S ₂₄ is V
Is connected to the _F ^+, the input voltage V _IN and ^{_{(V F + -V F -)}} / 2 are compared, and the output O ₍₃₎ = 0. Then, on the results of the output O _(3), the switch S _22, S ₂₄ is V _F ^- in and switch S ₂₃ is V _F ⁺
, The input voltage V _IN is compared with (V _F ⁺ −V _F ⁻ ) / 4 to obtain an output O ₍₂₎ = 0. Next, switches S ₂₃ and S ₂₄ are set to V
_F ^- in and the switch S ₂₂ is connected to ^{_{V F +, (V F +}} -V
_F ⁻ ) / 8 to obtain the output O ₍₁₎ = 0. As a result, the output becomes O ₍₃₎ O ₍₂₎ O ₍₁₎ = 000, and a digital value of the input voltage V _IN is obtained. At this time, the comparator 1 (-) side input substantially equal to the voltage obtained when the switch S ₉ is turned on, the comparator 1 (-) sum of the charge stored in the side
Q _{2 ^{is, Q 2 = (V F -}} -V C) C 1 + (V A -V C) C 2 + (V B -V C) C 3 + (V D -V C) C 4 ...... ( 2) (where, V _C is the ground _{voltage, V a, V B, V} D is V _F ⁺ or V _F ^- is either a, V _F ⁺ for ^{_{000, V F -, V F}} - order . become) Therefore, since Q ₁ = Q ₂ is satisfied, the above-mentioned (1) and (2) solving this equation as Q ₁ -Q ₂ = 0 from the equation (V _F ^- the reference of 0 to the) and , (V _IN −0) C ₁ + (V _IN −V _A ) C ₂ + (V _IN −V _B ) C ₃ + (V _IN −V _D ) C ₄ = 0 (3) ^{_{However, C 1 = 2 0 C,}} C 2 = 2 0 C, C 3 = 2 1 C, C 4 = 2 2 C
Since it has been described above (3) ^{_{is, V IN - (2 2 V}} D +2 1 V B +2 0 V A) / 8 = 0 , and the and the output of the input voltage V _IN and the D / A converter comparison And
When it becomes 0, it indicates that the conversion is completed.

[Problems to be solved by the invention]

The accuracy of the above-described conventional A / D converter is determined by the relative ratio of the capacitance elements used in the D / A converter.

However, a usual individual capacitance element is formed by arranging a required number of unit capacitors having the same shape and size to obtain a required value. In this way, an error caused by an overetch or the like in the manufacture of the IC works on each of the capacitive elements in the same manner, and the relative error deterioration can be minimized.

However, the thickness of the insulating film using the capacitor becomes 300~400Å or less, one size of SiO ₂ molecules is only several tens of times the distance be compared to several Å. Therefore, thermal oxidation performed at the time of manufacturing cannot control the thickness at the molecular level, so that there is a disadvantage that the relative accuracy is deteriorated due to the variation in the thickness.

An object of the present invention is to provide an A / D converter capable of preventing the deterioration of the relative accuracy and improving the manufacturing yield with high accuracy.

[Means for solving the problem]

The A / D converter of the present invention includes a plurality of switches and a plurality of capacitance elements, and connects a D / A converter that switches between an analog input voltage and a plurality of reference voltages, and connects a positive input and a negative input to a common potential. And a function to release the comparator, and a comparator that compares the input voltage and the plurality of reference voltages, and outputs a digital signal by logically converting the output of the comparator, and the D / A converter. A having a logic circuit to control
In the / D converter, one end of a plurality of capacitive elements commonly connected to one end of a plurality of capacitive elements, and one end of another plurality of capacitive elements formed with the same capacitance as the capacitance of the plurality of capacitive elements. The connected second capacitance element group, one of which is connected to the input voltage and at least one reference voltage, and the other of which is connected to the other ends of the plurality of capacitance elements of the first capacitance element group. A first switch means composed of a plurality of switches, one of which is connected to the input voltage and at least one reference voltage, and the other corresponding to the other end of the another plurality of capacitance elements of the second capacitance element group A second switch means composed of a plurality of switches connected to each other, one end of each of the first and second capacitive element groups commonly connected to the plus side input of the comparator and Input selection means for switching to and connecting to the minus side input, driving the input selection means based on A / D conversion accuracy, the first capacitance element group and the second capacitance element group To generate a reference voltage or a dummy load.

Further, the A / D converter of the present invention includes a plurality of switches and a plurality of capacitance elements, a D / A conversion unit for switching an analog input voltage and a plurality of reference voltages, and a common input for a plus side input and a minus side input. A function of connecting the input voltage and the release voltage, and a comparator for comparing the input voltage and the plurality of reference voltages, and outputting a digital signal by logically converting a positive-phase output or a negative-phase output of the comparator. An A / D converter having a logic circuit for controlling the D / A conversion unit, wherein one ends of a plurality of capacitive elements are connected in common, and the commonly connected ends are connected to the minus input of the comparator. One end of another first capacitance element group and another plurality of capacitance elements formed with the same capacitance as the capacitances of the plurality of capacitance elements are connected in common and connected in common. A second capacitive element group having one end connected to the positive input of the comparator, and a plurality of capacitive elements each having one connected to the input voltage and at least one reference voltage and the other being connected to the first capacitive element group A first switch means composed of a plurality of switches connected in correspondence with the other end of the second capacitance element group, one of which is connected to the input voltage and at least one reference voltage, and the other of which is connected to the other of the second capacitance element group. A second switch means including a plurality of switches connected to the other ends of the plurality of capacitive elements, and an output for switching and connecting the positive-phase output and the negative-phase output of the comparator to the logic circuit; Selecting means for driving the output selecting means based on A / D conversion accuracy to generate a reference voltage for the first capacitive element group and the second capacitive element group. Configured to determine a dummy load.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an A / D converter showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment also has a 3 bit
Is the case.

First, the capacity ratio of 2 ^0: 2 ^0: 2 ^1: capacitive element C ₁ in 2 ² relations,
One of the electrodes C ₂ , C ₃ , and C ₄ is commonly connected, and the other electrode is connected to one end of each of the switches S ₁ , S ₂ , S ₃ , and S ₄ to form a first D / A converter. Is composed. Similarly, the capacitive elements C ₅ ,
C ₆ , C ₇ , C ₈ are also connected to the switches S ₅ , S ₆ , S ₇ , S ₈ and the first D / A
A second D / A converter similar to the converter is configured. The comparator 1 has differential inputs, and switches S ₉ and S ₉ are connected between the respective (+) side and (−) side inputs and ground.
₁₀ is connected. These switches S ₉ and S ₁₀ are turned on during the precharge period, and are provided for determining the input bias level. A second D / A conversion unit and a first D / A conversion unit are respectively formed on the (−) side input of the differential input of the comparator 1 via the switches S ₁₁ and S _12. It is connected to the common end of the capacitive element. Similarly,
(+) Input side is connected to the common terminal of the capacitive element constituting converting section first D / A and the second D / A conversion unit respectively through the switches S _13, S _14. These switches S ₁₁ , S
Select signal phi _S to _13, switches S _12, S ₁₄ are supplied to the signal obtained by inverting the phi _S inverter L2. On the other hand, the output O of the comparator 1 is supplied to the logic circuit (L) 2 Thereafter, the signal D ₁ and the A / D to control a switch S ₁ to S ₄ or switches S ₅ to S ₈ by the value of the output O Conversion result D
_{And 2} are output.

 Next, a detailed operation of the A / D converter will be described.

FIG. 2 is a drive signal waveform diagram of the switch shown in FIG.

As shown in FIG. 2, is shown here signal phi _B applied to the switch S ₉ to S _14, and phi _S, a contact potential of the switch S ₁ to S ₄ and S ₅ to S _8. Here, a select signal phi _S is "0", the order switch S _12, S ₁₄ are turned on, the switch S _11, S ₁₃ are turned off. This select signal φ _S
Does not change except in special cases. With this
S ₅ ~S ₈ also remains connected to the ground side.

First, first phi _B is "1", the switch S _9, S ₁₀ are turned on, a differential input is biased. At the same time, the switches S _{1 to} S ₄ are connected to the input V _IN and the capacitance elements C _{1 to} C
₄ stores the input potential. Next, φ _B becomes “0”,
At the same time as the bias is cut off, the D / A conversion unit sets the reference voltage (V _F ⁺ −
V _F ^-) for outputting the level of 1/2 of the. Specifically, switch S ₄
Is V _F ^+, also switches S _1, S _2, S ₃ is V _F ^- (only the switch S ₁ is V _F in the binary search period ^- remains) at by subsequent logical value of the output O of the comparator 1 "0" If (V _F ⁺ −
V _F ⁻ ) / 4, or “1”, the signal is processed by the logic circuit (L) 2 so that the D / A conversion unit is set to (V _F ⁺ −V _F ⁻ ) × 3/4. .

In the case of a 3-bit low-resolution A / D converter as in the present embodiment, no problem occurs. However, in an A / D converter of 8 to 10 bits or more, the capacity used in the D / A conversion unit The relative accuracy of the elements becomes a problem. Because of this, the usual 10
In the bitA / D converter, a defect of about 5% occurs. Therefore, by the above-described operation, if the if the characteristic does not satisfy the standard, by changing the select signal φ _S "1"
And Then, instead of the first D / A converter, the second D / A
The conversion unit is switched and connected to the (−) side input of the comparator 1. The work with the switches S ₁ to S ₄ until now it has been done subjected switch S ₅ to S _8, the operation of switches S ₅ to S ₈ have been carried out on the opposite switch S ₁ to S ₄ is performed. In this way, it until capacity the capacitor C ₅ -C ₈ that were connected in order to increase the common-mode rejection ratio of the differential input not out and accurately place for level generation of the D / A converter By replacing the elements C _{1 to} C ₄ with the dummy load, the failure rate can be drastically reduced to (5%) ² = 0.25%.

At this time, the select signal phi _S normally be set by the PROM, as if once measured within specifications during IC manufacture, in the case of failure can change the polarity of the signal by writing data the PROM.

FIG. 3 is a circuit diagram of an A / D converter showing a second embodiment of the present invention.

Third, as shown in FIG., The embodiment is the capacitive element C ₁ -C ₄ and the first D / A converter unit comprising a switch S ₁ to S _4, the capacitive element C ₅ -C ₈ and Switches C ₅ ~ the second D / a conversion section consisting of C ₈ is exactly the same as the first embodiment described above. The switch S _9, S ₁₀ the input side of the comparator 1 is also the same as phi _B is turned on when "1" is connected between the ground.

This embodiment is different from the above-described first embodiment in that the (-) input of the comparator 1 becomes the output of the first D / A converter,
Further, the (+) input is directly connected to the output of the second D / A converter. The output of the comparator 1 is connected to the switch S ₁₅ to the (+) output, yet (-) switch S ₁₆ is connected to the output. The opposite sides of the switches S ₁₅ and S ₁₆ are collectively used as the output terminal O of the comparator 1. These switches S _16, S _15, and the select signal phi _S respectively, the inverted signal obtained by inverting ▲ ▼ and are input by the inverter I _2. Thus, the switch S ₁₅ when the select signal phi _S is "0" is turned on, the reverse to the select signal phi _S is the switch S ₁₆ is turned on when the "1".

That is, in the first embodiment, the input side of the comparator 1 is switched, whereas in the present embodiment, the output side is switched. According to this method, there is an advantage that the stray capacitance of the input is reduced.

Although the present embodiment has been described above, in the present embodiment, the pseudo load capacitance at one of the differential inputs has the same configuration as that of the D / A converter, and when the accuracy of one of the D / A converters is not obtained, the other is used. By using the D / A conversion unit including the capacitive element group described above, the probability of occurrence of accuracy failure can be significantly reduced.

Also, since the relative variation of the capacitance element is a matter of probability, it is averaged by increasing the area of the capacitance element,
This is disadvantageous in terms of the degree of integration. Therefore,
Although the probability of variation is a little large, a compact group of capacitive elements can be prepared and actually A / D converted, and the one with higher accuracy can be used as the D / A converter.

〔The invention's effect〕

As described above, in the A / D converter of the present invention, a plurality of groups of capacitance elements are provided, and a pseudo load capacitance element formed by one group of capacitance elements is made to have the same configuration as that of the D / A conversion unit, and the electric charge is regenerated. Distribution type D
By using it as a / A conversion unit, the other D / A conversion unit can be used when the accuracy of one D / A conversion unit is not high, so that the relative accuracy is prevented from deteriorating and the probability of occurrence of poor accuracy is reduced. This has the effect of greatly reducing the precision and improving the manufacturing yield.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an A / D converter showing a first embodiment of the present invention, FIG. 2 is a drive signal waveform diagram of a switch shown in FIG. 1,
FIG. 3 is a circuit diagram of an A / D converter showing a second embodiment of the present invention, FIG. 4 is a circuit diagram of an A / D converter showing an example of the prior art, and FIG. FIG. 4 is a drive signal waveform diagram of a switch. 1... Comparator, 2... Logic circuit (L), C ₁ to
C ₄ ...... first capacitive element group, C ₅ ~C ₈ ...... second capacitive element group, S ₁ ~S ₁₆ ...... switch, I _1, I ₂ ...... inverter.

Claims (2)

(57) [Claims] A plurality of switches and a plurality of capacitive elements for switching an analog input voltage and a plurality of reference voltages;
A D / A converter, having a function of connecting or releasing the positive side input and the negative side input to a common potential, a comparator for comparing the input voltage and the plurality of reference voltages, and an output of the comparator In the A / D converter having a logic circuit that outputs a digital signal by logically converting and a logic circuit that controls the D / A converter, a first capacitive element group in which one ends of a plurality of capacitive elements are commonly connected. And a second capacitive element group in which one ends of another plurality of capacitive elements formed of the same capacitance as the capacitances of the plurality of capacitive elements are connected in common, and one of each is connected to the input voltage and at least one reference voltage. A first switch means comprising a plurality of switches and the other is connected corresponding to the other end of the plurality of capacitive elements of the first capacitive element group,
A second switch comprising a plurality of switches, one of which is connected to the input voltage and at least one reference voltage, and the other of which is connected to the other end of the other plurality of capacitance elements of the second capacitance element group. Switch means, and input selection means for switching and connecting one end of each of the first and second capacitive element groups that are commonly connected to the plus side input and the minus side input of the comparator And driving the input selection means based on A / D conversion accuracy to determine whether the first capacitor element group and the second capacitor element group generate a reference voltage or whether to use a pseudo load. An A / D converter characterized by determining. A plurality of switches and a plurality of capacitance elements for switching an analog input voltage and a plurality of reference voltages;
A D / A converter, a function of connecting and disconnecting a positive input and a negative input to a common potential, a comparator for comparing the input voltage and the plurality of reference voltages, and a positive In the A / D converter having a logic circuit that controls the D / A conversion unit while outputting a digital signal by logically converting the phase output or the reverse phase output, one end of a plurality of capacitive elements is commonly connected. One end of the first capacitive element group having one end connected in common to the negative input of the comparator and one end of another plurality of capacitive elements formed with the same capacitance as the capacitances of the plurality of capacitive elements. And a second group of capacitive elements, one end of which is connected to the common side and the other end of which is connected to the plus side input of the comparator. A first switch means comprising a plurality of switches connected to a reference voltage and the other connected to the other ends of the plurality of capacitance elements of the first capacitance element group, one of which is an input voltage and at least one of A second switch means comprising a plurality of switches connected to one reference voltage and the other connected to the other ends of the plurality of other capacitive elements of the second capacitive element group; and Output selection means for switching and connecting the positive-phase output and the negative-phase output to the logic circuit, and driving the output selection means based on A / D conversion accuracy, the first capacitive element An A / D converter, which determines whether to generate a reference voltage or a dummy load for the group and the second capacitive element group.