JP2953014B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which a bipolar transistor and a MOS transistor are integrated on the same chip.
The present invention relates to an iMOS semiconductor integrated circuit.

[Conventional technology]

EC for fast operation of unsaturated bipolar transistor
BiMOS for L (emitter coupled logic) output circuit
When it is constituted by a circuit, it is generally realized by a circuit as shown in FIG. That is, those comprising a logic amplitude of an internal circuit of BiMOS level conversion circuit for converting the logical amplitude of the ECL, power generation circuit V _CS and V _R, from the constant current generating circuit further power switching circuit.

This circuit configuration has features such as realizing high-speed operation, while maintaining the amplitude of the base potential of the bipolar transistor constant regardless of the power supply voltage and manufacturing variations.

As shown in FIG. 4, a similar circuit is installed between the positive potential power supply and the ground potential. The so-called offset ECL output circuit is connected to a TTL circuit or a CMOS circuit via a level conversion circuit while maintaining high speed. The method used is also taken.

In particular, the offset ECL output circuit configured between the positive potential power supply and the ground potential is in high demand for high-speed graphics and computer peripheral devices.
The incorporation into the chip is shouted.

[Problems to be solved by the invention]

The ECL output circuit using the BiMOS circuit has the following problems. First, there is an increase in power consumption and difficulty in circuit design using a power supply generation circuit and the like.

For example, the power consumption of a BiMOS circuit is normally about the same as that of a CMOS, so it is as small as several hundred mW, and although it has a high thermal resistance, it can be mounted in an inexpensive mold package. However, if a conventional ECL output circuit is introduced, it will be several watts,
As with general ECL devices, cooling considerations were required, affecting not only the cost of expensive packages and airflow conditions, but also the system design. or,
In terms of circuit design, it is necessary to configure a power supply generating circuit for a constant current circuit or a current switch circuit, and the design usually requires a high degree of skill and time.

Second, in the ECL output circuit using the conventional BiMOS circuit,
Since the level conversion circuit is required, there is a disadvantage that the high speed of the original ECL output circuit cannot be fully utilized.

An object of the present invention is to provide a semiconductor integrated circuit which suppresses power consumption and has high speed.

[Means for solving the problem]

The semiconductor integrated circuit according to the present invention has a so-called ECL (emitter / emitter) which has a bipolar transistor at an output stage connected between a ground potential and a negative potential power supply and having a collector connected to the ground potential.
In a coupled logic) output circuit, a driving resistor connected between a base and a ground potential of the bipolar transistor, a source connected to a negative potential power supply, and a gate connected to an input terminal of the ECL output circuit. A drain of a channel MOS transistor, a constant current generating circuit having a first resistor connected between the base and the negative potential power supply of the bipolar transistor, and a drain and a second of a second N-channel MOS transistor having a gate and a drain connected. A resistor has a logic amplitude temperature-compensated at the base of the bipolar transistor by a temperature compensation circuit connected in series between the ground potential and the drain of the first N-channel MOS transistor of the constant current generation circuit. .

Further, if the ground potential is changed to the positive potential power source and the negative potential power source is changed to the ground potential, it can be used as an offset ECL output circuit that operates between the positive potential power source and the ground potential.

〔Example〕

Next, the circuit operation according to the present invention will be specifically described. FIG. 1 shows an embodiment of the present invention. First, the input terminal V _IN
In the case where the “L” level (〜V _EE ) is input from the internal circuit. Since N-channel MOS transistor 1 is turned off, the base potential V _B of the bipolar transistor 3 rises to approximately ground potential, the output terminal V _O outputs "H" level, Becomes This is the same as a general ECL-10KH output circuit, and has the same temperature characteristics as the base-emitter voltage of a bipolar transistor.

Next, when an “H” level (〜0 V) is input to the input terminal V _IN , the N-channel MOS transistor 1 is turned on, and the current I
Subtract _zero . At this time, current is drawn from both the path of the N-channel MOS transistor 2 and the path to which the bipolar transistor 3 is connected. At this time, the drain potential _VA of the N-channel MOS transistor 1 does not _drop to VEE.
That is, the resistances of R _{1 to} R ₃ and the dimensions of the N-channel MOS transistor 2 are adjusted so that the N-channel MOS transistor 1 does not enter the linear region. Here, considering the temperature dependency, the current drive capability of the N-channel MOS transistor 1 decreases (the threshold voltage increases) and I ₀ decreases with the temperature rise, while the N-channel MOS transistor 2 current driving capability decreases (Suresshuhorudo voltage increases), the base potential V _B of the bipolar transistor 3 as a result to reduce even I ₃ can be kept constant with respect to temperature.

The method for determining the circuit constant will be described below. First, considering the node A, I ₂ + I ₃ = I ₀ → I ₂ = I ₀ −I ₃ (1) I ₁ R ₁ + I ₂ R ₂ = I ₃ R ₃ + V _X (where V _X = | V _C −V _A |) …… (2) Substituting (1) into (2) and deforming I ₁ R ₁ = I ₃ R ₃ + V _X − (I ₀ −I ₃ ) R ₂ Differentiation by temperature T Since I ₀ and I ₃ all indicate the ON current of the MOS, If R ₂ and R ₃ are made of the same material (impurity implantation) Therefore, equation (3) is Here, the current of the N-channel MOS transistor is It is represented by (W ₃ and L ₃ are N-channel MOS transistors 2
Is the mobility, C _OX is the capacitance due to the gate oxide film. Substituting (5) into (4) That is, in equation (6) To make Equation (7) indicates that if the N-channel MOS transistor 1 is used as a basis, the gate length of the N-channel MOS transistor 2 should be half of that. R ₃ can also be determined by equation (8). ( Is measured in advance from the element characteristics. )further (9) determine the I ₁ by determining the design center of the V _OL by the formula, from which (10) determining the R ₁ by equation. (V _F3 is the base-emitter voltage of the bipolar transistor 3) Finally R ₂ is Can be determined by

〔The invention's effect〕

As described above, the present invention does not use the power generation circuit and the constant current circuit in the ECL output circuit constituted by the BiMOS circuit, so that the steady current is only at the time of "L" output, and the power consumption is about 1/2. In addition, the N-channel MOS transistor also has an operating point outside the linear region, and does not require a level conversion circuit, thereby having high speed.

In particular, the present invention is more effective when used in an offset ECL output circuit, and can be mounted on a relatively inexpensive mold package.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing a second embodiment of the present invention, and FIGS. 3 and 4 are diagrams showing a conventional example. 1,2 ... N-channel MOS transistor, 3 ... Bipolar transistor, 4,5,6 ... Resistance.

Claims (2)

(57) [Claims] A bipolar transistor connected between a first power supply and a second power supply; a driving resistor connected between a base of the bipolar transistor and the first power supply;
A first N-channel MOS transistor having a source connected to the second power supply and a gate connected to the input terminal; a drain and a first resistor of the first N-channel MOS transistor being connected to the base of the bipolar transistor and the second transistor; A constant current generating circuit connected between the two power supplies, a second N-channel MOS transistor having a gate and a drain connected thereto, and a drain and a second resistor of the second N-channel MOS transistor connected to the first power supply. And a temperature compensating circuit connected in series between the drains of the first N-channel MOS transistors of the constant current generating circuit. 2. A bipolar transistor connected between a first power source and a second power source, a driving resistor connected between a base of the bipolar transistor and the second power source, and a source connected to the first power source. A first N-channel MOS transistor having a gate connected to the input terminal; a drain connected to the drain of the first N-channel MOS transistor and a first resistor connected to the base of the bipolar transistor and the first power supply; A current generating circuit, a drain of a second N-channel MOS transistor having a gate and a drain connected thereto, and a second resistor connected in series between the second power supply and a drain of the first N-channel MOS transistor of the constant current generating circuit; A semiconductor integrated circuit having a temperature compensation circuit connected thereto.