JP2953178B2 - High voltage switch - Google Patents
High voltage switchInfo
- Publication number
- JP2953178B2 JP2953178B2 JP5452992A JP5452992A JP2953178B2 JP 2953178 B2 JP2953178 B2 JP 2953178B2 JP 5452992 A JP5452992 A JP 5452992A JP 5452992 A JP5452992 A JP 5452992A JP 2953178 B2 JP2953178 B2 JP 2953178B2
- Authority
- JP
- Japan
- Prior art keywords
- snubber
- voltage switch
- high voltage
- circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Generation Of Surge Voltage And Current (AREA)
- Lasers (AREA)
Description
【0001】[0001]
【産業上の利用分野】この発明は、パルスレーザ等のパ
ルス発生回路を構成する高電圧スイッチに関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage switch constituting a pulse generation circuit for a pulse laser or the like.
【0002】[0002]
【従来の技術】以下説明においては高電圧スイッチが使
われる銅蒸気レーザの回路を用いて説明する。図1、図
2は例えば特開平3−226114号公報に記載の、銅
蒸気レーザのパルス発生回路を示すもので、1は高圧電
源、2は充電用リアクトル、3は充電用ダイオード、4
はコンデンサ、5はピーキングコンデンサ、6はレーザ
放電管、7は充電用抵抗、8は高電圧スイッチ、9はス
ナバ回路、10はトリガ回路、11は回路配線のインダ
クタンス、12はスナバダイオード、13はスナバコン
デンサ、14はスナバ抵抗、15はFETである。2. Description of the Related Art In the following description, a circuit of a copper vapor laser using a high voltage switch will be described. 1 and 2 show a pulse generator of a copper vapor laser described in, for example, JP-A-3-226114, in which 1 is a high-voltage power supply, 2 is a charging reactor, 3 is a charging diode,
Is a capacitor, 5 is a peaking capacitor, 6 is a laser discharge tube, 7 is a charging resistor, 8 is a high voltage switch, 9 is a snubber circuit, 10 is a trigger circuit, 11 is inductance of circuit wiring, 12 is a snubber diode, and 13 is a snubber diode. A snubber capacitor, 14 is a snubber resistor, and 15 is an FET.
【0003】次に動作について説明する。高圧電源1に
よって発生される高圧電圧は充電リアクトル2、充電用
ダイオード3、充電用抵抗7を通して、放電用コンデン
サ4に高圧電圧を充電する。トリガ回路10によって発
生されたトリガ信号が高電圧スイッチ8を構成するFE
T15に入力されると高電圧スイッチ8が導通し、放電
用コンデンサ4に蓄えられた電圧が回路配線のインダク
タンス11を通りレーザ放電管6に供給され、レーザ発
振を得る。上記の動作を数kHzにて繰り返す。銅蒸気
レーザはパルスレーザであり一般的に、レーザ放電管6
内に流れる電流は急峻であればあるほどレーザ効率が上
昇する。そのため、回路配線のインダクタンス11等は
できるだけ小さく(約300nH程度)することが必要
である。ピーキングコンデンサ5は回路配線のインダク
タンス11によるレーザ放電管6に流れる電流のなまり
を解消するために設けられている。また、スナバ回路9
は直列接続されたFET15の特定の並列段の導通タイ
ミングが遅れた場合に、その段に過電圧が印加されてF
ET15が破壊するのを防止するために設けられたもの
である。図2はスナバ回路9の詳細を示すものであり、
導通タイミングが遅れた場合には、スナバダイオード1
2を通してスナバコンデンサ13に回路電流is をバイ
パスする。スナバコンデンサ13を十分に大きくしてお
くことでis の流入による電圧上昇を小さくでき、FE
T15を過電圧から保護することができる。スナバコン
デンサ13に流入した電荷は繰り返し周期の休止期間中
に放出する。なお、タイミングの遅れはトリガ回路10
内の配線のばらつきや部品のばらつき等によって生じ
る。Next, the operation will be described. The high voltage generated by the high voltage power supply 1 passes through the charging reactor 2, the charging diode 3, and the charging resistor 7, and charges the discharging capacitor 4 with the high voltage. The trigger signal generated by the trigger circuit 10 constitutes the high voltage switch 8
When input to T15, the high voltage switch 8 is turned on, and the voltage stored in the discharge capacitor 4 is supplied to the laser discharge tube 6 through the inductance 11 of the circuit wiring to obtain laser oscillation. The above operation is repeated at several kHz. The copper vapor laser is a pulsed laser and generally has a laser discharge tube 6.
The steeper the current flowing inside, the higher the laser efficiency. Therefore, it is necessary that the inductance 11 and the like of the circuit wiring be as small as possible (about 300 nH). The peaking capacitor 5 is provided to eliminate the rounding of the current flowing through the laser discharge tube 6 due to the inductance 11 of the circuit wiring. The snubber circuit 9
If the conduction timing of a specific parallel stage of the FET 15 connected in series is delayed, an overvoltage is applied to that stage and F
This is provided to prevent the ET 15 from being destroyed. FIG. 2 shows details of the snubber circuit 9.
If the conduction timing is delayed, the snubber diode 1
2, the circuit current is bypassed to the snubber capacitor 13. By making the snubber capacitor 13 sufficiently large, the voltage rise due to the inflow of is can be reduced, and the FE
T15 can be protected from overvoltage. The electric charge that has flowed into the snubber capacitor 13 is released during the rest period of the repetition cycle. Note that the timing delay is caused by the trigger circuit 10.
It is caused by the variation of the wiring in the inside and the variation of the components.
【0004】[0004]
【発明が解決しようとする課題】従来の銅蒸気レーザ用
に用いられる高電圧スイッチは上記のように構成されて
いるため、特定の並列段のタイミング遅れが繰り返し発
生すると、繰り返し周期の休止期間中にスナバコンデン
サ13に流入した電荷が完全に放出できず、スナバコン
デンサ13の電圧が上昇して、スナバの本来の機能が低
下するという問題があった。Since the high-voltage switch used for the conventional copper vapor laser is constructed as described above, if the timing delay of a particular parallel stage repeatedly occurs, the high-voltage switch during the repetition period is inactive. In addition, the electric charge flowing into the snubber capacitor 13 cannot be completely discharged, so that the voltage of the snubber capacitor 13 increases, and the original function of the snubber deteriorates.
【0005】この発明は上記のような問題点を解消する
ためになされたもので、特定の並列段のタイミング遅れ
が繰り返し発生しても、スナバコンデンサ13の電圧が
異常に上昇せず、スナバの本来の機能を維持することが
可能な高電圧スイッチを得ることを目的とする。The present invention has been made in order to solve the above-mentioned problems. Even if the timing delay of a specific parallel stage occurs repeatedly, the voltage of the snubber capacitor 13 does not rise abnormally, and An object is to obtain a high-voltage switch capable of maintaining its original function.
【0006】[0006]
【課題を解決するための手段】この発明に係る高電圧ス
イッチは、スイッチ回路のインダクタンスをL1 、高電
圧スイッチのスイッチング時間をton、複数の半導体の
導通タイミングのばらつきの最大値をτc 、半導体の直
列数をk、スイッチングの繰り返し周波数をfとした
時、スナバ抵抗の大きさを6L1・ton /(τc 3f(k
−1))より小さくしたものである。According to the high voltage switch of the present invention, the inductance of the switch circuit is L 1 , the switching time of the high voltage switch is t on , and the maximum value of variation in the conduction timing of a plurality of semiconductors is τ c. When the number of series semiconductors is k and the switching repetition frequency is f, the size of the snubber resistor is 6L 1 · t on / (τ c 3 f (k
-1)).
【0007】[0007]
【作用】この発明に係わる高電圧スイッチにおいては、
スナバ抵抗の大きさを 6L1・ton/(τc 3f(k−1)) より小さくしたため、タイミングの遅れによってスナバ
コンデンサに流入した電荷を繰り返し周期の休止期間中
に十分に放出できる。In the high voltage switch according to the present invention,
Since the size of the snubber resistance is smaller than 6L 1 · t on / (τ c 3 f (k-1)), the charge flowing into the snubber capacitor due to the timing delay can be sufficiently released during the rest period of the repetition period.
【0008】[0008]
【実施例】実施例1.以下、請求項1に示したスナバ抵
抗14の制限条件について説明する。高電圧スイッチ8
はFET15がk段直列に接続されているものとする。
特定の並列段のタイミングが遅れた場合の等価回路を図
3に示す。Vd は放電用コンデンサ4に蓄えられた電
圧、13a はタイミングが遅れた並列段のスナバコンデ
ンサであり、容量をCs とする。放電用コンデンサ4に
Vdが充電された際には、k個直列されたFET15の
両端には均等に電圧が分配されているものとする。この
とき、高電圧スイッチ8のスイッチング時(スイッチン
グ時間ton中には特定の段以外のFET15は図4に示
されるように単調に電圧が低下するものとする)にスナ
バコンデンサ13a に流れ込む電流i( t)は以下のよう
になる。[Embodiment 1] Hereinafter, the limiting condition of the snubber resistor 14 will be described. High voltage switch 8
Assume that the FETs 15 are connected in k stages in series.
FIG. 3 shows an equivalent circuit when the timing of a specific parallel stage is delayed. Vd is the voltage stored in the discharging capacitor 4, 13a is a parallel-stage snubber capacitor with a delayed timing, and the capacitance is Cs. When the discharge capacitor 4 is charged with Vd, it is assumed that the voltage is uniformly distributed to both ends of the k series FETs 15. At this time, the current i flowing into the snubber capacitor 13a at the time of switching of the high voltage switch 8 (assuming that the voltage of the FET 15 other than the specific stage monotonously decreases as shown in FIG. 4 during the switching time t on ). ( t ) is as follows.
【0009】[0009]
【数1】 (Equation 1)
【0010】よって、タイミング遅れの時間をτcとす
れば、τcまでにスナバコンデンサ13に流入した電荷
量はTherefore, if the time of the timing delay is τc, the amount of charge flowing into the snubber capacitor 13 up to τc is
【0011】[0011]
【数2】 (Equation 2)
【0012】となる。流入した電荷量を繰り返し周期の
休止期間中に放出するためには、## EQU1 ## In order to discharge the inflowing charge during the rest period of the repetition cycle,
【0013】[0013]
【数3】 (Equation 3)
【0014】となる。よって、左辺の第2項を展開して
Rcの許容値を求めれば Rc<6L1・ton/(τc 3f(k−1)) となる。つまり、図5に示すように、τc にて流入した
電荷が約1/fの期間にて放出され、スナバコンデンサ
13a の電圧をVd /kまで下げることで、タイミング
遅れが繰り返し発生しても、スナバコンデンサ13の電
圧がVd /k以上にならず、確実にスナバ機能を維持す
ることができる。もし、休止期間中にスナバコンデンサ
13a への流入電荷を放出できない場合には図5の点線
に示したように、電圧が除々に増加して、スナバ機能が
低下してしまう。## EQU1 ## Therefore, by obtaining the tolerance of Rc expand the second term of the left side Rc <6L 1 · t on / (τ c 3 f (k-1)) and becomes. In other words, as shown in FIG. 5, even if the charge that flows in at τc is released during a period of about 1 / f and the voltage of the snubber capacitor 13a is reduced to Vd / k, even if the timing delay occurs repeatedly, The voltage of the snubber capacitor 13 does not exceed Vd / k, and the snubber function can be reliably maintained. If the electric charge flowing into the snubber capacitor 13a cannot be released during the idle period, the voltage gradually increases as shown by the dotted line in FIG. 5, and the snubber function decreases.
【0015】[0015]
【発明の効果】以上のように、この発明によればスナバ
抵抗の大きさを 6L1・ton/(τc 3f(k−1)) より小さくしたので、タイミング遅れが繰り返し発生し
ても、スナバコンデンサの電圧が異常に上昇せず、安定
なスナバ機能を維持することができ、信頼性の高い高電
圧スイッチが得られる効果がある。As described above, according to the present invention, the size of the snubber resistance is made smaller than 6L 1 · t on / (τ c 3 f (k-1)), so that the timing delay occurs repeatedly. However, there is an effect that the voltage of the snubber capacitor does not abnormally increase, a stable snubber function can be maintained, and a highly reliable high-voltage switch can be obtained.
【図1】パルスレーザ用パルス発生回路を示す回路図で
ある。FIG. 1 is a circuit diagram showing a pulse generation circuit for a pulse laser.
【図2】高電圧スイッチのスナバ回路を示す回路図であ
る。FIG. 2 is a circuit diagram showing a snubber circuit of a high-voltage switch.
【図3】タイミング遅れ時の等価回路を示す回路図であ
る。FIG. 3 is a circuit diagram showing an equivalent circuit at the time of timing delay.
【図4】FETのスイッチング特性を示す特性図であ
る。FIG. 4 is a characteristic diagram showing switching characteristics of the FET.
【図5】この発明の一実施例による高電圧スイッチの動
作を説明する説明図である。FIG. 5 is an explanatory diagram illustrating the operation of the high-voltage switch according to one embodiment of the present invention.
8 高電圧スイッチ 9 スナバ回路 10 トリガ回路 11 回路配線のインダクタンス 12 スナバダイオード 13 スナバコンデンサ 14 スナバ抵抗 15 FET 8 High voltage switch 9 Snubber circuit 10 Trigger circuit 11 Inductance of circuit wiring 12 Snubber diode 13 Snubber capacitor 14 Snubber resistor 15 FET
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01S 3/097 - 3/0977 H02M 9/04 H03K 3/57 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 6 , DB name) H01S 3/097-3/0977 H02M 9/04 H03K 3/57
Claims (1)
両端にダイオードとコンデンサとの直列回路を並列に接
続し、上記コンデンサの両端に抵抗を並列に接続して構
成され、上記複数の半導体を外部からのトリガ信号によ
って一斉に導通する高電圧スイッチにおいて、L1 をス
イッチ回路のインダクタンス、tonを上記高電圧スイッ
チのスイッチング時間、τc を上記複数の半導体の導通
タイミングのばらつきの最大値、kを上記半導体の直列
数、fをスイッチングの繰り返し周波数とした時、上記
抵抗の大きさを6L1・ton /(τc 3f(k−1))より
小さく構成したことを特徴とする高電圧スイッチ。1. A semiconductor device comprising: a plurality of semiconductors connected in series; a series circuit of a diode and a capacitor connected in parallel to both ends of each semiconductor; and a resistor connected in parallel to both ends of the capacitor. In a high voltage switch that conducts all at once by an external trigger signal, L 1 is the inductance of the switch circuit, t on is the switching time of the high voltage switch, and τ c is the maximum value of the variation in the conduction timing of the plurality of semiconductors. , K is the series number of the semiconductor and f is the switching repetition frequency, the magnitude of the resistor is smaller than 6L 1 · t on / (τ c 3 f (k-1)). High voltage switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5452992A JP2953178B2 (en) | 1992-03-13 | 1992-03-13 | High voltage switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5452992A JP2953178B2 (en) | 1992-03-13 | 1992-03-13 | High voltage switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05259551A JPH05259551A (en) | 1993-10-08 |
| JP2953178B2 true JP2953178B2 (en) | 1999-09-27 |
Family
ID=12973195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5452992A Expired - Lifetime JP2953178B2 (en) | 1992-03-13 | 1992-03-13 | High voltage switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2953178B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4839263B2 (en) * | 2007-05-30 | 2011-12-21 | 東芝三菱電機産業システム株式会社 | Semiconductor switch device |
-
1992
- 1992-03-13 JP JP5452992A patent/JP2953178B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05259551A (en) | 1993-10-08 |
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