JP2956355B2 - Video signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal generator suitable for use in inspection or evaluation of a video signal processor or the like.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional video signal generating apparatus using digital processing.

[0003] In FIG. 6, 60 denotes an input terminal of the clock Nf _H, 61 is an address counter, 62 a memory, 63 a D / A converter, 64 is a low pass filter (LPF), 6
5 is a buffer, and 66 is an output terminal of a video signal.

A video signal for one scanning line is stored in a memory 62,
Direct digital data quantized is written at the timing of the clock Nf _H. Simultaneously reading the digital data by a counter 61 at the timing of the clock Nf _H, it is converted into an analog signal by a D / A converter 63, a video signal having a harmonic component as shown in FIG. When unnecessary harmonic components are removed from the video signal by the low-pass filter 64, a smooth video signal is obtained from the output terminal 66.

[0005]

In an image signal generating apparatus, obtaining an image having an oblique component as shown in FIGS. 5A and 5B requires crossing an image having only vertical and horizontal components with respect to an image having only a vertical and horizontal component. It is very effective for inspection of color disturbance and the like and evaluation of a high-definition television system by next-generation digital processing. However, in the above-described conventional video signal generating apparatus, since the synchronizing signal, the luminance signal, the burst signal, and the chrominance signal constituting one scanning line are all stored in the memory 62 as digital data in a combined state, When an image having an oblique component is to be realized as described above, different digital data is obtained for each scanning line. As a result, a frame memory for storing digital data of video signals corresponding to the number of scanning lines constituting one screen is required, and in order to generate a plurality of oblique images, an increase in the size of the apparatus and an increase in cost are inevitable. There was a problem.

The present invention solves such a conventional problem, and a video signal giving an image having an oblique component can be easily generated only with a line memory without using a frame memory. Therefore, it is an object of the present invention to provide a video signal generating device capable of reducing the size and cost of the device.

[0007]

The technical means of the present invention for achieving the above object is to provide a synchronizing signal with a luminance signal , a chrominance signal and a synchronizing signal.
A / D converted data of the signal and the color subcarrier signal are stored.
A memory for reading data stored in the memory;
From the flat address generating means and the horizontal address generating means
A tie for extracting data for the effective image period for each scan line
Vertical memo for storing vertical control data
And the vertical direction control for each scanning line from the vertical memory.
Vertical address generating means for reading data, and the memory
The luminance signal and the chrominance signal stored in
Data during the vertical blanking period based on the
Stop shifting the clock, and during the horizontal blanking period
Even if the read address is shifted, the effective image
After shifting into the range, the address is sequentially shifted and read
An address control unit for performing an operation for each scanning line;
Data read from the memory controller and stored in the memory
Calculation means for performing a superposition calculation of the obtained synchronization signal and the color sub-carrier signal .

[0008]

The arithmetic processing means includes a color difference signal.
Digital data and color subcarrier signal digital data
Multiplying means for obtaining modulated wave digital data, and means for adding the two modulated wave digital data and adding the luminance signal digital data and the synchronization signal digital data to the addition result. it can.

[0010]

Therefore, according to the present invention, the output timing of the luminance signal digital data and the two color difference signal digital data is varied in units of scanning lines by the address control unit, so that the video signal digital data for all the scanning lines is stored. A video signal giving an image having an oblique component can be generated only with a line memory corresponding to one scanning line without requiring a frame memory.

Further, by preparing various vertical control data for varying the output timing of the digital data, various oblique components can be given to one image.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing a video signal generator according to one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a memory holding luminance signal digital data D _Y quantized by a clock Nf _H (N = integer) synchronized with a line frequency f _H , 2 and 3
Memory held by two mutually orthogonal quantized in clock Nf _H synchronized with the line frequency f _H RY and BY color difference signals digital data D _RY and D _BY, respectively, the 4 line frequency f _H Synchronized clock Nf _H
The memories 5 and 6 which hold the synchronization signal digital data D _S quantized by the above are color co-carrier signal digital data D cos and two cos θ and sin θ orthogonal to each other, quantized by the clock Nf _H synchronized with the line frequency f _H. Dsin is stored in each memory, 7 is memories 1, 2,
Address control unit that controls so as to sequentially shifting every three timing of reading the digital data held by one scan line, 8 reads a digital data memory 4, 5, 6 are held at a fixed timing clock Nf _H counter, 9 is a digital multiplier multiplies the chrominance subcarrier signal digital data Dcos read from the color difference signal digital data D _RY and memory 5 which is read from the memory 2, the color difference signal digital read from the memory 3 The data D _BY is multiplied by the color subcarrier signal digital data Dsin read from the memory 6 to obtain RY modulated wave digital data and BY modulated wave digital data, respectively. Reference numeral 10 denotes a digital adder, which includes RY and B-
Y modulated wave digital data is added, and the luminance signal digital data D read from the memory 1 is added to the addition result.
Adds the sync signal the digital data D _S read from the _Y and the memory 4. Reference numeral 11 denotes a D / A converter for converting the result of addition by the digital adder 10 into an analog signal, 12 a low-pass filter (LPF), 13 a buffer, and 14 an analog video signal output terminal.

FIG. 2 shows an example of the address control unit 4. 2, 20 is a counter that operates at a clock Nf _H, 21 are AND gates, 22 is a data selector, 23
Digital comparator 24 is a vertical memory to hold vertical control data, 25 denotes a counter which operates at a line frequency f _H, 26 is an output terminal of the read address for the memory 1, 2 and 3 in Figure 1.

The clear signal input to the counter 20 is

[0017]

[Outside 1]

The clear signal input to the counter 25 is

[0019]

[Outside 2]

## EQU1 ## Also, a signal input to the AND gate 21 together with the comparison result output signal of the digital comparator 23 is output.

[0021]

[Outside 3]

It is assumed that The three signals (external 1), (external 2) and (external 3) will be described with reference to the timing chart shown in FIG.

As shown in FIG. 3, the signal (the external 1) at the timing of the start of the video signal corresponding to one scanning line, a signal such that one period L _O clock Nf _H.

The signal (the outer 3) is a horizontal blanking period 31 ends in one scan line, at the timing when the effective video period 33 starts, a signal which becomes one period L _O clock Nf _H.

The signal (outside 2) starts one frame.
Clock f _HL for one cycle of_OTona
Signal.

Next, the operation of the address control unit 4 shown in FIG. 2 will be described with reference to the timing chart shown in FIG.

Firstly, the counter 25 is the signal the digital output at the start of the frame by (the outer 2) is reset to 0, then the clock f _H, and counts up until the next signal (outer 2) is sent Thereafter, this operation is repeated. The vertical memory 24 reads out the written vertical control data by the counter 25, and the data has the same value for the number of scanning lines constituting the vertical blanking period 32 (see FIG. 3). Set to “a”. This situation is shown in FIG.

The value of a is (horizontal blanking period 31) /
It is determined by (the period of the clock Nf _H). When the vertical control data is between the values of a, A and B of the data selector 22
Since the value a is supplied to both inputs, the output of the data selector 22 is a regardless of the output state of the digital comparator 23.

On the other hand, the counter 20 at the start of the horizontal blanking period 31, the output from the signal (external 1) is reset to 0, then when it counts up at the timing of the clock Nf _H to a value of a-1, Since the horizontal blanking period 31 ends and the signal (outside 3) becomes L _O , the data supplied to the D input is loaded. When the value of the vertical direction control data output from the vertical memory 24 is a, the counter 20 loads the value a at the timing of the signal (outside 3) and continues counting up until the next signal (outside 1) is sent. So, in the end, 0, 1, 2, ...,
The count operation of a-1, a, a + 1,..., N-1 is repeated. This situation is shown in FIG.

When the counter 25 continues counting and the vertical blanking period 32 ends, the vertical memory 24 changes the output value every moment. For example, FIG.
The operation in the case of increasing gradually as a + 1, a + 2, a + 3,... Will be described below.

First, when the vertical memory 24 outputs "a + 1", the counter 20 counts 0, 1,..., A-1 and the data selector 22 counts at the timing of the signal (outer 3).
At this time, the digital comparator 23 outputs the output value “a−1” of the counter 20 and the value “N”.
Since the comparison result Hi of "-1" is output, the data selector 22 selects the output value "a + 1" of the vertical memory 24 given to the B input and supplies it to the counter 20. Therefore, the counter 20 outputs the signal (outside). The counter 20 outputs the value “a + 1” at the timing of 3) After that, the counter 20 continues to count up, but when the count value becomes “N−1”,
The comparison output of the digital comparator 23 changes to L _O. As a result, the AND gate 21 becomes L at that timing.
_Since it becomes _O , the counter 20 enters the load state, and at the same time, the data selector 22 supplies the fixed value a set to the A input to the counter 20. Therefore, counter 2
0 loads the value a. As a result, the comparison output of the digital comparator 23 returns to Hi again. Thereafter, when the output value of the vertical memory 24 increases to a + 2, a + 3,..., The operation of the digital comparator 23 to change the output value of the counter 20 to “n” after “N−1” is repeated. This situation is shown in FIG.

In this manner, shift is performed sequentially for each scanning line.
The output data of the counting counter 20 is a horizontal address.
From the output terminal 26 to the memories 1 to 3 shown in FIG.
And memories 1 to 3 sequentially shift the luminance signal digit.
Total data D_YAnd color difference signal digital data D_BY,
D_RYIs output. On the other hand, the counter 8 outputs the clock Nf _Hof
Supply fixed horizontal address to memories 4 to 6 at timing
Therefore, the fixed synchronization signal digital data D_Sand
Color subcarrier signal digital data Dsin and Dcos are stored in memory
4 to 6 are output. Each digital data D_Y,
D_BY, D_RY, D_S, Dsin and Dcos are all the same
Check Nf_HOccurs at the timing of
And the adder 10 performs an operation represented by the following equation.

(D _BY ) × (D sin) + (D _RY ) × (D cos) + D _Y + D _S (1) The digital data obtained by such an operation is converted into an analog signal by the D / A converter 11. And low-pass filter 1
By removing unnecessary harmonic components in step 2, a smooth video signal is obtained at the output terminal 14.

When the vertical control data output from the vertical memory 24 linearly increases as described above, the memories 1 to 3
Is shifted in the advancing direction for each scanning line, the image generated by the video signal obtained from the output terminal 14 is a so-called right-diagonal image as shown in FIG. Become. Also, if the vertical control data is increased linearly and then decreased linearly, it is possible to recreate the image as shown in FIG. 5B.

[0035]

As described above, according to the present invention, a video signal is decomposed into a luminance signal, a synchronizing signal, two mutually orthogonal color difference signals and two mutually orthogonal color subcarrier signals, and these are separated into digital data. And controlling the address control unit to shift the readout timing of only three types of digital data of the luminance signal and the two color difference signals among the digital data sequentially for each scanning line. Thus, a video signal for realizing an image having an oblique component is generated. Therefore, a frame memory for storing one screen of digital data as in the related art is not required, and only a line memory for storing one scan line of digital data is required. Therefore, the size and cost of the apparatus can be reduced. Can be.

By preparing various vertical control data for controlling the timing of reading digital data of the luminance signal and the color difference signal, one image can be easily changed to an image having various oblique components. And
A video signal generating device that generates an image having a wide range of evaluation elements, which has never existed before, can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a video signal generation device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an address control unit used in the video signal generator.

FIG. 3 is a timing chart of signals for operation of the address control unit.

FIG. 4 is a timing chart for explaining the operation of the address control unit;

FIG. 5 is a diagram showing an image realized by one embodiment of the present invention.

FIG. 6 is a schematic block diagram showing a conventional video signal generator.

FIG. 7 is an explanatory diagram of an analog signal that has been D / A converted by the video signal generator.

[Explanation of symbols]

 1 Memory 2 Memory 3 Memory 4 Memory 5 Memory 6 Memory 7 Address Control Unit 8 Counter 9 Digital Multiplier 10 Adder 11 D / A Converter 12 Low-Pass Filter 13 Buffer 14 Video Signal Output Terminal 21 AND Gate 22 Data Selector 23 Digital Comparator 24 Vertical memory 26 Horizontal address output

Claims (2)

(57) [Claims] 1. A luminance signal, a color difference signal, a synchronization signal, and a color sub-carrier.
A memory for storing data obtained by A / D converting the transmission signal,
Horizontal address for reading data stored in the memory
Generating means and the horizontal address generating means for each scanning line.
Gives timing to extract data of valid image period
A vertical memory for storing vertical control data
The vertical control data is read from the vertical memory for each scanning line.
A vertical address generating means,
Based on the vertical direction control data.
The read address during the vertical blanking period.
And read during the horizontal blanking period.
Stop shifting the address, and within the effective image period
One run of reading operation by shifting the address sequentially after entering
An address control unit to be performed for each inspection line and the address control unit
Data read from the memory and the synchronization signal stored in the memory.
A video signal generating apparatus comprising a calculating means for performing a superposition calculation of a signal and a color subcarrier signal . 2. An address control section arithmetic processing means multiplies the color difference signal digital data and the color subcarrier signal digital data to obtain modulated wave digital data, and adds the two modulated wave digital data to each other. result image signal generating apparatus according to claim 1, further comprising a means for adding the luminance signal digital data and a synchronization signal digital data.