JP2959352B2 - Method of manufacturing semiconductor wafer and analysis method by SIMS - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for detecting impurities (contaminants) on the surface of a semiconductor wafer by secondary ion mass spectrometry (hereinafter referred to as S
More specifically, the present invention relates to a method for manufacturing a semiconductor wafer to be subjected to SIMS analysis.

[0002]

2. Description of the Related Art Conventionally, SIM has been used as a method for analyzing impurities on the surface of a semiconductor wafer such as a silicon single crystal wafer.
The S method is widely used. In this analysis method, a sample surface is sputtered by a primary ion beam, and secondary ions emitted from the sputter surface are subjected to mass spectrometry.In addition to being able to analyze the types and concentrations of elements on a semiconductor wafer surface, Due to the sputtering phenomenon, there is an advantage that the impurity element profile in the depth direction of the semiconductor wafer can be measured.

However, in this SIMS method, the secondary ionization rate at the outermost surface of the sample is unstable, and it takes a certain amount of time until the secondary ions released from the sample are stabilized. By the time, the surface to be analyzed had already been scraped off by sputtering and was dug inward from the surface, it was difficult to analyze the impurities on the outermost surface of the sample with good reproducibility.

As a method for solving such a problem, for example, as shown in FIG. 6, a surface of a sample wafer 61, that is, a measured surface 62 [FIG.
hemi-cal Vapor Deposition
When the polysilicon layer 63 having a predetermined thickness is deposited in the step n), a sample is prepared by depositing the polysilicon layer 63, for example, at 650 ° C. for 2 hours (FIG. 6B). There is known a method in which stable secondary ions are emitted from the outermost surface of a sample wafer 61 by increasing the time (hereinafter, referred to as a PC-SIMS method).

As another method, Japanese Patent Application No. 2-253937 is disclosed.
FIG. 7 (a) to FIG. 7 (name of invention: method for cleaning semiconductor wafer and method for analyzing surface of semiconductor wafer).
As shown in (d), mirror-polished surface (surface to be measured)
A sample wafer 71 having a surface 72
A cap wafer 81 having a mirror-polished surface 82 is prepared as a silicon wafer for coating (FIG. 7A), and the mirror-polished surface 82 is superimposed on and adhered to the surface 72 of the sample wafer 71, and these are joined by heat treatment. 7 (b)], and the upper half of the bonded wafer 91 is ground (FIG. 7 (c)) and then polished (polished) to reduce the thickness of the cap wafer 81 [FIG.
(D)] A method of irradiating a primary ion beam from the surface of the thin film Si layer 83 (hereinafter referred to as a direct bonding method) has been proposed.

In this method, similarly to the PC-SIMS method, the time required for the secondary ions to be stably released from the outermost surface of the sample wafer 71 is obtained by the thin Si layer 83. At the time when the sputtering of the sample surface by the beam is started, the emission of the secondary ions is already in a stable state.

[0007]

However, the above P
In the C-SIMS method, it takes a long time to prepare a sample in a CVD furnace, and there is a high possibility that the surface of the sample is contaminated during the growth of the CVD film. Although the contamination from the CVD furnace can be measured by depositing the polysilicon layer in two layers, there is a problem that it is difficult to measure the intrinsic impurities of the sample before charging the sample into the furnace. In addition, it is difficult to accurately analyze the inherently easily vaporizable components of the sample, since a substance having a property of vaporizing at a relatively low temperature before the polysilicon covers the surface of the sample wafer is easily vaporized. .

On the other hand, in the direct bonding method, it is necessary to make the bonding strength sufficient to prevent peeling at the bonding surface at the time of grinding or polishing. For example, at 1100 ° C. or more for about 2 hours). However, heat treatment under such harsh conditions causes the impurities on the sample surface to diffuse into the sample, making it impossible to measure the original concentration accurately.This is particularly important for elements with a high diffusion rate such as hydrogen and copper. There was a problem.

According to the present invention, a semiconductor substrate (a sample wafer) and a cap wafer having an SOI structure are joined by a low-temperature heat treatment, and the base Si layer and the SiO ₂ layer of the cap wafer are removed by etching with a chemical solution. It is an object of the present invention to solve the above-mentioned conventional problems associated with a wafer sample manufacturing process to be subjected to the SIMS method by using a wafer having a form in which only the Si layer of the SOI structure portion of the cap wafer is left as a sample.

[0010]

The method of manufacturing a semiconductor wafer according to claim 1 SUMMARY OF THE INVENTION, the semiconductor substrate subjected to HF washing
On the surface, a base Si layer, a SiO ₂ layer and a Si single crystal thin film
Of cap wafers with SOI structure
After bonding by heat treatment,
The substrate Si layer of the cap wafer at the wafer
Etch and then SiO ₂ layer
By doing so, the Si single crystal of the SOI structure
The method is characterized in that a semiconductor wafer having a Si thin film on a semiconductor substrate is obtained while leaving a thin film .

An analysis method by SIMS according to claim 2.
Is the Si of the semiconductor wafer manufactured in claim 1.
Irradiation of the primary ion beam from the surface of the single crystal thin film
It is characterized by performing quantitative analysis.

[0012] The analysis method by SIMS according to claim 3.
Represents a substrate Si layer and a Si
O ₂ Consisting of SOI structure with layers and Si single crystal thin film
Cap wafers are superimposed and brought into close contact with each other.
After bonding, the cap wafer on this bonded wafer
The base Si layer of the wafer is removed by etching with a chemical solution.
SiO ₂ By etching away the layer,
SIMS analysis leaving a single crystal Si thin film with SOI structure
A semiconductor wafer is prepared for
Irradiation of primary ion beam from the surface of Si single crystal thin film
It is characterized by performing mass spectrometry.

[0013] The analysis method by SIMS according to claim 4.
Is B (boron), F (fluorine), A
at least one of l (aluminum) and Cl (chlorine)
To seed And analyzing it.

[0014] Hereinafter, the present invention according to claim 3, Figure 1
This will be described in more detail with reference to (a) to (d). FIG. 1 shows a procedure for preparing a sample to be subjected to SIMS analysis. First, a semiconductor substrate (sample wafer) 1 and a cap wafer 11 having an SOI structure are prepared [FIG.
(A)]. In this case, the surface of the semiconductor substrate 1, that is, the surface to be measured 2 is a mirror-polished surface. Cap wafer 11
Is a 1 μm thick SiO ₂ layer 13 on a base Si layer 12.
And a thin Si layer 14 overlaid on the SiO ₂ layer, and the surface of the thin Si layer 14 is mirror-polished. As a method for manufacturing such a cap wafer 11, a method similar to the method described in Example 2 of Japanese Patent Application No. 2-253937, that is, a silicon wafer having a thermal oxide film formed on one surface, A method may be adopted in which a silicon wafer having no thermal oxide film is bonded, the bonding strength is increased by heat-treating the bonded wafer, and then one of the Si layers sandwiching the thermal oxide film is thinned by grinding and polishing.

[0015] Then, the surface 2 of these semiconductor substrate 1,
After the thin film Si layer 14 of the cap wafer 11 is quickly overlapped and adhered to prevent contamination from the outside air, heat treatment is performed in a nitrogen atmosphere, for example, at 350 ° C. for 2 hours to bond the sample wafer 1 and the cap wafer 11. Then, a bonding wafer 21 having a structure in which the front surface 2 of the semiconductor substrate 1 is covered with the cap wafer 11 is obtained (FIG. 1B).

If necessary, a suitable sealant (silicone sealant wax or the like) is applied to the outer peripheral portion of the bonding surface of the bonding wafer 21.
After applying and sealing the joint surface (not shown),
For example, the entire substrate Si layer 12 of the cap wafer 11 of the bonding wafer 21 is removed by etching with a mixed solution of hydrofluoric acid, nitric acid and acetic acid (3: 5: 3) [FIG.
(C)]. In this case, since the etching rate of the SiO ₂ layer 13 is small, the etching stop is automatically performed when the etching removal of the Si layer 12 is completed. Then SiO ₂ layer 1
3 is etched with dilute hydrofluoric acid or the like (FIG. 1D).

[0017] Thus, the semiconductor substrate (sample wafer)
A semiconductor wafer 31 having a structure in which the thin film Si layer 14 is formed on the surface 2 of the semiconductor wafer 1 is obtained. Using the semiconductor wafer 31 thus manufactured as a sample, SIMS
Perform analysis.

[0018]

The method for manufacturing a semiconductor wafer according to claim 1 is provided.
According to this, a semiconductor wafer suitable for a sample for SIMS analysis was prepared.
Can be manufactured. That is, unlike the conventional direct bonding method, the cap wafer covering the semiconductor substrate surface is not removed by grinding and polishing, but is etched with a chemical solution, so that the bonding strength of the bonding wafer may not be so large, Therefore, high-temperature heat treatment is not required in the process of manufacturing the bonded wafer, and bonding can be performed by low-temperature processing. For this reason, it is possible to prevent impurities on the surface of the semiconductor substrate from diffusing inside in the process of manufacturing the bonded wafer. Moreover, the cap wafer is composed of the base Si layer and the Si wafer.
Since it has an O ₂ layer and a Si single crystal thin film, the etch rate
With the completion of etching and removal of the Si
Since the stop is applied and the etching of the SiO ₂ layer having a small etch rate does not substantially proceed, the management of the etching time is simplified, and the thickness of the layer to be bonded to the semiconductor substrate of the cap wafer is set in advance. By that
The thickness of the thin film on the semiconductor substrate in the semiconductor wafer can be set to a desired value.

[0019] The analysis method by SIMS according to claim 2.
A semiconductor wafer manufactured by the method according to claim 1.
Irradiation of primary ion beam from Si single crystal thin film surface
To perform mass spectrometry, making the sample suitable for SIMS analysis.
SIMS analysis is possible by using a semiconductor substrate (sample wafer).
-Ha) Analysis of surface impurities can be performed more accurately.
Wear.

An analysis method by SIMS according to claim 3.
So unlike conventional direct lamination method, not to be removed by grinding and polishing the cap wafer having an SOI structure which covers the semiconductor substrate surface, since the etching with a chemical solution, a high temperature heat treatment in the manufacturing process of the bonded wafer Is unnecessary and can be joined by low-temperature processing. For this reason, it is possible to prevent impurities on the surface of the semiconductor substrate from diffusing inside in the process of manufacturing the bonded wafer. Moreover,
Etch stop is automatically performed at the same time as the etching removal of the base Si layer on the cap wafer,
_Since the etching of the _two layers is not performed, the management of the etching time is simplified, and the SOI of the cap wafer is previously determined.
By setting the thickness of the Si layer (corresponding to the portion indicated by reference numeral 14 in FIG. 1) of the structure, the thickness of the thin film Si layer on the semiconductor wafer can be set to a desired value.
Further, unlike the conventional PC-SIMS method, it is possible to quickly cap the semiconductor substrate by bonding.
Further, since the heat treatment is performed while the surface of the semiconductor substrate is capped, vaporization of a substance which is easily vaporized at a relatively low temperature can be prevented. And, according to the third aspect,
According to the analysis method by SIMS, the half produced by the above method is used.
Primary ion beam from the surface of the Si single crystal thin film layer on the conductor wafer
Irradiates the mass spectrometer to perform mass spectrometry, making it suitable for SIMS analysis.
SIMS analysis is possible with the sample
(Sample wafer) More accurate surface impurity analysis
Can be.

[0021]

Next, examples of the present invention will be described in comparison with the conventional method. Example 1 A plurality of semiconductor wafers (sample wafers) and a plurality of cap wafers having an SOI structure, each of which has been subjected to processing up to single-sided mirror polishing in a normal processing step, were prepared, and these wafers were washed under the following conditions. A semiconductor wafer was prepared as a sample by the procedure shown in FIG. 1, and what kind of impurity light element remained on the cleaning surface of the wafer was measured. (1) HF cleaning: concentration is 5% by weight, temperature is normal temperature. (2) SC1 cleaning: composition is NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 6, temperature is 80 ° C. (3 ) SC2 cleaning: composition: HCl: H ₂ O ₂ : H ₂ O = 1: 1: 6, temperature: 80 ° C.

An N-type silicon wafer is used as the semiconductor substrate (sample wafer) and the cap wafer.
Lamination for bonding wafer preparation is about 1 after washing is completed.
Performed within a class 1000 clean room within minutes.
The heat treatment for bonding is performed at 600 ° C. for 2 hours in an N ₂ atmosphere in any of the cleaning products, and the cap wafer in the bonding wafer is etched to form a film on the surface of the semiconductor substrate (sample wafer). 1.5
A μm thin-film Si layer was provided.

[0023] on the surface of Comparative Example 1 (PC-SIMS method) semiconductor substrate after the cleaning (sample wafer),
According to the process of FIG. 6, a polysilicon layer having a thickness of 1.5 μm was provided by CVD at 650 ° C. for 2 hours.

[0024] The standard in went SIMS measurement conditions are shown in Table 1. Also, RSF (Relative Sen)
calculation formula (PM.
kahora and F.K. A. Stevei, in
SIMS VII, pp. 143) was converted to the surface concentration. The conversion formula is shown in [Equation 1].

[0025]

[Table 1]

[0026]

(Equation 1)

The RSF: conversion factor by volume concentration (atoms / ^cm 3) D: Measurement Depth (cm) ΣIi: impurity ions total count Ib: impurity background (CPS) C: Measurement Cycle Im: intensity of matrix elements (CPS)

FIG . 2 shows a SIMS chart according to the first embodiment, and FIG. 3 shows a SIMS chart according to the first comparative example. As is clear from comparison of these, Example 1
As a result, a chart having a sharper peak than that of Comparative Example 1 was obtained. The sharp peak means that the SN ratio is good, and the detection sensitivity is extremely high. Such a sharp peak is considered to be because the roughness of the crater bottom is suppressed because the Si layer covering the surface of the semiconductor substrate (sample wafer) is not polysilicon but single crystal.

[0029] The analysis results of Example 1 shown in FIG. Although an oxide film is formed at the joint between the mirror-polished surface of the semiconductor substrate (sample wafer) and the mirror-polished surface of the cap wafer, B is detected from the joint of the SC1 and SC2 cleaning bonded wafers. B was not detected from the HF cleaning sample having no oxide film. The contact time with the atmosphere in the clean room is determined by the HF cleaning sample, SC1 and S
Since B is the same as that of the C2 cleaning sample, B is S
It is considered that it does not easily adhere to the i surface. A large amount of F was detected from the HF washed sample and the SC1 washed sample. Al
Was detected only from the SC1 washed sample, and other analyzes (VPD
-AAS) method. Cl was detected from the SC2 cleaning sample, probably because Cl from HCl was mixed into the oxide film.

The same semiconductor substrate (sample wafer) as used in Example 1 and the cap wafer to a plurality prepared, allowed to stand in a clean room after a chemical cleaning for the former, chemical cleaning for the latter Was done. Using these wafers, a semiconductor wafer shown in FIG. 1D was manufactured by the procedure shown in FIG. 1, and boron (B) contamination due to standing in a clean room was evaluated.

[0031] That is, the semiconductor SC1 cleaning for the substrate (sample wafer), SC2 cleaning, SC1 cleaning (the composition of the chemical solution as in Example 1 the same) and cleaning process in order,
After drying, it was left in a class 1000 clean room for various times. The cap wafers were subjected to HF cleaning (the composition and the like were the same as in Example 1), and semiconductor wafers were prepared from these wafers according to the procedure shown in FIG.

[0032] Since the lamination was carried out immediately after the end HF cleaning of the cap wafer, the thickness of the cap wafer surface oxide film at the bonding wafer is considered almost constant. Heat treatment for bonding in an _{N 2} atmosphere by RTA furnace was carried out under the conditions of 600 ° C. · 2 hours. Then, a 1.5 μm-thick thin-film Si layer was provided on the surface of the semiconductor substrate (sample wafer) by etching the cap wafer portion of the bonding wafer.

FIG . 5 shows the relationship between the time of leaving the semiconductor substrate in the clean room and the boron concentration at the bonding interface of the bonding wafer. From this figure, it was confirmed that the boron concentration increased as the standing time increased, and there was contamination from the clean room atmosphere. Further, even in the case of leaving for a short time of 25 seconds, a considerably large amount of boron was detected, that is, 4 × 10 ¹⁰ atoms / cm ² . From this, it is considered that when measuring the surface boron of 4 × 10 ¹⁰ atoms / cm ² or less even in the analysis method according to the present invention, it is necessary to bond the wafers in an environment in which measures against boron contamination are taken. .

When the surface boron is measured by the PC-SIMS method, usually, boron of 1 × 10 ¹² atoms / cm ² or more is often detected. In addition, since it is currently the case that the time required for the sample wafer to be exposed to the clean room atmosphere during the measurement takes 5 minutes or more, the boron concentration that can be measured by the PC-SIMS method is approximately the shaded region in FIG.

[0035] Thus, for a high concentration of boron contamination during the fabrication process of the polysilicon deposition wafer occurs in PC-SIMS method, the measurement of the sample wafer original low concentration surface boron before depositing the polysilicon layer Impossible. On the other hand, in the present invention, as described above, the detection limit of surface boron can be significantly reduced as compared with the PC-SIMS method, and light elements such as C, Cl, and F can be measured. Further, the same result as described above was obtained even when a sample was prepared by setting the heat treatment conditions for bonding at 350 ° C. for 2 hours.

[0036]

As is apparent from the above description, the present invention
Then, the following excellent effects can be obtained. (1) Invention according to claim 1: (a) a semiconductor wafer suitable for a sample for SIMS analysis
C can be manufactured. The (b) the required bonding strength of the bonded wafer, it is possible to reduce considerably in comparison with the case of direct lamination method, a high temperature heat treatment in the manufacturing process is not necessary, since it is sufficient bonding by the low temperature process In addition, it is possible to prevent impurities on the surface of the semiconductor substrate from diffusing inside in the process of manufacturing the bonded wafer. Therefore, highly sensitive analysis can be performed, and analysis of hydrogen that easily diffuses is also possible. (C) pasting Therefore to cap the fast semiconductor substrate by alignment, it is possible to prevent contamination of the semiconductor substrate surface, it is possible to accurate analysis. (D) Since the heat treatment is performed with the semiconductor substrate surface capped, vaporization of a substance which is easily vaporized at a relatively low temperature can be prevented, so that accurate analysis is possible. (2) Invention according to claim 2: (a) Unlike the PC-SIMS method, SIMS according to claim 2
In the analysis method according to the above, since the Si layer covering the surface of the semiconductor substrate is a single crystal, the S layer having a sharp and high SN ratio peak is used.
Since an IMS chart is obtained, the detection limit of elements such as boron can be significantly reduced. (B) Unlike the PC-SIMS method, diffusion of impurities on the surface of the semiconductor substrate is extremely small, and contamination during the semiconductor wafer manufacturing process is extremely small. Therefore, the analysis on the measurement surface becomes accurate. (3) The invention according to claim 3 : A sample for SIMS analysis, similar to the invention according to claim 1.
To produce a suitable semiconductor wafer.
In addition, the same excellent effects as those of the second aspect can be obtained. (4) The invention according to claim 4: The method according to claim 3 reduces the amount of B, F, Al, Cl
Since at least one type of analysis is performed,
More accurate analysis of these impurities present
it can.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a sample manufacturing process according to the present invention, which is shown in a cross-sectional view of a wafer.

FIG. 2 is a SIMS chart according to the first embodiment of the present invention.

FIG. 3 SIMS by Comparative Example 1 (PC-SIMS method)
It is a chart of.

FIG. 4 is a graph showing analysis results of various elements according to Example 1.

FIG. 5 is a graph showing the results of analyzing boron according to Example 2.

FIG. 6 is an explanatory diagram of a sample manufacturing step by a PC-SIMS method, which is shown in a cross-sectional view of a wafer.

FIG. 7 is an explanatory view of a sample preparation process by a conventional direct bonding method, which is shown in a cross-sectional view of a wafer.

[Explanation of symbols]

1,61,71 Semiconductor substrate (sample wafer) 2,62,72 Surface (measured surface) 11,81 Cap wafer 12 Base Si layer 13 SiO ₂ layer 14,83 Thin film Si layer 21,91 Bonding wafer 31 Semiconductor wafer 63 Polysilicon layer 82 Mirror-polished surface

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takuo Takenaka 2-3-1-1, Isobe, Annaka-shi, Gunma Shin-Etsu Semiconductor Co., Ltd. Inside the semiconductor isobe research laboratory (56) References JP-A-2-1914 (JP, A) JP-A-4-132222 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/12 H01L 21/02 H01L 21/66 H01L 21/306 G01N 23/22

Claims (4)

(57) [Claims] 1. The method according to claim 1 , wherein the surface of the semiconductor substrate subjected to the HF cleaning is
S having base Si layer, SiO ₂ layer and Si single crystal thin film
Overlaid and adhered cap wafers with OI structure
After bonding by heat treatment, this bonded wafer
The substrate Si layer of the cap wafer with a chemical solution
And then etching away the SiO ₂ layer
As a result, a single-crystal Si thin film having an SOI structure is left on the bonding surface.
And obtaining a semiconductor wafer having a Si thin film on a semiconductor substrate . 2. The semiconductor wafer manufactured in claim 1.
A primary ion beam from the surface of the Si single crystal thin film
SIMS, characterized by irradiating and performing mass spectrometry
Analysis method. 3. A substrate S on a surface of a semiconductor substrate to be analyzed.
SOI structure having i layer, SiO ₂ layer and Si single crystal thin film
Laminated cap wafers are attached to each other,
After bonding by heat treatment, the bonding wafer
Etching removal of base wafer Si layer of cap wafer with chemical solution
And then etching away the SiO ₂ layer.
Leaving a single-crystal Si thin film of the SOI structure on the bonding surface
Prepare a semiconductor wafer for SIMS analysis
Primary ion beam from the surface of Si single crystal thin film
SIMS characterized by performing mass spectrometry by irradiating a system
Analysis method. 4. The analysis by SIMS comprises : B, F, A
characterized in that it is performed for at least one of l and Cl
The analysis method by SIMS according to claim 3.