JP2959619B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a multilayer wiring.

[0002]

2. Description of the Related Art Conventionally, high integration and high speed of semiconductor devices have been achieved by miniaturization and multi-layer wiring, but this trend is expected to continue in the future. In the conventional multilayer wiring, as shown in FIG. 5, when the lower wiring 51 and the upper wiring 53 are connected via the connection port 52, the connection port 5
An overlapping margin is provided so that 2 does not protrude from the lower wiring 51.

[0003] In order to increase the packing density, it is necessary to reduce the wiring pitch, but to reduce the wiring pitch, it is necessary to reduce not only the wiring width and the wiring interval but also the area of the connection port. . However, reducing the size of the connection port is limited due to reasons such as difficulty in processing the connection port and an increase in connection resistance.Therefore, it is necessary to reduce the overlap margin between the wiring layer and the connection port. Since the submicron device and thereafter, the overlap margin is 0.1 μm or less, and further approaches the state of the margin 0 shown in FIG. 6 without limit.

[0004] On the other hand, although the accuracy of the superposition of the wiring layer and the connection port has been improved, at present it is 0.1%.
It is difficult to keep the thickness below μm. In particular, when the chip size is increased due to high integration, it is extremely difficult to maintain high overlay accuracy over the entire surface of the chip because the exposure apparatus has lens distortion (distortion) and the like. In other words, rather than the overlay accuracy,
The overlap margin becomes smaller, and the connection port 52 protrudes from the lower wiring 51 as shown in FIG.

A conventional method for forming a multilayer wiring in the case where the connection port protrudes from the lower wiring will be described below with reference to the drawings. 8A to 8E are process sectional views showing main process steps of the related art. First, C is placed on a silicon substrate 41 on which semiconductor elements such as transistors are formed.
BPSG (Boro-Phospho-Silicate Glass:
A boron (phosphorus glass) film 42 is formed, and a first Al wiring 43 is formed thereon using an AlCu alloy obtained by adding 0.5% of copper to Al (FIG. 8A).

Next, chemical vapor deposition using plasma (P
Silicon oxide is grown by an E-CVD method, and a plasma oxide film 44 is formed as an interlayer insulating film. The surface is flattened by applying spin-on-glass (SOG) on the plasma oxide film 44, etching back after forming a photoresist film, or polishing by a chemical mechanical polishing (CMP) method. [Fig. 8
(B)]. Next, a photoresist film 45 is coated on the plasma oxide film 44, and the pattern of the connection port is exposed using an exposure machine such as a stepper, and then developed to form an opening at a predetermined position of the photoresist film 45. [FIG. 8 (c)].

Next, the plasma oxide film 44 is etched by dry etching using the photoresist film 45 as a mask until it reaches the first Al wiring 43 (FIG. 8).
(D)]. Conventionally, in this type of dry etching method, the etching speed of the connection ports having different sizes has been made as equal as possible, and the condition has been used in which the microloading effect in which the etching rate becomes smaller as the connection port becomes smaller is suppressed.

A method for suppressing such a microloading effect is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-283374.
As shown in JP, C _n F and a method of etching by fluorocarbon compound and oxygen is represented by _m, CHF ₃ and -60 ° C. ~ 18 ° C. The substrate using Ar gas
Etching at a low temperature (this method is described in Japanese Journal of Applied Physics, Vol. 31, 1992, Part 1, 4370-4)
375 pages (Jpn. J. Appl. Phys. Vol. 31 (1992) Part 1)
pp.4370-4375) “Suppression of microloading Effeft by Rot'em PERTURE S
io ₂ etching ”(Suppression of Microloading Eff
ect by Low-Temperature SiO ₂ Etching). ) Etc. have been proposed.

According to this method, Al having a wiring width of 0.4 μm is formed.
Assuming that 0.3 μm × 0.3 μm connection ports are formed on the wiring, the overlap margin is only 0.05 μm on one side, and all the connection ports on the wafer are 0.05 μm or less in the current mass production technology. It is impossible to overlap with the Al wiring due to the displacement, and the connection port is 0.05 to
Some portions protrude by about 0.1 μm.

Further, since the etching of the connection port has a difference or variation in the thickness of the interlayer insulating film or a variation in the etching rate, the deepest connection is required to ensure that the connection port reaches the Al wiring. Generally, etching is performed for 1.5 to 2 times the etching time at which the etching of the mouth is considered to be completed.

For example, the deepest connection port has a depth of 1.0 μm.
m, a silicon oxide film having a thickness of about 1.5 to 2.0 μm is etched. At this time, the connection port is
In the portion protruding from the Al wiring 43, the plasma oxide film 44 on the side wall of the first Al wiring is also etched (FIG. 8D).

Thereafter, the photoresist film 45 is removed,
After the AlCu alloy film is formed again by the sputtering method, the second Al wiring 46 is formed by patterning the AlCu alloy film into a desired shape by ordinary lithography and dry etching techniques, and the formation of the Al2 layer wiring is completed [FIG.
(E)].

[0013]

In this conventional method of manufacturing a semiconductor device, the miniaturization of a semiconductor element may cause a point where the connection port protrudes from the lower layer wiring because the overlay accuracy in photolithography cannot keep up. . However, since the etching of the connection port is performed under the condition that the etching rate does not depend on the size of the connection port, that is, under the condition that the microloading effect is small, 50 to 100%
When the over-etching is performed, the interlayer insulating film on the side surface of the lower wiring is also etched.

If the interlayer insulating film is etched to the side of the lower wiring, as shown in FIG. 8E, when the Al alloy is formed as the upper wiring by the sputtering method, the coverage of the Al alloy film deteriorates. And the connection resistance rises,
Electromigration resistance and stress migration resistance are deteriorated, and reliability is reduced. If the amount of over-etching is further increased, as shown in FIG. 9, the insulating film below the lower wiring is also etched, and the lower silicon substrate is exposed, which causes a problem of short-circuiting with the upper wiring. This problem is remarkable in the case of connecting ports having different depths, since the etching is performed in accordance with the deepest connecting port. If a margin for overlapping the lower wiring and the connection port is increased to prevent these problems, the size of the semiconductor device is increased, and it is difficult to achieve high integration.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a method in which a lower layer wiring is formed even if a connection port protrudes from a lower layer wiring due to a lack of overlay accuracy in photolithography technology. Is intended to prevent the etching of the insulating film on the side surface of the semiconductor device, thereby making it possible to form a highly reliable multilayer wiring even if the margin of the lower wiring with respect to the connection port is reduced. .

[0016]

According to the present invention, in order to achieve the above object, a connection port reaching the lower wiring is formed at a desired position of an interlayer insulating film on a lower wiring by a dry etching method. In the method of manufacturing a semiconductor device, the dry etching is performed under a condition that the etching rate of the interlayer insulating film is sufficiently higher than the etching rate of the lower wiring, and at least in the final stage of the connection port forming step. Is 0.1 μm × 0.1
A method of manufacturing a semiconductor device, characterized in that etching is performed under a condition that an etching rate of dry etching of a size of μm or less is one third or less of an etching rate of a minimum size of the connection port.

Preferably, the etching is performed under the condition that the etching rate difference due to the size of the connection port is small to a depth that does not exceed the minimum thickness of the interlayer insulating film on the lower wiring, and thereafter, the etching rate difference is large. Etching is performed. Such a difference in etching rate is caused by changing the ratio of fluorine to carbon in the etching gas.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 1A to 1E show a first embodiment of the present invention.
FIG. 7 is a process order sectional view showing main process steps of the example in order. First, a first wiring having a wiring width of 0.3 μm is formed by a polycrystalline silicon film 13 having a thickness of about 0.3 μm on a silicon substrate 11 covered with a silicon oxide film 12. After forming a BPSG film 14 having a thickness of about 1.0 μm to cover it, a reflow heat treatment is performed in a nitrogen atmosphere to flatten the surface [FIG. 1 (a)].

Next, a photoresist film 15 is applied,
Reduction projection exposure machine using rF excimer laser (Kr
After exposure by an F stepper, the photoresist film 15 is developed to form an opening of 0.3 μm × 0.3 μm at a predetermined position of the photoresist film 15. At this time, it is difficult to overlap the openings of the photoresist film 15 on all the polycrystalline silicon films 13 over the entire surface of the silicon substrate 1 (wafer).
There is a possibility that a portion shifted by about 0.1 μm may occur (FIG. 1B).

Next, the BPSG film 14 is etched using the photoresist film 15 as a mask. Etching is magnetron reactive ion etching (MRIE)
Using an apparatus, a mixed gas of CHF ₃ and CO is used as an etching gas, under the conditions of pressure: 40 to 70 mTorr, RF power: 600 W, substrate temperature: 70 to 120 ° C., more preferably 90 to 110 ° C.

FIG. 2 shows the change in the etching rate when the flow rate ratio between CHF ₃ and CO is changed under these conditions. As shown in the figure, when CHF ₃ is small, 0.1 μm ×
At the opening of 0.1 μm, the amount of F radicals required for etching is small and the carbon-based film is formed more than the etching.
The etching rate is high at the opening of 0.5 μm. On the other hand, when the amount of CHF ₃ increases, radicals penetrate into small openings as much as necessary for etching.
The difference between the etching rates of the openings of m × 0.1 μm and 0.5 μm × 0.5 μm becomes small.

[0022] Therefore, first CHF _3: CO = 4: etched until just before the polycrystalline silicon film 13 is exposed by one of the gas ratio [FIG. 1 (c)], followed by, CHF _3: CO
Etching is performed for an etching time of about 0.5 μm in a 0.3 μm × 0.3 μm opening at a gas ratio of = 1: 3. At this time, since the portion shifted from the polycrystalline silicon film 3 is 0.1 μm or less, the side of the polycrystalline silicon film 13 is etched only to 0.1 μm or less [FIG.
(D)].

CHF ₃ from the beginning of etching : CO =
The etching may be performed under the condition of 1: 3, but under this condition, it takes too much time at the opening of 0.3 μm × 0.3 μm because the etching rate is low, which is not preferable.
CH when the opening is larger than 0.4 μm × 0.4 μm
Since a relatively high etching rate can be obtained even under the condition of F ₃ : CO = 1: 3, it is better to perform etching under this condition from the beginning. Usually, the etching of the opening is 50-100.
%, But even if the BPSG film 14 of about 1.0 μm is 100% over-etched, the etching rate of a size of 0.1 μm or less is 0.3%.
If the etching rate at the opening of μm × 0.3 μm is one third or less, only the part shifted from the polycrystalline silicon film 13 is etched at most 0.33 μm. There is no such thing that the surface of is exposed.

A size of 0.1 μm or less and 0.3 μm ×
The larger the difference between the etching rates of 0.3 μm, the smaller the amount of etching beside the polycrystalline silicon film 13, so that good results can be obtained.
When the etching rate for the submicron size is reduced,
The etching rate at the opening of 0.3 μm × 0.3 μm is also reduced, and a practical etching rate cannot be obtained. Therefore, etching at a size of 0.3 μm × 0.3 μm must be performed at a practical etching rate, and the difference between the two etching rates must be reduced to some extent. The effect of the present invention can be obtained by suppressing the etching rate of the size to one third or less of the etching rate at the opening of 0.3 μm × 0.3 μm.

Next, the photoresist film 15 is removed, and T for reducing the contact resistance with the polysilicon film 13 is removed.
Ti for preventing interdiffusion between silicon film and Al with i film
After providing the barrier metal layer 16 made of an N film, a second wiring is formed by the Al alloy film 17 (FIG. 1E).
During the formation, the Al alloy film 17 may be heated to about 450 to 500 ° C. and fluidized to fill the connection port. Further, the barrier metal layer does not necessarily have to be provided. Or,
The Al alloy film 17 may be formed after W or the like is selectively grown by a chemical vapor deposition (CVD) method to bury the connection port.

[Second Embodiment] FIGS. 3 (a) to 3 (d)
FIG. 9 is a sectional view illustrating the main process steps of a second embodiment of the present invention in order. After a first wiring is formed with a polycrystalline silicon film 23 on a silicon substrate 21 covered with a silicon oxide film 22 and a first interlayer insulating film is formed with a BPSG film 24, a film having a thickness of about 0.4 μm is formed. A second wiring having a wiring width of about 0.3 μm is formed with the Al alloy film 25. Al alloy film 25
Have different heights on the first wiring and in other regions. Thereafter, a plasma oxide film 26 serving as a second interlayer insulating film is formed by PE-CVD and is completely planarized (FIG. 3A).

As a method of flattening the plasma oxide film 26, a high-frequency bias is applied to the silicon substrate 21 by a PE-CVD method using high-density plasma.
After forming as thick as about μm, a method of polishing the silicon oxide film by about 1.0 μm by a CMP method can be used. The formed plasma oxide film 26 has a thickness of about 1.0 μm where the first wiring and the second wiring overlap, and has a thickness of about 1.3 to 1.4 μm where the first wiring and the second wiring overlap.

Next, after applying a photoresist film 27, it is exposed and developed by a KrF stepper to form an opening of 0.3 μm × 0.3 μm at a predetermined position. At this time, it is difficult to completely overlap the opening with the second wiring, and the opening may be shifted by about 0.1 μm (FIG. 3B).

Next, using the photoresist film 27 as a mask, the difference in the etching rate due to the size of the opening is small and the etching rate is large until the second wiring overlapping the first wiring with the silicon oxide film 26 is exposed. Etching is performed under dry etching conditions (FIG. 3C). The dry etching conditions include, for example, CHF ₃ and C ₂
The mixing ratio of F ₆ is 1: 1 and the etching gas pressure is 10
It is possible to use a reactive ion etching method under the conditions of 0 to 200 mTorr and high frequency power: 900 W.

Next, the mixing ratio of CHF ₃ and C ₂ F ₆ is set to 2:
1, pressure: 100 to 300 mTorr, high frequency power: 900 W, substrate temperature: 60 to 100 ° C.
Etching is performed until a second wiring which does not overlap with the first wiring is exposed. Under this condition, since the etching is almost performed at a size of 0.1 μm or less, the side of the second wiring overlapping with the first wiring is not dug deeply [FIG.
(D)].

Thereafter, the photoresist film 27 is removed,
As in the case of the first embodiment, the connection port is formed so as to be embedded with an Al alloy film, or after being embedded with W, an Al alloy film is formed, and the Al alloy film is patterned into a desired shape. Third wiring (not shown) is formed.

[Third Embodiment] FIGS. 4 (a) to 4 (d)
FIG. 9 is a sectional view sequentially illustrating main process steps of a third embodiment of the present invention. A first wiring is formed by a first Al alloy film 33 on a silicon substrate 31 covered with a silicon oxide film 32. A first plasma oxide film 34 serving as an interlayer insulating film is formed thereon by a PE-CVD method, a second wiring is formed thereon by a second Al alloy film 35, and a second wiring is further formed thereon. Is formed, and the surface is flattened by a CMP method or the like (FIG. 4A).

Next, a photoresist film 37 is applied,
Exposure is performed using an rF stepper, and development is performed to form an opening at a predetermined position. Here, it is difficult to completely overlap the opening with the lower wiring, and there is a possibility that the opening is shifted by about 0.1 μm (FIG. 4B). In the case of the present embodiment, even if the opening can be completely overlapped with the second wiring, if the first wiring and the second wiring are slightly displaced, the connection port will be the first wiring. It will be off. And vice versa. Next, using the photoresist film 37 as a mask, the second plasma oxide film 36 is formed on the second Al alloy film 35.
Until is exposed, etching is performed under dry etching conditions in which the difference in etching rate due to the size of the opening is small and the etching rate is large [FIG. 4 (c)].

Thereafter, the etching is performed until the surface of the first Al alloy film 33 is exposed under the condition that the etching is hardly performed at a size of 0.1 μm or less. At this time, the second Al
The gap between the opening and the second wiring is 0.1 mm beside the alloy film 25.
Since it is less than μm, it is hardly etched [FIG. 4 (d)]. The etching conditions for the first and second steps may be the same as those in the above-described first or second embodiment. Thereafter, the photoresist film 37 is removed, the connection port is buried with a metal such as W, and a third wiring (not shown) is formed thereon with an Al alloy film.

According to the second and third embodiments, according to the present invention, even when the connection ports having different depths are formed, even if the alignment between the lower wiring and the connection port is slightly shifted, the present invention provides a good shape and good connection. It was confirmed that electrical characteristics could be obtained.

[0036]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the etching rate of 0.1 μm or less is set at least in the final stage of the process of opening the connection port between the wirings. Since the etching is performed under one-third or less of the etching rate of the minimum size, the interlayer insulating film beside the lower wiring should be hardly etched even if the alignment between the lower wiring and the connection port is slightly shifted. And a metal film can be formed in the connection port with good coverage. Thus, according to the present invention,
The connection between the upper wiring and the lower wiring can be performed stably and reliably, and the stable connection between the layers enables
Electromigration resistance, stress migration resistance, and the like are also improved, and reliability can be improved. Furthermore, according to the method of the present invention, even when forming connection ports having different depths, for the same reason as described above, it is possible to form a stable connection even when the lower layer wiring and the connection port are slightly misaligned. It is possible.

Therefore, according to the present invention, it is not necessary to increase the margin for overlapping the lower wiring and the connection port, and the wiring density can be improved, which contributes to high integration and high density of the semiconductor device. be able to.

[Brief description of the drawings]

FIG. 1 is a process order sectional view showing main process steps of a first embodiment of the present invention.

FIG. 2 is a graph showing a relationship between a mixing ratio of an etching gas and an etching rate.

FIG. 3 is a process order sectional view showing main process steps of a second embodiment of the present invention.

FIG. 4 is a process sectional view showing main process steps of a third embodiment of the present invention.

FIG. 5 is a plan view of a conventional multilayer wiring structure.

FIG. 6 is a plan view of a multilayer wiring when a margin between a lower wiring and a connection port is 0.

FIG. 7 is a plan view when a connection port is displaced from a lower wiring.

FIG. 8 is a process order sectional view showing main process steps of a conventional example.

FIG. 9 is a cross-sectional view for explaining a problem of the conventional example.

[Explanation of symbols]

 Reference Signs List 11 silicon substrate 12 silicon oxide film 13 polycrystalline silicon film 14 BPSG film 15 photoresist film 16 barrier metal layer 17 Al alloy film 21 silicon substrate 22 silicon oxide film 23 polycrystalline silicon film 24 BPSG film 25 Al alloy film 26 plasma oxide film 27 Photoresist film 31 Silicon substrate 32 Silicon oxide film 33 First Al alloy film 34 First plasma oxide film 35 Second Al alloy film 36 Second plasma oxide film 37 Photoresist film 41 Silicon substrate 42 BPSG film 43 First Al wiring 44 Plasma oxide film 45 Photoresist film 46 Second Al wiring 51 Lower wiring 52 Connection port 53 Upper wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (6)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: forming a connection port reaching a lower layer wiring at a desired position of an interlayer insulating film on a lower layer wiring by a dry etching method. The etching is performed under the condition that the etching rate of the interlayer insulating film is sufficiently higher than the etching rate, and at least in the final stage of the connection port forming step, 0.1 μm × 0.1 μm
The etching rate of dry etching of the following sizes is
A method of manufacturing a semiconductor device, characterized in that etching is performed under a condition that is equal to or less than one third of an etching rate of a minimum size of the connection port. 2. The method according to claim 1 , wherein the step of forming the connection port comprises the steps of:
It is performed in two stages, the final stage, and
The minimum thickness of the interlayer insulating film on the lower wiring is exceeded.
Etching to an inevitable depth
It is characterized by performing subsequent etching in the process
The method for manufacturing a semiconductor device according to claim 1. 3. The semiconductor according to claim 1, wherein etching is performed under a condition that an etching rate difference depending on a size of a connection port is small to a depth not exceeding a minimum thickness of the interlayer insulating film on the lower wiring. Device manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 3 , wherein a difference in etching rate depending on the size of the region to be etched is changed by changing a ratio of fluorine to carbon in the etching gas. By wherein varying the CHF ₃ gas mixing ratio of CO, a method of manufacturing a semiconductor device according to claim 4, wherein the changing the etching speed difference due to the size of the etched region. By wherein changing the gas mixing ratio of CHF ₃ and C ₂ F _6, claim 3, characterized in that to vary the etching rate difference due to size of the etched region
The manufacturing method of the semiconductor device described in the above.