JP2960144B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device.

2. Description of the Related Art In recent years, the density of semiconductor memory devices has been increasing, and in particular, the integration and density of dynamic random access memories (DRAMs) have been remarkable. Although the memory cell area and the memory cell capacity have been reduced due to such high integration and high density, accurate and high-speed reading of information of the small memory cell capacity has been required. FIG. 2 is an example of a memory cell array of a conventional semiconductor memory device. SA1 to SA4 are sense amplifiers, ROWDEC is a row coder, WL1 to WL16 are word lines, BL1 to BL8 are bit lines, Q21 to Q28 are N-channel MOS transistors, ○ marks at the intersections of word lines and bit lines are memory cells And VCC are power supply voltages. Regarding the operation, for example, when the word line WL3 is selected, the information of the memory cell is read to the bit lines BL2, BL3, BL6, BL7, and the bit lines BL1 and BL3, BL2 and BL4, BL5 and BL7, BL6 And BL8
The small potential difference that occurs in the sense amplifiers SA1 and SA
2, amplified by SA3 and SA4 and output as data. This memory cell array has a configuration in which one sense amplifier is connected to a pair of bit lines having a constant capacitance and resistance per unit length.

As described above, in a conventional semiconductor memory device of a memory cell array, a pair of bit lines having a constant capacitance and a constant resistance per unit length are connected to one sense amplifier.
The time required to amplify the bit line pair to the logical voltages “H” and “L” by operating the sense amplifier on the minute potential difference read out to the pair of bit lines depends on the capacitance and resistance of the bit line. Is determined by the resistance between the source and drain of the transistor that constitutes the sense amplifier when the transistor is on. The smaller the capacitance and resistance, the higher the speed. However, the resistance of the bit line is usually between the source and drain when the transistor is on. The effect is small because it is smaller than the resistance. Here, the large capacity of the bit line is a major obstacle to the high-speed operation of the sense amplifier. Also, it is difficult to reduce the capacity of the bit line from the viewpoint of manufacturing or the layout of the entire semiconductor chip.

Means for Solving the Problems In order to solve the above problems, the present invention has a plurality of memory cells, a bit line connected to the memory cells, and a sense amplifier connected to one end of the bit lines. In the semiconductor memory device, the bit line may include at least a first bit line portion to which the memory cell is connected, a second bit line portion to which the memory cell is connected, and the first bit line portion. And a resistance means for connecting the second bit line portion in series. Further, in the present invention, the resistance means is constituted by a MOS transistor, and a predetermined resistance value is obtained by controlling a gate voltage of the MOS transistor.

Operation As described above, the configuration in which the bit line is divided into two or more by the resistance means and connected in series via the resistance means has the same capacity as the whole bit line, but the bit line farthest from the sense amplifier is connected. Since the capacitance has a resistance means in front of it, the capacitance value seen from the sense amplifier becomes smaller due to this resistance value, the apparent bit line capacitance seen from the sense amplifier as a whole becomes smaller, and the amplification speed of the sense amplifier becomes smaller. And speeding up becomes possible. This resistance means is constituted by a MOS transistor, and by controlling the gate potential of the MOS transistor, the effect of increasing the resistance value of the MOS transistor during reading and decreasing the apparent bit line capacitance is enhanced. The effect of reducing the resistance value of the transistor and shortening the time for actually amplifying the bit line can be obtained.

Embodiment An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a diagram showing one embodiment of a memory cell array of a semiconductor memory device of the present invention. SA1 to SA4 are sense amplifiers, ROWDEC is a row decoder, WL1 to WL16 are word lines, BL1 to BL8 are bit lines, Q11 to Q28 are N-channel MOS transistors, ○ marks at the intersections of word lines and bit lines are memory cells, VCC is a power supply voltage, and BLD is a bit line division signal. The operation is the same as the conventional one,
For example, when word line WL3 is selected, bit line BL
2, the information of the memory cell is read out to BL3, BL6, BL7, and the minute potential differences generated in the bit lines BL1 and BL3, BL2 and BL4, BL5 and BL7, BL6 and BL8 are sense amplifiers SA1, SA2, SA3, respectively. SA
Amplified by 4 and output as data. As described above, the bit lines BL1 to BL8 are divided into two bit line portions by the MOS transistors Q11 to Q18, which are resistance means, and are connected in series via the MOS transistors Q11 to Q18. Lines BL1 to BL8 have the same capacitance, but have sense amplifiers SA1 to SA1.
The capacitance of the bit line part farther from the sense amplifier is smaller due to this resistance because the MOS transistor is in front of it, and the apparent bit line capacitance as seen from the sense amplifier as a whole is smaller. As a result, the amplification speed of the sense amplifier is increased and the speed can be increased. As a method of controlling the resistance value of a MOS transistor which is a resistance means for dividing and connecting a bit line, a gate potential (bit line dividing signal BLD) is controlled so that, for example, a power supply voltage VCC is used at the time of reading, and an N-channel MOS transistor Q11 is used.
Also, the effect of reducing the apparent bit line capacitance by increasing the resistance value between the source and drain when Q18 is on is enhanced, and the bit line division signal BLD is set to a potential higher than the power supply voltage at the time of writing, and the N-channel MOS transistor Q11 Or reduce the resistance between the source and drain when Q18 is turned on, shorten the time required to amplify the bit line to logic values "H" and "L", and completely change the level of logic value "H" to the power supply voltage. Can be VCC.

As described above, according to the semiconductor memory device of the present invention,
The speed of the sense amplifier can be increased without increasing the layout area of the semiconductor chip, and a high-speed semiconductor memory device can be supplied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor memory device. SA1 to SA4 Sense amplifier ROWDEC Row decoder WL1 to WL16 Load line BL1 to BL8 Bit line Q11 to Q28 N-channel MOS transistor Circle mark at intersection of word line and bit line Memory cell VCC: Power supply voltage BLD: Bit line division signal

Claims (2)

(57) [Claims] 1. A semiconductor memory device having a plurality of memory cells, a bit line connected to the memory cell, and a sense amplifier connected to one end of the bit line, wherein the bit line includes at least the memory cell Are connected, a second bit line portion to which the memory cell is connected, and resistance means for connecting the first bit line portion and the second bit line portion in series. A semiconductor memory device, wherein an apparent capacitance value of a bit line portion far from the sense amplifier is reduced by the resistance means. 2. The resistance means comprises a MOS transistor, and controls a gate voltage of the MOS transistor so that an apparent capacitance value of a bit line portion remote from the sense amplifier is reduced. 2. The semiconductor memory device according to claim 1, wherein a value is obtained.