JP2960809B2 - Attenuator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an attenuator circuit used for audio equipment such as an audio amplifier and a cassette tape recorder and video equipment such as a video camera and a VTR.

[0002]

2. Description of the Related Art Attenuator circuits for adjusting the level of an input signal to a level suitable for a subsequent circuit and outputting the same are provided in audio equipment such as an audio amplifier and a cassette tape recorder and video equipment such as a video camera and a VTR. Many are used. As an example of this attenuator circuit, for example, the one shown in FIG. In the figure, a positive logic (NPN type) digital transistor 1 and a negative logic (PNP type) digital transistor 2 connected to a control terminal C have a control voltage of 0 V or 5 V, which will be described later. Then, when a control voltage of, for example, 0 V is applied to the control terminal C, the base of the positive logic digital transistor 1 is
0V is applied to the side terminal BT and the output becomes open.
You. In addition, the negative logic digital transistor 2
0V is applied to the terminal ET on the
Since the child BT is grounded, the bias voltage becomes 0V.
Ri, the output is ing and open. When a control voltage of 5 V is applied , a positive logic digital transistor
5V is applied to the base terminal BT of No. 1 and its output is
Rose, and negative logic digital transistor 2
5V is applied to the emitter side terminal ET of the
Since the terminal is grounded, the characteristics of the digital transistor
Due to the nature, a negative bias voltage is applied, and the output is closed . The transistors 3 and 4 are turned on when a voltage higher than a predetermined value is applied to their base terminals. Terminals A and B in the figure are input terminals for inputting a signal to be attenuated, and terminal D is an output terminal for outputting the signal after attenuated. In this circuit, the power supply voltage V
cc is 9V. And resistors 5, 6, 7,
Reference numerals 8, 14, and 15 constitute an attenuating circuit for attenuating signals input from the A and B terminals by a predetermined level.

The circuit shown in FIG. 2 has a selection function for selectively attenuating a signal from the input terminal A or the input terminal B. That is, when a control voltage of 0 V is applied to the control terminal C, the outputs of the digital transistors 1 and 2 are each opened, so that the power supply voltage Vcc of 9 V is applied to the base terminal of the transistor 3. This turns on and the collector voltage becomes 0V. On the other hand, no voltage is applied to the base terminal of the transistor 4, so that the transistor 4 is turned off, and the emitter-collector terminal is turned off. Therefore, only the signal from the input terminal B is selectively input to the above-described attenuating circuit, and the attenuated signal is output from the output terminal D. When a control voltage of 5 V is applied to the control terminal C, on the contrary, only the signal from the input terminal A is selectively input, and a signal obtained by attenuating the signal is output from the output terminal D. Will be.

[0004]

However, in such a conventional attenuator circuit, when a control voltage of 5 V is applied to the control terminal C, that is, only the signal from the input terminal A is selectively input. If the level of this signal is high or the amount of attenuation in the above-described attenuation circuit is small, the input waveform may be different from the output waveform. That is, the input terminal A is selected,
When 5 V is applied to the control terminal C, the digital transistor 1 is closed and the transistor 3 is turned off, so that 5 V input to the input terminal A is applied to the resistor 5.
The output terminal D is attenuated to a predetermined level by 6, 7, 8
Since the base terminal of the transistor 3 is grounded via the closed digital transistor 1 as shown in FIG. 2, even if the transistor 3 is turned off, the collector base terminal The NP connection between them functions as a diode. When an AC signal is applied from an input terminal, the NP connection is conducted for a predetermined minus signal and the digital signal in a closed state is provided.
Input terminal A to be grounded through transistor 1
There is a problem that the signal input from the input terminal is clipped and the signal output from the output terminal D is distorted.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and has a similar shape to an input signal regardless of the level of an input signal or the amount of attenuation of an attenuation circuit. It is an object of the present invention to provide an attenuator circuit capable of outputting the output signal of (1).

[0006]

SUMMARY OF THE INVENTION The present invention will be easily understood.
For the sake of simplicity, the embodiments described below are cited for each component of the present invention.
The description will be given with reference numerals. Note that the reference numerals are
It is attached for convenience and is not limited to the embodiment.
No. In order to achieve the above object, the present invention provides a plurality of input terminals (A, B) for inputting signals from the outside, and a signal input from a specific input terminal among the plurality of input terminals (A, B) . Selecting means for selecting an input, and resistors (5, 6,... ) For lowering a signal input from an input terminal selected by the selecting means to a predetermined level without changing the signal waveform
7, 8, 14, 15) , and an output terminal for outputting a signal whose level has been reduced by the attenuation circuit
A attenuator circuit having a (D), the selection
The means comprises a first input terminal (A) and a second input terminal (B).
Input terminal switching provided between output terminals (D)
Switching transistors (3, 4) and each of the input terminals
To the bias voltage input terminals of the transistors (3, 4)
A transistor for supplying a bias voltage, and
An input terminal switching transformer for supplying the bias voltage.
Equipped with transistors with different polarities from the transistors (3, 4)
A transistor circuit (10, 2) and a first input terminal (A)
And to select one of the second input terminal (B)
A control signal attached to the first input terminal (A) and the second input terminal (A).
Each transistor circuit (10, 10) corresponding to the input terminal (B)
2) A common system for controlling the conduction / non-conduction of transistors
Control signal input to each transistor circuit (10, 2)
And a control signal from the control terminal (C).
The transistor corresponding to the input terminal selected based on
The transistors of the power supply circuit are turned off,
The transistor of the transistor circuit corresponding to the
To each transistor circuit (10, 2)
An attenuator circuit characterized by applying a bias voltage .

[0007]

According to the attenuator circuit of the present invention configured as described above, the transistor in the transistor circuit (10, 2) can be used.
The transistor is connected to each input terminal switching transistor (3,
4) Supply bias voltage to bias voltage input terminal
Input that supplies a bias voltage as a transistor
Different polarity from the terminal switching transistors (3, 4)
By using a transistor, the input terminal that is not conducting
Diode between collector and base of switching transistor
Even if the signal conducts as a
Collector of non-conducting transistor in the circuit
Between the bases, the collector of the input terminal switching transistor
To have the opposite polarity to the diode between the
This will prevent the signal from passing. Also, the control terminal
Input terminal selected based on the control signal from (C)
The transistor of the transistor circuit corresponding to
The transistor circuit corresponding to the unselected input terminal.
Each transistor is connected so that the
To apply a bias voltage to the
A force signal can be output. And, in the non-conductive state
The collector base of a certain input terminal switching transistor
When the input signal conducts as a diode between
Even if the transistor in the transistor circuit is off
Between the collector and the emitter of the transistor.
It is not grounded through. Therefore, the signal input from the input terminal selected by the selection means is attenuated to a predetermined level by the attenuation circuit without being distorted by the selection means, and is output from the output terminal (D).
Therefore, regardless of whether the input signal level is high or low, and whether the attenuation amount of the attenuation circuit is set high or low, the input signal does not distort and maintains a similar shape. It will be output as it is. Therefore, the dynamic range of the input increases.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an attenuator circuit according to the present invention. In this circuit, the same members as those in the circuit shown in FIG. 2 are denoted by the same reference numerals. Control terminal C is negative
Base of logic (PNP) digital transistor 10
Side terminal BT and a negative logic of the digital transistor 2 Emitting
Are connected to the data terminal ET . Control terminal C
Is a terminal for supplying a control signal to these two digital transistors 10 and 2 to turn them on and off. In this embodiment, voltages of 0 V and 5 V are used for the control signal. The output of the digital transistor 10 is open when a voltage of 5 V is used for the control signal, and the output of the digital transistor 2 is open when a voltage of 0 V is used for the control signal. is there. A resistor 11 and a resistor 12 for dividing a power supply voltage are connected to the digital transistor 10.

In this embodiment, 9 V is used as the power supply voltage Vcc, and the emitter of the digital transistor 10 of negative logic is used.
A voltage lower than 5 V obtained by dividing 9 V by the resistors 11 and 12 is applied to the data terminal ET . The digital transistor 10 has a base terminal B
T to the control terminal C, and the emitter side terminal ET to the power supply voltage Vc.
c between the resistor 11 and the resistor 12 which divide voltage c.
The terminal CT ( output side ) is connected to the base terminal of the transistor 3 via the resistor 13 . The digital transistor 2 has a base terminal BT grounded and an emitter terminal
The terminal ET is connected to the control terminal C, and the collector terminal CT ( output side ) is connected to the base terminal of the transistor 4 via the resistor 16.
Connected to The transistor 3 is connected when the output of the digital transistor 10 is open (control terminal
In the case where the control signal of 5V is applied to C), between the collector-emitter terminals becomes off Ru blocked. The transistor 3 is turned on when the output of the digital transistor 10 is closed (when a control signal of 0 V is supplied to the control terminal C ), and the voltage between the collector and the emitter of the transistor 3 is changed. Conducted. On the other hand, the transistor 4 is adapted to the inverse operation to the transistor 3. That is, the transistor 4 operates when the output of the digital transistor 2 is open (the control terminal C
To the 0V if the control signal is applied) of Ru is blocked between the collector-emitter terminal turned off. Also ,
When the output of the digital transistor 2 is closed (when a control signal of 5 V is applied to the control terminal C ), the transistor 4 is turned on, and the collector and the emitter are conducted.

An input terminal A and an input terminal B are connected to a resistor 5,
6, 7, 8, 14, and 15, respectively. An output terminal D for outputting signals from these input terminals A and B passing through the attenuation circuit is connected to the attenuation circuit. The signal from the input terminal A is connected to the resistors 5, 6, among the resistors constituting the attenuation circuit.
The signal level of the signal from the input terminal B is reduced by the resistors 7, 8, 14 and 15.

The attenuator circuit of the present invention configured as described above operates as follows. First, control terminal C
When a control signal of 5 V is applied to the base terminal, 5 V is applied to the base side terminal BT of the negative logic digital transistor 10.
The voltage is divided to the emitter side terminal ET to be lower than 5V.
Voltage is applied, and the characteristics of digital transistors
Resistance between the base and emitter terminals
The base terminal is bypassed via a resistor
To become the positive potential is applied, the output is open <br/> down and ing. Then, the transistor 3 is turned off and Do Ri, the inter collector-emitter terminals is blocked. On the other hand, 5 is also applied to the terminal ET on the emitter side of the digital transistor 2 of negative logic.
V is applied, the base terminal BT is grounded, and
Emitter terminal and base terminal inside digital transistor 2
Is connected, the base terminal has a negative bias voltage.
Takes pressure, output of that is closed and ing. Therefore, the closed digital transistor is connected to the base terminal of the transistor 4 .
Passed between emitter-collector side terminals of transistor 2
5 V from the control terminal C is applied via the resistor 16, which turns on, and conducts between the emitter-collector terminals to make the collector voltage 0 V. With this operation, the signal input from the input terminal B is grounded by the transistor 4 and is not input to the attenuation circuit. On the other hand, the signal input from the input terminal A is input to the attenuation circuit composed of the resistors 5, 6, 7, and 8, since the transistor 3 is off. From the output terminal D, a signal attenuated by this attenuation circuit is output. The attenuation rate of this attenuation circuit is determined by the resistance values of the resistors 5, 6, 7, and 8, respectively. Also, transistor 3 is off.
Digital transistor connected to its base terminal
Since the output of 10 is open, the transistor
The signal passed between the collector and base terminals of
Through the collector-emitter side terminal of transistor 10
It will not be grounded. In addition, transistor 3
Digital Trang di (NPN type) and negative logic (PNP type)
The polarity of the transistor 10 is different,
The signal that has passed between the
Passing between collector and base side terminals of transistor 10
Can not. Therefore, the signal input from the input terminal A
The signal is clipped and sent to the attenuation circuit without distortion
It will be.

Further, when the control signal of 0V is applied to the control terminal C is the negative logic of the digital transistor 2 d
0V is applied to the terminal ET on the transmitter side and the terminal on the base side
Since the BT is grounded, the bias voltage becomes 0V.
Ri, the negative logic of the output of the digital transistor 2 O <br/> Pung and ing. Then, the transistor 4 is turned off and Do Ri, the collector - emitter terminals is blocked. On the other hand, negative theory
0 on the base side terminal BT of the digital transistor 10
V is applied, and is lower than 5 V at the emitter side terminal ET.
Voltage is applied, and the characteristics of the digital transistor,
That is, the resistance between the base and emitter terminals
Is connected to the base terminal
A negative potential is applied and its output is closed . Soshi
Thus, a voltage lower than 5 V obtained by dividing 9 V of the power supply voltage Vcc by the resistors 11 and 12 through the resistor 13 is applied to the base terminal of the transistor 3, which is turned on and the emitter is turned on. -The collector voltage is set to 0 V by conducting between the collector terminals. With this operation, the signal input from the input terminal A is grounded by the transitor 3 and is not input to the attenuation circuit. On the other hand, the signal input from the input terminal B includes the resistors 7, 8,
The signal is input to the attenuating circuit composed of 14 and 15, and the signal attenuated by this attenuating circuit is output from the output terminal D. Also, transistor 4 is turned off.
The digital transformer connected to its base
Since the output of transistor 2 is open, the transistor
The signal passing between the collector and base terminals of the star 4
Through the collector-emitter terminal of the digital transistor 2
It will not be grounded too much. In addition, transistor 4
(NPN type) and negative logic (PNP type) digital transition
The polarity of transistor 4 is different from that of
The signal that has passed between the
Passing between the collector and base side terminals of the
Absent. Therefore, the signal input from the input terminal B is
Being clipped and sent to the damping circuit without distortion
Become.

Since the attenuator circuit of this embodiment operates as described above, the amount of attenuation of the attenuating circuit is set to be larger even if the signal levels input from the input terminals A and B are large or small. Regardless of whether the signal is set or set small, the input signal is output without distortion and with a similar shape maintained. Therefore, the dynamic range of the input increases.

[0014]

As is apparent from the above description, according to the present invention, the input signal is not clipped, and the signal is attenuated regardless of the level of the input signal. Regardless of the magnitude of the attenuation rate set in the circuit, a signal without distortion can be output from the output terminal, and the dynamic range can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an attenuator circuit according to the present invention.

FIG. 2 is a circuit diagram of a conventional attenuator circuit.

[Explanation of symbols]

1, 2: Digital transistor (selection means) 3, 4: Transistor (selection means) 5, 6, 7, 8, 14, 15: Resistor (attenuation circuit) A, B: Input terminal C: Control terminal (selection means) D: output terminal BT: base terminal of digital transistor CT: collector terminal of digital transistor ET: emitter terminal of digital transistor

Claims (1)

(57) [Claims] 1. A plurality of input terminals for inputting a signal from the outside, a selecting means for selecting a signal input from a specific input terminal among the plurality of input terminals, and an input selected by the selecting means An attenuator circuit having a resistor that reduces a signal input from a terminal to a predetermined level without changing the signal waveform, and an output terminal that outputs a signal whose level is reduced by the attenuator. Wherein the selection means supplies an input terminal switching transistor provided between the first input terminal and the second input terminal and the output terminal, and supplies a bias voltage to a bias voltage input terminal of each of the input terminal switching transistors. Transistor
Input terminal for supplying the bias voltage
Equipped with a transistor having a different polarity from the
To select a transistor circuit and one of a first input terminal and a second input terminal
A control signal associated with the first input terminal and the second input terminal.
Transistor of each transistor circuit corresponding to the input terminal
Each transient common control signal for controlling the Dodori / Hidodori
A control terminal for inputting to the star circuit, and based on a control signal from the control terminal, the transistor of the transistor circuit corresponding to the selected input terminal is turned off.
In the state, the transistor corresponding to the unselected input terminal
Each transistor in the circuit is turned on so that
An attenuator circuit characterized by applying a bias voltage to a star circuit .