JP2962247B2 - In-circuit emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an in-circuit emulator, and more particularly to an in-circuit emulator for emulating a microcomputer having an address bus corresponding to each of a program memory area and a data memory area.

[0002]

2. Description of the Related Art An in-circuit emulator is a device for realizing the operation of a specific microcomputer.
First, the function of this in-circuit emulator will be described.

The memory space of the microcomputer to be emulated and the memory space of the entire target system using the microcomputer mainly include a program memory area used for storing programs,
It is often divided into a data memory area mainly used for storing data. Each of the mapping areas mapped in the program memory area is called a mapping area, and an unused area is called a non-map area. Further, the mapping areas are distinguished by the attributes of the memory used. The area to which the ROM is assigned is called a ROM area, and the area to which the RAM is assigned is called a RAM area. The function of detecting access to the non-map area and write access to the ROM area and stopping emulation is a mapping function. Stopping emulation by this function is called a non-map break and a write protect break.

In the data memory area, a special function register (hereinafter, referred to as SFR) and an area called a main RAM are allocated. The function to detect unauthorized access to this SFR and stop emulation
This is an FR protection function. Stopping the emulation by this function is called an SFR protect break. There are five types of unauthorized access to the SFR. The first is an access to an address where no SFR exists in an area allocated to the SFR area. The second is a write access to a read-only SFR. Third, light-only S
Read access to FR. The fourth is byte access to the SFR for which byte access is prohibited. The fifth is word access to the SFR for which word access is prohibited.

FIG. 7 is a block diagram showing a configuration example of a conventional in-circuit emulator. In this conventional in-circuit emulator, there is an evaluation chip 101 which operates in the same manner as the microcomputer to be emulated and further realizes a part of the functions of the in-circuit emulator. This Eva chip 101
Thus, signals necessary for realizing the mapping function are output to the mapping unit 701.

The signals necessary for realizing the mapping function include an address signal on the EMA bus 106 of the program memory address bus and a signal BEN of the program memory bus enable signal.
D signal, BC of program memory read / write signal
URWB signal. The address signal on the EMA bus 106 is output when an access to the program memory occurs. The BEND signal is a signal that becomes “1” when the address signal on the EMA bus 106 is valid and becomes “0” when the address signal is invalid. The BCURWB signal is a signal that becomes “0” when the access to the program memory is a read access and becomes “1” when the write memory is accessed.

Using the above signals as input signals, mapping section 701 generates an NMPBK signal and a WPBK signal.
The NMPBK signal is "1" when a non-map break occurs.
The signal becomes "0" when no non-map break occurs. The WPBK signal is a signal that becomes “1” when a write-protect break occurs and “0” when a write-protect break does not occur.

[0008] Also, a signal necessary for realizing the SFR protection function is output from the evaluation chip 101 to the SFR protection section 702.

The signals required to realize the SFR protection function include an address signal on the EA bus 107 of a data memory system address bus, an STB signal of a data memory system bus enable signal, an EXUBW signal of a data memory system access width signal,
An EXURWB signal of a data memory system read / write signal and a STAC signal of a data memory system area discrimination signal. The address signal on the EA bus 107 is output when an access to the data memory occurs. The STB signal is a signal that becomes “1” when the address signal on the EA bus 107 is valid and becomes “0” when the address signal is invalid. E
The XUBW signal is a signal that becomes "0" when the data memory is accessed by byte access and becomes "1" by word access. The EXURWB signal is "0" when the access to the data memory is a read access.
The signal becomes “1” at the time of write access. The STAC signal is a signal that becomes “0” when accessing the SFR and becomes “1” when accessing the main RAM.

[0010] Using the above signal as an input signal, the SFR protector 702 generates an SFRPBK signal. SF
The RPBK signal is a signal that becomes “1” when an SFR protection break occurs and becomes “0” when an SFR protection break does not occur. Also, NMPBK signal, WP
The BK signal and the SFRPBK signal are input to the OR gate 703, and when at least one of the three signals is "1", the SVIR
The Q signal becomes "1". When all three signals are "0", the SVIRQ signal is "0". This SVIRQ
The signal is an emulation stop request signal to the evaluation chip 101.

FIG. 8 is a circuit diagram showing a detailed configuration example of the mapping unit 701. The mapping unit 701 includes a mapping memory 801, an AND gate 802, and pull-down resistors 804 and 805. Mapping memory 80
1 stores mapping data. FIG.
FIG. 4 is an explanatory diagram illustrating a format of the mapping data. This mapping data is composed of 2 bits, and “bit 1, bit 0” = “0, 0” is stored in the address of the RAM area, “1, 0” is stored in the address of the ROM area, “0, 1” is stored in the address of the non-map area. Mapping memory 80
1, an address signal on the EMA bus 106 is input to the address input, and a BE signal is input to the output enable input.
The ND signal is input. The output of the mapping memory 801 has 2 bits, and both are connected to pull-down resistors 804 and 805. These pull-down resistors 804, 805
Is for fixing the output of the mapping memory 801 which becomes Hi-z to "0" when "0" is input to the output enable input. The bit 0 output of the mapping memory 801 becomes the NMPBK signal, and the bit 1 output 803 is input to the AND gate 802 together with the BCURWB signal. Then, the output of the AND gate 802 becomes a WPBK signal.

FIG. 10 is a timing chart showing the operation when a non-map break or a write protect break occurs. Referring to FIG. 8 and FIG.
Will be described. When an access to the non-map area occurs, an address is output to the EMA bus 106 and the BE
“1” is output as the ND signal. At that time, mapping data is output from the mapping memory 801. Since the mapping data in the non-map area is “0, 1”, the NM
The PBK signal becomes “1” and the WPBK signal always becomes “0” because the bit 1 output 803 of the mapping data is “0”. Since the NMPBK signal becomes “1”, the SVIRQ signal which is an emulation stop request signal for the evaluation chip 101 also becomes “1”.

When a write access to the ROM area occurs, an address is output to the EMA bus 106 and BEND is output.
“1” is output as the signal, and “1” is output as the BCURBB signal. The mapping data of the ROM area is “1,
0 ”, the NMPBK signal becomes“ 0 ”and WPBK
The signal becomes "1". Since the WPBK signal becomes “1”, the SVIRQ signal which is an emulation stop request signal to the evaluation chip 101 also becomes “1”.

FIG. 11 is a circuit diagram showing a detailed configuration example of the SFR protection section 702. The SFR protection section 702 includes an SFR protection memory 1103, a NOT gate 1101, an AND gate 1102, and a pull-down resistor 1104. SFR protection memory 11
03 inputs an address signal, an EXURWB signal, and an EXUBW signal on the EA bus 107 as an address input, and inputs an output of the AND gate 1102 as an output enable input. AND gate 1102
The output of the NOT gate 1101 and the STB signal are input. NOT gate 1101 inputs a STAC signal. The output of the SFR protection memory 1103 has 1 bit, and a pull-down resistor 1104 is connected. This pull-down resistor 1104 is for fixing the output of the SFR protect memory 1103 that becomes Hi-z to “0” when “0” is input to the output enable. When the output of the SFR protect memory 1103 is S
This becomes the FRPBK signal.

The SFR protection memory 1103 has S
FR protection data is stored. FIG. 12 is an explanatory diagram illustrating the format of this SFR protected data. The SFR protect data is different from the mapping data in that first, data is stored as to whether byte read access is permitted for each address from the first address to the last address in the SFR area, and the byte write is stored in the upper side thereof. Data on whether access is permitted is stored, data on whether word read access is permitted is stored on the upper side, and data on whether word write access is permitted is stored on the upper side. “0” is stored in the permitted address, and “1” is stored in the prohibited address.

FIG. 13 is a timing chart showing an operation when an SFR protection break occurs. The operation of the SFR protection unit 702 will be described with reference to FIGS.

When a byte read access to the SFR area occurs, an address signal is output on the EA bus 107, and the STAC signal is "0", the STB signal is "1", and the EX signal is EX.
“0” is output as the UBW signal and “0” is output as the EXURWB signal. At this time, the SFR protection data of "00EA" is output. SFR protection data is "0"
Then, both the SFRPBK signal and the SVIRQ signal are “0”, but if the SFR protect data is “1”, the SFRP
The BK signal is “1”, and the SVIRQ signal, which is an emulation stop request signal for the evaluation chip 101, is also “1”.

Similarly, when a byte write access occurs, the SFR protected data at address "01EA" is generated. When a word read access occurs, the SFR protected data at "10EA" is generated. When a word write access occurs, "11EA" is read.
EA address "SFR protection data is output,
The FRPBK signal and the SVIRQ signal are determined.

In this conventional in-circuit emulator, a memory space of 64 Kbytes and an SFR of 256 bytes are used.
For a microcomputer with space, 6
One memory of 4K words × 2 bits or more and one memory of 1K words × 1 bit or more are required.

[0020]

In recent years, as memories have been increasing in capacity, conventional in-circuit emulators have a configuration in which two small-capacity memories, a mapping memory and an SFR protect memory, are used. The use efficiency is extremely poor, making it difficult to obtain a small-capacity memory, and hindering the miniaturization of substrates.

Further, since the means of realization is different between the mapping unit and the SFR protection unit, there is a difference in achievable specifications, and there is no uniformity of specifications.

Furthermore, since the formats of the mapping data and the SFR protect data are different, there is a problem that two separate data must be created.

Accordingly, it is an object of the present invention to provide a general-purpose part, a small-sized board, a uniform specification and an improved convenience in an in-circuit emulator.

[0024]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a method for emulating a microcomputer in which a memory space is divided into a program memory area for storing programs and data, and a data memory area, and has a corresponding address bus. Mapping data indicating an attribute of each mapping area mapped in the program memory area; and access permission / access to each special function register allocated in the data memory area.
Protected data indicating non-permission is set in advance, and in an in-circuit emulator that detects unauthorized access to each of the mapping areas and each of the special function registers and stops emulation, a bus signal of each of the address buses is input and A selection means for selecting and outputting one bus signal by a control signal, and a storage means for inputting a bus signal output of the selection means as an address and presetting and storing the mapping data and the protection data.

Further, the control signal is a signal corresponding to one of signals indicating a valid period of the address signal on each address bus.

[0026]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an in-circuit emulator according to the present invention. Referring to FIG. 1, the in-circuit emulator according to the present embodiment includes:
Evaluation chip 101, control circuit 103, selector 102,
And a break signal generation circuit 105.

The control circuit 103 uses the BEND signal and the STB signal output from the evaluation chip 101 to
It generates and outputs two control signals. One is selector 1
SELE which determines which signal is to be selected from the signals output to the selector 102 and input to the selector 102.
It is a CT signal. The other is a PROMOE signal output to the protect memory 104 and serving as an output enable signal of the protect memory 104. PR
The OMOE signal is "1" when valid and "0" when invalid.

The selector 102 includes an EMA bus 106 and an EA bus 107 output from the evaluation chip 101.
Using the above address signal and the SELECT signal output from the control circuit 103, the address signals on the EMA bus 106 and the EA bus 107 are selected and PR
Output as OMAD signal. When the SELECT signal is "1", the address signal on the EA bus 107 is PR
When the signal is "0", the EMA bus 106
The upper address signal becomes the PROMAD signal.

The protect memory 104 includes the selector 10
2 and the control circuit 10
3 using the PROMOE signal output from
When the PROMOE signal becomes "1", a protect data signal stored at the address indicated by the PROMAD signal is output. A pull-down resistor 122 is connected to the output of the protection memory 104. This pull-down resistor 122 is a protection memory 104 that becomes Hi-z when “0” is input to the output enable.
Is fixed at "0".

The break signal generation circuit 105 controls the protection data 1 output from the protection memory 104.
17 and the BEND signal, STB signal, BCUBW signal, EXUBW signal, B
Using CURWB signal and EXURWB signal, SVI
RQ signal, NMPBK signal, WPBK signal and SFRPB
Generate and output a K signal. The BCUBW signal is a signal that becomes “0” when the access to the program memory is a byte access and becomes “1” when the word memory is accessed.

FIG. 2 is a circuit diagram showing a detailed configuration example of the control circuit 103. The control circuit 103 includes one OR gate 201. The BEND signal and the STB signal are input to the OR gate 201, and the output of the OR gate 201 is a PROMOE signal. In other words, if either the BEND signal or the STB signal becomes “1”, PR
The OMOE signal becomes “1”. The SELECT signal is S
The TB signal is used as it is. That is, the EA bus 107
The SELECT signal is set to "1" only when the upper address signal is valid, and when the EA bus 107 is invalid, including when the address signal on the EMA bus 106 is valid.
The signal is set to “0”.

FIG. 3 is an explanatory diagram for explaining the format of a protect data signal output from the protect memory 104. The protect data is data indicating an access mode permitted for an arbitrary address, and is stored in the protect memory 104. The protect data signal has a 7-bit configuration.

Bit 0 is a bit indicating whether or not read access is possible. If "0", permission is given, and if "1", permission is prohibited. Bit 1 is a bit indicating whether write access is possible or not.
“0” indicates permission, and “1” indicates prohibition. Bit 2 is
This bit indicates whether byte access is possible or not. If "0", it is permitted, and if "1", it is prohibited. Bit 3 is a bit indicating whether or not word access is possible. If "0", permission is given; if "1", permission is prohibited. In an address or a non-map area where no SFR exists, all of the bits 0, 1, 2, and 3 are "1".
Bits 4, 5, and 6 are bits indicating an area attribute. If “bit 4, bit 5, bit 6,” = “1, 0, 0”, R
OM area, if it is “0,1,0”, RAM area, “0,0,
1 ”indicates the SFR area. The non-map area is“ 0,
0, 0 ”. Bits 4, 5, and 6 are two or more“ 1 ”.
Never be.

FIG. 4 is a circuit diagram showing a detailed configuration of the break signal generation circuit 105. The break signal generation circuit 105 includes two three-state buffers, two NOT gates, seven AND gates, one OR gate, and one NOR gate. Here, each bit of the protect data signal is represented by PROMDA
[0] signal, bit 1 is PROMDA [1] signal, bit 2 is PROMDA [2] signal, bit 3 is PROMD
A [3] signal, bit 4 is PROMDA [4] signal, bit 5 is PROMDA [5] signal, bit 6 is PROMDA
This is indicated by the DA [6] signal.

When the BEND signal is valid, the three-state buffer 402 outputs the BCUBW signal and the BCURBB signal as they are, but outputs Hi-z when the BEND signal is invalid. On the other hand, when the STB signal is valid, the three-state buffer 403
Outputs the EXUBW signal and the EXURWB signal as they are, but outputs Hi-z when they are invalid. The outputs of the two three-state buffers are directly connected to the BCUBW signal and the EXUBW signal, and the BCURB signal and the EXURWB signal, respectively. The signal directly connected between the BCUBW signal and the EXUBW signal is the BW signal, and the BCURBB signal and the EXURW signal.
The signal directly connected to the B signal is the RWB signal.

FIG. 5 is a timing chart showing the operation when a non-map break or a write protect break occurs. FIG. 6 is a timing chart showing an operation when an SFR protection break occurs. The operation when a non-map break, a write protect break, and an SFR protect break occur will be described below with reference to FIGS. Here, the protected data shown in FIGS. 5 and 6 are described in the order of bits 6, 5, 4, 3, 2, 1, and 0.

When a byte access occurs, either the BEND signal or the STB signal becomes "1", and the protected data 117 corresponding to the address is stored in the protected memory 1.
04. Also, the BW signal becomes “0”.
When the BW signal is “0”, the output of the NOT gate 406 becomes “1”, and the output of the AND gate 405 is determined by the PROMDA [2] signal. When byte access is prohibited, since the PROMDA [2] signal is "1", the output of the AND gate 405 becomes "1", and the output of the OR gate 412, that is, the SVIRQ signal becomes "1". On the other hand, when the byte access is permitted, since the PROMDA [2] signal is "0", the output of the AND gate 405 becomes "0", and the SVIRQ signal is determined by other factors. on the other hand,
When the BW signal is “0”, the output of the AND gate 404 is always “0” regardless of the PROMDA [3] signal.
The VIRQ signal is determined by other factors.

When a word access occurs, the BW signal becomes "1", contrary to when a byte access occurs.
When the BW signal is "1", the output of the NOT gate 406 becomes "0", and the output of the NOT gate 406 becomes AN regardless of the PROMDA [2] signal.
Since the output of D gate 405 is always "0", SVIRQ
The signal is determined by other factors. When the BW signal is "1", the output of the AND gate 404 is PROMDA
[3] Determined by signal. When word access is prohibited, since the PROMDA [3] signal is "1", the output of the AND gate 404 becomes "1", and the SVIRQ signal becomes "1". On the other hand, when word access is permitted, PR
Since the OMDA [3] signal is "0", the AND gate 40
4 becomes "0", and the SVIRQ signal is determined by other factors.

When a read access occurs, either the BEND signal or the STB signal becomes valid, and the RWB signal becomes "0". When the RWB signal is "0", the output of the NOT gate 409 becomes "1", and the output of the AND gate 408 is determined by the PROMDA [0] signal. When the read access is prohibited, the output of the AND gate 408 becomes "1" because the PROMDA [0] signal is "1",
The IRQ signal becomes "1". On the other hand, when the read access is permitted, the PROMDA [0] signal is "0", and
The output of gate 408 is always "0" and the SVIRQ signal is determined by other factors. Also, when the RWB signal is “0”, the AND is independent of the PROMDA [1] signal.
Since the output of gate 407 is always "0", the SVIRQ signal is determined by other factors.

When a write access occurs, contrary to when a read access occurs, either the BEND signal or the STB signal becomes valid, and the RWB signal becomes "1". R
When the WB signal is “1”, the output of the NOT gate 409 becomes “0”, and the output of the NOT gate 409 becomes AN regardless of the PROMDA [0] signal.
The output of the D gate 408 becomes "0", and the SVIRQ signal is determined by other factors. Also, the RWB signal is "1".
, The output of the AND gate 407 is PROMDA [1]
Determined by signal. PR when write access is prohibited
Since the OMDA [1] signal is "1", the AND gate 40
7 becomes "1", and the SVIRQ signal becomes "1". On the other hand, when write access is permitted, PROMDA
[1] Since the signal is "0", the output of the AND gate 407 is always "0", and the SVIRQ signal is determined by other factors.

The NMPBK signal is an output of the AND gate 411. When the SVIRQ signal is "1" and the protected data signal indicates a non-map area, NM
The PBK signal becomes "1". At this time, as for the protected data signal indicating the non-map area, the PROMDA [4] signal, the PROMDA [5] signal, and the PROMDA [6] signal all become "0", and the output of the NOR gate 401 becomes "1". It is.

The WPBK signal is the output of the AND gate 413. When the output of the AND gate 407 is “1” and the protect data signal indicates the ROM area, the WPBK signal becomes “1”. At this time, the protect data signal indicating the ROM area is PROMDA [4]
This is because the signal becomes “1”.

The SFRPBK signal is supplied to the AND gate 410
Is the output of When the SVIRQ signal is “1” and the protect data signal indicates the SFR area, the SF
The RPBK signal becomes “1”. At this time, the PROMDA [6] signal of the protected data signal indicating the SFR area is "1".

As described above, the in-circuit emulator according to the present embodiment has the same operation as the conventional in-circuit emulator shown in FIG. However, the conventional in-circuit emulator required two memories,
In the in-circuit emulator of this embodiment, 64K
When a microcomputer having a memory space of 256 bytes and an SFR space of 256 bytes is targeted, a memory space of 64 Kbytes includes an SFR space of 256 bytes.
Only one memory of 64K words × 7 bits or more is required.

[0045]

As described above, the in-circuit emulator according to the present invention comprises a mapping memory and an SFR.
By combining the protected memories into one protected memory, a versatile large-capacity memory can be used.

Further, since the difference between the specifications of the mapping function and the SFR protection function is eliminated, the specifications that can be realized are unified, and the same illegal access can be detected in the entire memory space.

Furthermore, there is an effect that only one piece of protect data is created in advance, and convenience is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an in-circuit emulator according to the present invention.

FIG. 2 is a circuit diagram showing a control circuit in FIG.

FIG. 3 is an explanatory diagram illustrating a format of protected data in FIG. 1;

FIG. 4 is a circuit diagram showing a break signal generation circuit in FIG. 1;

FIG. 5 is a timing chart showing an operation when a non-map break and a write protect break occur in the in-circuit emulator of FIG. 1;

FIG. 6 shows an S in the in-circuit emulator of FIG.
5 is a timing chart showing an operation when an FR protection break occurs.

FIG. 7 is a block diagram illustrating a configuration example of a conventional in-circuit emulator.

8 is a circuit diagram illustrating a detailed configuration example of a mapping unit in FIG. 7;

FIG. 9 is an explanatory diagram illustrating a format of mapping data in FIG. 8; .

FIG. 10 is a timing chart showing an operation when a non-map break and a write protect break in FIG. 8 occur.

11 is a circuit diagram showing a detailed configuration example of an SFR protection section in FIG. 7;

FIG. 12 is an explanatory diagram for explaining the format of SFR protected data in FIG. 11;

13 is a timing chart showing an operation when SFR protection data is generated in FIG.

[Explanation of symbols]

Reference Signs List 101 evaluation chip 102 selector 103 control circuit 104 protect memory 105 break signal generation circuit 106 program memory system address bus (EMA bus) 107 data memory system address bus (EA bus) 122 pull-down resistor 201 OR gate 401 NOR gate 402, 403 three-state buffer 404, 405, 407, 408, 410, 411, 4
13 AND gates 406, 409 NOT gate 412 OR gate 701 Mapping unit 702 SFR protect unit 703 OR gate 801 Mapping memory 802 AND gate 804, 805 Pull down resistor 1101 NOT gate 1102 AND gate 1103 SFR protect memory 1104 Pull down resistor

Claims (2)

(57) [Claims] When emulating a microcomputer having a memory space divided into a program memory area for storing programs and data and a data memory area and having an address bus corresponding to each memory area, each memory area mapped in the program memory area is emulated. Mapping data indicating the attributes of the mapping area, etc., and protect data indicating access permission / non-permission to each special function register allocated in the data memory area are set in advance, and the mapping areas and the special functions are set. In an in-circuit emulator which detects an illegal access to a register and stops emulation, a selection means for inputting a bus signal of each address bus and selecting and outputting one of the bus signals by a control signal, and a bus signal output of the selection means. Storage means for inputting a force and setting and storing the mapping data and the protection data in advance. 2. The in-circuit emulator according to claim 1, wherein said control signal is a signal corresponding to one of signals indicating a valid period of an address signal on each of said address buses.