JP2962273B2 - Exposure / drawing apparatus, exposure / drawing method, and recording medium storing exposure / drawing processing program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure / drawing apparatus, an exposure / drawing method, and a recording medium on which an exposure / drawing processing program is recorded.
The present invention relates to an exposure / drawing apparatus, an exposure / drawing method, and a recording medium on which an exposure / drawing processing program is recorded, which can correct a positional deviation of a drawing pattern caused by expansion and contraction of a sample such as a wafer) or a sample stage.

[0002]

2. Description of the Related Art In recent years, the line width of a circuit pattern formed on a wafer has become extremely small due to high integration and miniaturization of a semiconductor integrated circuit. Along with this, in a lithography process for forming a circuit pattern on a wafer, transfer of a finer pattern is required. An electron beam writing method is known as a method for satisfying such a demand for finer patterns.

In general, in the electron beam lithography method, a global alignment method is used as an alignment method when performing electron beam lithography, as in the case of reduced projection exposure. In the global alignment method, alignment marks of a plurality of chips on a wafer are continuously detected prior to writing, and an alignment error of chips on the wafer is corrected in a wafer plane. At this time, the correction amount of the chip position is usually represented by a polynomial such as a quadratic equation. After completion of the mark detection and correction, writing of all chips on the wafer is continuously performed while correcting the position of the chip to be written. Therefore, the global alignment method has the advantage that the time required for alignment can be greatly reduced and the throughput is greatly improved, as compared with the die-by-die alignment method in which alignment and writing are repeated for each chip. doing.

In this global alignment method, time elapses between the alignment operation and the writing operation.
During the writing after the alignment, the wafer expands or contracts due to the temperature difference due to the temperature difference, which causes a problem that the overlay accuracy is deteriorated. In particular, the problem of the expansion and contraction of the wafer during writing is remarkable in the electron beam writing method in which the writing time is long.

A technique for solving this problem has been proposed, for example, in Japanese Patent Application Laid-Open No. Hei 6-13299. FIG.
FIG. 1 is a side view showing this conventional electron beam drawing apparatus and method. As shown in FIG. 7, in the conventional electron beam writing method, a temperature change is measured by a temperature sensor 11 provided on a sample stage 10 of an electron beam writing apparatus, and the amount of temperature change and the sample stage 10 and the sample 12 such as a wafer are measured. The control computer 13 calculates the amount of displacement of the sample 12 assumed from the coefficient of thermal expansion, controls the deflection system 14 or the laser length measurement system 15 based on the calculated amount of displacement, and radiates from the electron gun 16. The correction of the irradiation position of the electron beam 17 is performed. In FIG. 7, reference numeral 18 denotes a lens that converges the electron beam 17, and 19 denotes a drive system that moves the sample stage 10.

[0006]

However, in the conventional electron beam writing method, the amount of displacement of the sample 12 is corrected by estimating from the amount of temperature change and the coefficient of thermal expansion by calculation. It is difficult to correct the positional deviation amount with high accuracy of 10 nm level.

Further, when only the sample 12 expands and contracts on the sample stage 10, there is a problem that the amount of displacement cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is an exposure / drawing apparatus capable of correcting a positional deviation of a drawing pattern due to expansion and contraction of a sample such as a wafer or a sample stage during exposure with high accuracy. It is an object of the present invention to provide a recording medium which records an exposure / drawing method and an exposure / drawing processing program.

[0009]

According to the present invention, there is provided an exposure / drawing apparatus comprising: a drawing means for drawing a pattern on a sample; a positioning mark detecting means for detecting a position of a positioning mark formed on the sample; A sample expansion / contraction measurement mark detection unit that detects the position of a sample expansion / contraction measurement mark formed on a sample at predetermined intervals, and a position correction amount of the sample is calculated from the detection result by the alignment mark detection unit. Drawing control means for calculating a correction amount of expansion and contraction of the sample from a detection result by the mark detection means for expansion and contraction, and controlling the drawing means based on the calculated position correction amount and expansion and contraction correction amount. It is.

The sample expansion / contraction measurement mark may be a mark used for performing rough alignment of the sample.
It may be at least a part of the alignment mark.

According to the present invention, there are provided an exposure / drawing method comprising: (1) a step of detecting a position of a positioning mark formed on a sample; and (2) a position correction amount of the sample based on a detection result of the position of the positioning mark. Calculating, and performing drawing based on the position correction amount; and (3) detecting the position of the sample expansion / contraction measurement mark formed on the sample at predetermined intervals.
(4) calculating the amount of expansion / contraction correction of the sample from the detection result of the position of the sample expansion / contraction measurement mark, performing drawing based on the amount of expansion / contraction correction, and repeating at predetermined intervals until the end of drawing. It is a feature.

According to another aspect of the present invention, there is provided an exposure / drawing method comprising:
(1) a step of detecting the position of the sample mark formed on the sample to perform coarse alignment; and (2) a step of detecting the position of the alignment mark formed on the sample.
(3) calculating the position correction amount of the sample from the detection result of the position of the alignment mark, and performing drawing based on the position correction amount; and (4) detecting the position of the sample mark at predetermined intervals. (5) calculating the amount of expansion / contraction correction of the sample from the detection result of the position of the sample mark, performing drawing based on the amount of expansion / contraction correction, and repeating at predetermined intervals until the drawing is completed. It is characterized by the following.

The exposure / drawing apparatus and the exposure / drawing method of the present invention are realized by an exposure / drawing processing program, and the program may be provided by being recorded on a recording medium.

The sample is, for example, a semiconductor substrate.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the exposure / drawing apparatus of the present invention.

As shown in FIG. 1, the exposure / drawing apparatus of the present invention detects a drawing unit 1 for drawing a pattern on a sample such as a wafer or a glass mask, and a position of an alignment mark formed on the sample. An alignment mark detection unit 2, a sample expansion / contraction measurement mark detection unit 3 for detecting the position of the sample expansion / contraction measurement mark formed on the sample at predetermined time intervals,
The position correction amount of the sample is calculated from the detection result by the alignment mark detection unit 2, and the expansion / contraction correction amount of the sample is calculated from the detection result by the sample expansion / contraction measurement mark detection unit 3. A drawing control unit 4 that controls the drawing unit 1 based on the correction amount.

Although not shown, the drawing unit 1 includes an electron gun for emitting an electron beam, a lens for converging the electron beam emitted from the electron gun, a deflector for deflecting the electron beam, and a sample stage for setting a sample. And

The positioning mark detection unit 2 and the sample expansion / contraction measurement mark detection unit 3 may be the same detection device, or may be separate detection devices.

The drawing control section 4 adjusts the operation of the deflector, the operation of the sample stage, or both of the operations according to the calculated position correction amount and expansion / contraction correction amount.

The exposure / drawing apparatus of the present invention also has a setting section 5 for setting a time interval for detecting the position of the sample expansion / contraction measurement mark, and a position correction amount such as the size and shape of the sample and an expansion / contraction correction amount. Has a memory 6 for storing data necessary for the operation.

FIG. 2 is an explanatory diagram showing a chip arrangement on a wafer according to the first embodiment of the present invention. As shown in FIG. 2, nine marks T for positioning are formed on nine chips T arranged on a wafer W serving as a sample. 5μ width for alignment mark
m, a total length of 50 μm and a depth of 0.5 μm are used. In addition, on the periphery of the wafer W,
Four wafer expansion / contraction measurement marks P, Q, R, and S are formed. These wafer expansion / contraction measurement marks P, Q, R, S
Also, a cross-shaped Si step mark similar to the alignment mark is used.

FIG. 3 is a flowchart showing the operation of the first embodiment of the present invention. As a sample, FIG.
It is assumed that a wafer W shown in FIG.

When performing electron beam exposure according to the present invention,
First, as global alignment operations, alignment marks A to I on wafer W set on the sample stage.
Is detected (step S1). Then, an approximate expression representing a position correction amount such as a shift, a gain, and a rotation of the chip array on the wafer W is obtained by the least square approximation of the detection result (step S2). In the present embodiment, equations 1 and 2 are used to correct the shift, gain, rotation, and platform formation of the chip array.
Correction coefficients a0 to a3 and b0 to b in the correction formula
3 was sought.

DX = a0 + a1.X + a2.Y + a3.XY (Equation 1) dY = b0 + b1.Y + b2.X + b3.XY (Equation 2) Next, four wafer expansion / contraction measurement marks P, Q, R, and S
(Step S3). Then, the position of the chip is corrected by the above correction equation (step S
4), a pattern is drawn (step S5).

Next, as a preset time interval,
Each time the drawing of three chips is completed (step S6), the position detection of the wafer expansion / contraction measurement marks P, Q, R, and S is performed again. At this time, the difference from the previous measurement result immediately after the global alignment is the positional shift amount due to the expansion and contraction of the wafer. In this embodiment, the correction coefficient of the correction formulas 1 and 2 for the chip position is corrected based on the positional deviation amounts of the marks P, Q, R, and S, with the expansion and contraction rate of the wafer being constant in the wafer plane. In this way, a new positional shift caused by expansion and contraction of the wafer after the global alignment is corrected, and the next chip is drawn.

Next, each time three-chip writing is performed, the positional deviation due to the expansion and contraction of the wafer is corrected, and the next chip is written.
This operation is repeated until the drawing of the last chip on the wafer is completed (step S7). In this case, it is possible to correct the positional deviation of the pattern due to the expansion and contraction of the wafer with high accuracy, so that it is possible to obtain the same high overlay accuracy as in the case of using the die-by-die alignment method.

According to an experiment conducted by the present inventor, in the conventional global alignment method, a superposition displacement of up to 0.15 μm occurred in the wafer surface due to expansion and contraction of the wafer. However, the method of the present invention is used. As a result, it was possible to reduce the overlay deviation in the wafer plane to 0.05 μm. Further, the writing time per wafer did not significantly decrease as compared with the conventional global alignment method, and a higher throughput was obtained as compared with the die-by-die alignment method.

FIG. 4 is an explanatory diagram showing a chip arrangement on a wafer for explaining a second embodiment of the present invention. As shown in FIG. 4, wafer marks P ′ and Q ′ are formed at the left and right ends of the wafer W. Thirteen alignment marks A to M are formed on 49 chips T arranged on the wafer W. Wafer mark P ', Q'
The cross-shaped Si step marks are used as the wafer expansion and contraction measurement marks A to M, as in the first embodiment.

FIG. 5 is a flowchart showing the operation of the second embodiment of the present invention. In the second embodiment of the present invention, when performing the electron beam exposure, first, as a rough alignment operation of the wafer W, the positions of the wafer marks P ′ and Q ′ formed in advance on the left and right ends of the wafer are detected. (Step S1), rough alignment of the wafer W is performed (Step S2).

Next, as global alignment, position detection is performed on 13 of the alignment marks A to M among the alignment marks of the chip T arranged on the wafer W (step S3), and the first embodiment is compared with the first embodiment. Similarly, an approximate expression representing a position correction amount such as a shift, a gain, and a rotation of the chip arrangement on the wafer is obtained by the least square approximation of the detection result (step S4).

Next, drawing is performed while correcting the position of the chip based on the correction formula (step S5).

Next, the wafer marks P 'and Q' are used as wafer expansion / contraction measurement marks, and the detection coordinates of the wafer marks P 'and Q' at the time of coarse alignment are used as reference coordinates at intervals of 60 seconds from the time of coarse alignment. P ', Q'
(Steps S6 and S7). The correction of the wafer expansion and contraction is performed by using the change in the distance between the P ′ and Q ′ marks as the expansion and contraction of the wafer, and using the correction coefficient a1 indicating the gain component of the correction formula,
This is performed by adding the variation to b1 (step S1).
8). Since the time required for the global alignment is about 20 seconds and the writing time per chip is about 10 seconds, the first wafer expansion / contraction correction is performed after writing the four chips following the global alignment.

Thereafter, the wafer expansion / contraction correction is performed every writing of six chips, and this operation is repeated until writing of all 49 chips on the wafer is completed (step S9). As a result, it is possible to highly accurately correct the positional deviation of the pattern due to the expansion and contraction of the wafer, so that it is possible to obtain the same high overlay accuracy as when the die-by-die alignment method is used.

According to an experiment conducted by the present inventor, in the conventional global alignment method, a superposition displacement of up to 0.12 μm occurred in the wafer surface due to expansion and contraction of the wafer. However, the method of the present invention is used. As a result, it was possible to reduce the overlay displacement in the wafer plane to 0.06 μm.

Further, the writing time per wafer was not significantly reduced as compared with the conventional global alignment method, and a higher throughput was obtained as compared with the die-by-die alignment method.

In addition, since a mark for wafer coarse alignment is used as a mark for measuring wafer expansion and contraction, it is not necessary to separately arrange a mark for measuring wafer expansion and contraction, and the effect of increasing the chip arrangement area and improving the degree of freedom in arrangement can be obtained. It is possible.

FIG. 6 is a block diagram for explaining a third embodiment of the present invention. As shown in FIG. 6, the third embodiment of the present invention has a recording medium 7 on which a program (exposure drawing processing program) for causing a computer to execute the above-described exposure drawing processing is recorded. The recording medium 7 may be a magnetic disk, a CD-ROM, a semiconductor memory, or another recording medium.

The exposure / drawing processing program is read from the recording medium 7 into the drawing control section 4, and the drawing control section 4 executes processing according to the exposure / drawing processing program.

The present invention is not limited to the above embodiment, and various changes can be made within the scope of the technical matters described in the claims.

For example, the detection interval of the wafer expansion / contraction measurement mark described in the embodiment can be appropriately changed such as a preset time interval, chip interval, shot number interval, and the like.

Also, the number of marks and mark positions detected for wafer expansion / contraction correction are not limited to the present embodiment, and the order of expansion / contraction correction can be appropriately changed according to the required correction accuracy. . Further, in this embodiment, a positioning mark for global alignment,
The description has been given of the case where a separately prepared mark is used as the wafer expansion measurement mark and the case where the wafer expansion measurement mark is also used by using the coarse alignment wafer mark. A portion may also be used. In this case, in the first wafer expansion / contraction measurement performed prior to all writing, it is also possible to use the detection result of the alignment mark at the time of global alignment.

[0042]

According to the present invention, in electron beam exposure using the global alignment method, the positional deviation of a drawing pattern caused by expansion and contraction of a sample such as a wafer or a sample stage during writing is highly accurately corrected. Since the alignment accuracy can be obtained, it is possible to obtain the same high overlay accuracy as that of the die-by-die alignment method without significantly reducing the throughput.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an exposure / drawing apparatus of the present invention.

FIG. 2 is a diagram for explaining a first embodiment of the present invention;
FIG. 3 is an explanatory diagram showing a chip arrangement on a wafer.

FIG. 3 is a flowchart showing an operation of the first exemplary embodiment of the present invention.

FIG. 4 is a view for explaining a second embodiment of the present invention;
FIG. 3 is an explanatory diagram showing a chip arrangement on a wafer.

FIG. 5 is a flowchart showing the operation of the second exemplary embodiment of the present invention.

FIG. 6 is a block diagram for explaining a third embodiment of the present invention.

FIG. 7 is a side view showing a conventional electron beam drawing apparatus and method.

[Explanation of symbols]

 1: Drawing unit 2: Alignment mark detection unit 3: Sample expansion / contraction measurement mark detection unit 4: Drawing control unit 5: Setting unit 6: Memory 7: Recording medium W: Wafer (sample) T: Chips A, B, C,... M: alignment mark P, Q, R, S: wafer expansion / contraction measurement mark P ′, Q ′: wafer mark (sample mark)

Claims (9)

(57) [Claims] 1. A drawing means for drawing a pattern on a sample, a positioning mark detecting means for detecting the position of a positioning mark formed on the sample, and a measuring means for measuring the expansion and contraction of the sample formed on the sample A sample expansion / contraction measurement mark detection means for detecting the position of a mark at predetermined intervals; and a position correction amount of the sample calculated from the detection result by the alignment mark detection means, and a detection by the sample expansion / contraction measurement mark detection means. An exposure / drawing apparatus, comprising: a drawing control unit configured to calculate an expansion / contraction correction amount of the sample from a result and control the drawing unit based on the calculated position correction amount and expansion / contraction correction amount. 2. The exposure drawing apparatus according to claim 1, wherein the sample expansion / contraction measurement mark is a mark used for performing rough alignment of the sample. 3. The exposure drawing apparatus according to claim 1, wherein the sample expansion / contraction measurement mark is at least a part of the alignment mark. 4. The exposure / drawing apparatus according to claim 1, wherein the sample is a semiconductor substrate. 5. A step of: (1) detecting a position of a positioning mark formed on a sample; and (2) calculating a position correction amount of the sample from a detection result of the position of the positioning mark. A step of performing drawing based on the position correction amount;
(3) detecting the position of the sample expansion / contraction measurement mark formed on the sample at predetermined intervals; and (4) calculating the expansion / contraction correction amount of the sample from the detection result of the position of the sample expansion / contraction measurement mark. Calculating, drawing based on the expansion / contraction correction amount, and repeating at predetermined intervals until drawing is completed. 6. A step of: (1) detecting a position of a sample mark formed on a sample to perform coarse alignment; and (2) detecting a position of a positioning mark formed on the sample. (3) calculating the position correction amount of the sample from the detection result of the position of the alignment mark, and performing drawing based on the position correction amount; and (4) at predetermined intervals,
Detecting the position of the sample mark; and (5) calculating the amount of expansion / contraction correction of the sample from the detection result of the position of the sample mark, performing drawing based on the amount of expansion / contraction correction, and ending the drawing. A step of repeating at predetermined intervals, comprising: 7. The exposure drawing method according to claim 5, wherein the sample is a semiconductor substrate. 8. A drawing process for drawing a pattern on a sample by a drawing unit; a positioning mark detection process for detecting a position of a positioning mark formed on the sample; and a sample formed on the sample. A sample expansion / contraction measurement mark detection process for detecting the position of the expansion / contraction measurement mark at predetermined intervals, and calculating the position correction amount of the sample from the detection result of the alignment mark, and a detection result of the sample expansion / contraction measurement mark And a drawing control process of controlling the drawing unit based on the calculated position correction amount and the calculated expansion / contraction correction amount, and a program for causing a computer to execute the drawing control process. 9. The recording medium according to claim 8, wherein said sample is a semiconductor substrate.