JP2962383B2 - Diversity receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver used in a radio communication system for performing synchronous digital communication.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional diversity receiving apparatus shown in, for example, "Basics of Mobile Communication" (edited by Yoshihisa Okumura and Masaaki Shinji, edited by the Institute of Electronics, Information and Communication Engineers, issued October 1, 1986). It is. In the figure, reference numerals 11 and 12 denote two-system receiving antennas which are spatially separated from each other.
21 and 22 are receivers prepared corresponding to the respective receiving antennas 11 and 12 and demodulating the demodulated data and the demodulated clock from the power induced in the respective receiving antennas 11 and 12. A level comparator 3 compares the reception levels of the receivers 21 and 22 and outputs a selection signal based on the comparison result, and 4 receives the selection signal from the level comparator 3 and receives the selection signal. This is a selection switch for selecting the demodulated data and the demodulated clock of the higher reception level among 11 and 12. Reference numeral 5 denotes a clock generation circuit that generates a reproduction clock and a system clock based on the demodulated clock selected by the selection switch 4.

Next, the operation will be described. The receiving antennas 11 and 1 are transmitted by radio waves radiated into the space from the transmitting side.
2 is transmitted to the corresponding receiver 21 or 2
The demodulated data and the demodulated clock are input to the selection switch 4 from the receivers 21 and 22, respectively. At this time, the level comparator 3 captures and compares the reception levels of the receivers 21 and 22, detects the receiver 21 or 22 having the higher reception level, and detects the demodulated data and the demodulated data from the receiver 21 or 22. A selection signal for selecting a demodulation clock is sent to the selection switch 4.
The selection switch 4 performs a switching operation in accordance with the received selection signal, outputs demodulated data from the receiver 21 or 22 having a high reception level as selection data,
The demodulated clock from the receiver 21 or 22 is input to the clock generation circuit 5. The clock generation circuit 5 generates a signal based on the demodulated clock selected by the selection switch 4.
Generate a reproduction clock and a system clock. These clocks are synchronized with the clock on the transmission side, and the reception side performs data reproduction and system operation in synchronization with them.

FIGS. 6A and 6B are explanatory diagrams showing the waveforms of the respective parts at that time. FIG. 6A shows the selection signal output from the level comparator 3 and FIG. 6B shows the selection signal output from the receiver 21. FIG. 4C shows a demodulated clock output from the receiver 22, and FIG. 4D shows a clock input to the clock generation circuit 5. As shown, the receiver 2
When the phase of the demodulated clock output from the receiver 1 is different from the phase of the demodulated clock output from the receiver 22, when the receiving system is switched by diversity, the clock generation circuit 5
6 changes in phase at the switching point of the selection signal as shown in FIG.
In the generation of the reproduction clock and the system clock. In addition, the reception levels of the receivers 21 and 22 fluctuate for each bit, and the switching of the reception system is performed frequently accordingly.

[0005]

Since the conventional diversity receiving apparatus is configured as described above, every time the receiving system is switched by the diversity, a phase jump occurs in the clock generating circuit 5, and the transmitting side and the receiving side are connected. There is a problem that it becomes difficult to synchronize the clock with the side, and it becomes difficult to reproduce data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a diversity receiving apparatus in which clocks on a transmitting side and a receiving side do not lose synchronization by switching a receiving system due to diversity. The purpose is to obtain.

[0007]

According to a first aspect of the present invention, there is provided a diversity receiving apparatus for selecting demodulated data from each receiving system in accordance with a receiving level of a receiver.
A demodulated clock from one receiving system is fixedly supplied to a clock generation circuit, and a reproduction clock and a system clock are generated based on the clock.

In the diversity receiving apparatus according to the present invention, the polarization plane of the receiving antenna is changed in each receiving system.

[0009]

According to the first aspect of the present invention, the clock generation circuit receives the fixed supply of the demodulation clock from one of the plurality of receivers and generates the reproduction clock and the system clock based on the supply of the demodulation clock. This prevents a phase jump in the clock generation circuit every time the receiving system is switched, and realizes a diversity receiving apparatus in which the clocks on the transmitting side and the receiving side do not lose synchronization when the receiving system is switched.

The diversity receiving apparatus according to the second aspect of the present invention realizes a diversity receiving apparatus having the effect of polarization diversity by using different polarization planes of the receiving antenna in each receiving system. .

[0011]

[Embodiment 1] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the invention described in claim 1. In the figure, 11 and 12 are receiving antennas, 21 and 22 are receivers, 3 is a level comparator,
Reference numeral 5 denotes a clock generation circuit, which is the same as or a part equivalent to the conventional one denoted by the same reference numeral in FIG. Reference numeral 6 denotes a selection switch different from the conventional switch denoted by reference numeral 4 in FIG. 5 in that selection and switching of only demodulated data of the receivers 11 and 12 are performed based on a selection signal from the level comparator 3. It is. Note that the clock generation circuit 5 includes one receiver (the receiver 21 in the illustrated example).
Is fixedly input.

Next, the operation will be described. The basic operation is the same as in the conventional case, and a description thereof will be omitted. 2A and 2B are explanatory diagrams showing waveforms of respective parts. FIG. 2A is a selection signal output from the level comparator 3 and FIG. 2B is input from the receiver 21 to the clock generation circuit 5. The clock is shown. When the selection switch 6 is switched by the selection signal shown in FIG. 2A, demodulated data from the receiver 21 or 22 having a high reception level is selected and output as selection data, so that the effect of diversity is impaired. There is no. However, the clock input to the clock generation circuit 5 is fixedly supplied from the receiver 21 as shown in FIG.
Even if the receiving system is switched by diversity, the phase does not change at the switching point of the selection signal. Therefore, even if the reception level in each of the receivers 21 and 22 changes for each bit and the reception system is frequently switched, the clock phase does not jump in the clock generation circuit 5 and the reproduction clock is not changed. And the generation of the system clock is performed normally.

Embodiment 2 FIG. In the first embodiment, the case where the number of the receiving systems is two has been described. However, as shown in FIG. 3, the number of the receiving systems may be N (N is an integer of 3 or more). In the figure, 11 to 1N are N-system receiving antennas, 21 to 2N are receivers prepared corresponding to the respective receiving antennas 11 to 1N, and 7 is the highest reception level among these receivers 21 to 2N. Is a selection switch for selecting the demodulated data from the one with the highest value in accordance with the selection signal from the level comparator 3. The other parts are the same as or similar to those given the same reference numerals in FIG. 1, and therefore description thereof is omitted. Also, the operation is substantially the same as that of the first embodiment shown in FIG.

Embodiment 3 FIG. Further, in each of the above embodiments, the case where the polarization planes of the reception antennas in each reception system are the same has been described, but each reception antenna may have a different polarization plane. FIG. 4 is a block diagram showing one embodiment of such an invention described in claim 2, and the same parts are denoted by the same reference numerals as in FIG. 1 and the description thereof is omitted. In the figure, reference numerals 81 and 82 denote receiving antennas having mutually different polarization planes. In this embodiment, the powers induced in the receiving antennas 81 and 82 having different polarization planes are demodulated by the receivers 21 and 22, and the demodulated data from the receiver 21 or 22 having a higher reception level is selected by the selection switch 6. In this case, the same effects as those of the above-described embodiments can be obtained, and the effect of polarization diversity can be obtained.

[0015]

As described above, according to the first aspect of the present invention, only the demodulated data is selected according to the reception level of each receiver, and the demodulated clock is selected from one of the plurality of receivers.
Fixedly supplied to the lock generating circuit, in <br/> the constructed as to perform generation of the playback clock and the system clock, every time the reception system is switched by diversity occurs in synchronization detection output The advantage that the phase jump does not occur in the clock generation circuit, the clock cycle between the transmitting side and the receiving side can be prevented from being out of cycle when the receiving system is switched, and the operation of the diversity receiving apparatus can be stabilized. There is.

According to the second aspect of the present invention, since the polarization plane of the receiving antenna is configured to be different in each receiving system, there is an effect that a diversity receiving apparatus having the effect of polarization diversity can be obtained. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing waveforms at various parts in the embodiment.

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a third embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating a conventional diversity receiving apparatus.

FIG. 6 is an explanatory diagram showing waveforms of respective parts.

[Explanation of symbols]

 11-1N receiving antenna 21-2N receiver 3 level comparator 5 clock generation circuit 6 selection switch 7 selection switch 81, 82 reception antenna

Continuation of the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04B 7/00 H04B 7/02-7/12 H04L 1/02-1/06

Claims (2)

(57) [Claims] Receive antennas 1. A plurality of systems, prior SL are provided in each receiving antenna corresponding, and a plurality of receiver unit you outputs demodulated data and demodulated clock demodulates the power induced in the receiving antenna, comparing the reception level before Symbol each receiver, and a level comparator for outputting a selection signal in synchronization with the demodulation clock, the highest demodulation of the receiver before Symbol level comparator receiving level based on the comparison result of the a selection switch for selecting data, said plurality of demodulated demodulated clock in one in the receiver is
A diversity receiving apparatus comprising: a clock input circuit which is fixedly input and generates a reproduction clock and a system clock based on the demodulated clock . 2. The diversity receiver according to claim 1, wherein the receiving antennas have different polarization planes, and the powers induced in the receiving antennas are demodulated by the respective receivers.