JP2964765B2 - Semiconductor integrated circuit using multilayer wiring layers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a layout method of a semiconductor integrated circuit such as a microprocessor or a digital signal processor in which a regular structure block including a bus wiring, an arithmetic unit and the like and its control circuit are integrated on the same chip.

[0002]

2. Description of the Related Art Advances in microfabrication technology for semiconductor integrated circuits have made it possible to integrate more elements on a single chip. Also, regarding the wiring technology of a semiconductor integrated circuit such as a microprocessor and a digital signal processor, the conventional wiring layer is only one layer, but two or three metal layers are now used for wiring. I have. For example, the 1991 IEE
EE International Solid-State Circuit Conference Digest of Technical Papers (1991 IEEE International Solid-State
A microprocessor laid out using three metal wiring layers is reported on pages 90 to 91 of Circuit Conference Digest of Papers).

[0003]

In the multilayer metal wiring technology of a semiconductor integrated circuit, electrical characteristics such as wiring capacitance and wiring resistance and physical characteristics such as minimum wiring width and minimum wiring pitch in each metal layer are different. . For this reason, in a semiconductor integrated circuit such as a microprocessor or a digital signal processor in which a regular structure block such as an arithmetic unit and a non-regular structure block (hereinafter referred to as a random block) such as a control circuit are integrated on the same chip, the area and delay are increased. In order to optimize the time, a layout method that considers the characteristics of each metal wiring layer is required. Therefore, an object of the present invention is to optimize a chip area and a delay time and minimize a layout man-hour in a semiconductor integrated circuit using a multilayer wiring technology in which a regular structure block and a random block are integrated on the same chip. It is to provide a layout method to be performed.

[0004]

A layout method of a semiconductor integrated circuit having three metal wiring layers including a regular structure block and a random block to achieve the above object will be described below. These three metal wiring layers are an uppermost layer (hereinafter, referred to as M3), an intermediate layer (hereinafter, referred to as M2), and a lowermost layer (hereinafter, referred to as M2).
M1).

First, a rule structure block is constructed by dividing a logical structure into cells (hereinafter, referred to as bit cells) that can be used repeatedly in bit units. In the bit cells, basically the same cells are arranged in the vertical direction from the 0th bit to the nth bit (hereinafter, referred to as Y direction). A one-dimensional array of the bit cells is arranged in a horizontal direction in which a bus such as an arithmetic unit runs (hereinafter, referred to as an X direction), and a regular structure block is laid out as a two-dimensional array of the bit cells as a whole. How to use the metal wiring layer,
M1 is used for the wiring inside the bit cell. M3 is used for a bus line connecting between bit cells. M2 is used for the control signal input from the random block to the bit cell.

On the other hand, a random block is laid out in units of gate-level cells (hereinafter, referred to as standard cells) such as AND, OR, inverter, and latch.
The standard cells are arranged in the X direction which is the same as the direction in which a bus such as a computing unit runs. A random block is formed by stacking a plurality of one-dimensional arrays of the standard cells in the Y direction. A wiring area is provided between the one-dimensional arrays of the standard cells. As a method of using the metal wiring layer in the random block, M1 is used for the wiring inside the standard cell. M1 and M3 are used in the X direction in the wiring between the standard cells. M2 in Y direction
Is used.

The connection wiring of the control signal between the regular structure block and the random block is the same as the wiring between the standard cells.
The direction uses M1 and M3, and the Y direction uses M2.

[0008]

The above means can be used for a metal wiring layer M of a semiconductor integrated circuit.
Effective use of different attributes of each layer of M1, M2 and M3 realizes an optimum chip area and delay time. Since M3 is at the top, the thickness of the layer can be made larger than M1 and M2, so that the electric resistance can be reduced. Further, by being at the top, the distance from the substrate is increased and the wiring capacitance can be reduced. For this reason, M3
Is useful for reducing the delay time. Since M2 is located between M1 and M3, it can be easily connected to M1 and M3 via one through hole. M1
Is located at the bottom, so that it is easy to connect to the polysilicon layer forming the gate of the transistor and the impurity layer forming the source / drain. In the rule structure block, since only M1 is used for the bit cell wiring, it is possible to run the M3 wiring (bus wiring) in any X direction above the bit cell, and to run the M2 wiring in any Y direction. It is possible to Thus, the area of the regular structure block can be minimized, and the control signal can be minimized accordingly. In the random block, since only M1 is used for the standard cell wiring, it is possible to run the M3 wiring (bus wiring) in any X direction above the standard cell, and to run the M2 wiring in any Y direction. It is possible to As a result, the area of the random block can be minimized, and accordingly, each signal can be minimized. A control signal connecting the regular structure block and the random block is wired in the Y direction using M2 in the regular structure block, and this direction matches the direction of the M2 wiring of the random block. For this reason, the change of the connection of the wiring layers when the control signal is connected between the two blocks is minimized, and the area and the speed loss of the inter-block region are eliminated. Other objects and features of the present invention will be apparent from the following examples.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the semiconductor integrated circuit of this embodiment, a 32-bit bus, an arithmetic unit connected thereto, and a control circuit for controlling the bus are integrated on a single chip. Three metal wiring layers are used for the internal wiring of this semiconductor integrated circuit. Top layer M3, middle layer M2, bottom layer M1
Of three layers.

FIG. 2 is a block diagram showing a part of the semiconductor integrated circuit. Hereinafter, each component will be described. 2
00 is an arithmetic and logic unit (hereinafter referred to as ALU) 20
4, 208 input buses (A bus) with a bus width of 32 bits. Reference numeral 201 denotes the other input bus (B bus) of the ALUs 204 and 208. The bus width is also 32 bits. Reference numeral 202 denotes one input selector of the ALU 204. 203 is the other input selector of the ALU 204. 204 is an arithmetic and logic unit (ALU). 2
Reference numeral 05 denotes an output latch of the ALU 204. 206 is
The bus driver outputs the value of the output latch 205 to the output bus 207. An output bus (C bus) 207 for the ALUs 204 and 208 has a bus width of 32 bits. Reference numeral 208 denotes another arithmetic and logic unit (ALU) connected to the bus. 209 is 202, 203, 20
This is a first operation block composed of 4, 205, and 206. 210 is a second operation block including the operation unit 208. Reference numeral 211 denotes a first control block including a circuit for generating the control signals 213 to 216 of the first operation block 209. Reference numeral 212 denotes a second control block including a circuit that generates a control signal of the second operation block 210. 213
Is a control signal for the input selectors 202 and 203. 2
Reference numeral 14 denotes a control signal for the ALU 204 and a type of operation. 215 is a control signal for the output latch 205. 216 is a control signal for the bus driver 206.
With the above configuration, the A bus, B bus, and C bus are physically long-distance wirings, and serve as critical paths in determining the operation speed of the semiconductor integrated circuit.

FIG. 1 shows a part of the layout of the semiconductor integrated circuit, showing the first control block 211 and the first arithmetic block 209 of FIG. That is, 15
0 is the layout of the first control block 211 in FIG. 2, and 151 is the layout of the first operation block 209. The first control block 150 is a random block. Gate-level standard cells 100 such as AND, OR, inverter, latch, etc. are arranged in the X direction, and this one-dimensional array is arranged in the Y direction from the first column to the nth column.
This X direction is the same as the direction in which the bus runs in the operation block. M1 is used for the wiring inside the standard cell 100. From the center of each standard cell 100, the input / output terminals 101 and 102 for this cell project at M2. 103,
Reference numeral 104 denotes a power supply Vcc line supplied to the standard cell,
M1 is used in the ND line. These are connected to transistors inside the standard cell. 103 by this M1,
104 is Vcc / GND in the Y direction wired by M2
The trunk lines 105 and 106 are connected. A wiring area is provided between the one-dimensional arrays of the standard cells. The wiring between the standard cells and the wiring between the control block and the operation block use M1 and M3 in the X direction, and use M2 in the Y direction. For example, 107 is an M2 wiring in the Y direction, 108 is an M1 wiring in the X direction, and 109 is an M3 wiring in the X direction. M3
The wiring can pass not only in the wiring area but also in the upper part of the standard cell. By allocating M1 and M3 to the wiring in the X direction in this way, the length of the first control block 150 in the Y direction can be minimized. When connecting wires in the X direction and the Y direction, through-holes are punched at the contact points.

The first operation block 151 is a rule structure block. The logical structure is divided into bit cells that can be used repeatedly in bit units. The bit cell 120 is a cell for constituting the input selector 202, and basically the same cell is arranged in the Y direction from the 0th bit to the 31st bit. However, cells of odd-numbered bits (eg, cell 121) are mirror-inverted in the Y direction. This is because the Vcc / GND line supplied to the bit cells adjacent in the Y direction is shared. 122, 12
3, 124, 125 are input selectors 203,
ALU 204, output latch 205, bus driver 206
Is a bit cell for configuring 133 and 134 are a power supply Vcc line and a ground GND line supplied to the bit cell, and M1 is used. These are connected to transistors inside the bit cell. 133 by this M1 wiring,
134 is Vcc / GND in the Y direction wired by M2
The trunk lines 105 and 106 are connected. M1 is used for the wiring inside the bit cell. 127 and 132 are A bus lines of the 0th bit and the 1st bit, respectively. 12
Reference numerals 8 and 131 denote B bus lines of the 0th bit and the 1st bit, respectively. 129 and 130 are the 0th bit,
This is the C bus wiring of the first bit. These cells 12
M3 is used for the bus wiring connecting between 1, 122, 123, 124 and 125. When connecting from the bus wiring to the gate and drain of the transistor in the lower bit cell, a through hole 126 is formed. Control signals 111 to 118 input from the first control block 150
Use M2. The control signals 111 to 114 correspond to the control signal 213 for the input selectors 202 and 203, and 115 to 116 are the control signals 214 and 117 for the ALU 204 and the control signal 2 for the output latch 205.
15, 118 are control signals 2 for the bus driver 206.
16 corresponds to 16.

[0013]

As described above, the following effects are produced by deciding the roles of the three metal wiring layers and laying them out. Since M3 is at the top, the thickness of the layer is M1, M2
Since the thickness can be increased, the electric resistance can be reduced. Further, by being at the top, the distance from the substrate is increased and the wiring capacitance can be reduced. Therefore, by using M3 for the bus wiring of the rule structure block, it is useful to reduce the delay time. Since M2 is located between M1 and M3, it can be easily connected to M1 and M3 via one through hole. Since M1 is at the bottom, it is easy to connect with the polysilicon layer forming the gate of the transistor and the impurity layer forming the source / drain. In the regular structure block, only M1 is used for the bit cell wiring, so that the M3 wiring (bus wiring) can run in any X direction above the bit cell, and the M2 wiring runs in any Y direction. It is possible. Thus, the area of the regular structure block can be minimized, and the control signal can be minimized accordingly. In the random block, since only M1 is used for the standard cell wiring, it is possible to run the M3 wiring (bus wiring) in any X direction above the standard cell, and to run the M2 wiring in any Y direction. It is possible to As a result, the area of the random block can be minimized, and accordingly, each signal can be minimized.
A control signal connecting the regular structure block and the random block is wired in the Y direction using M2 in the regular structure block, and this direction matches the direction of the M2 wiring of the random block. For this reason, the change of the connection of the wiring layers when the control signal is connected between the two blocks is minimized, and the area and the speed loss of the inter-block region are eliminated.

[Brief description of the drawings]

FIG. 1 is a layout configuration of a semiconductor integrated circuit using three metal wiring layers according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram of a portion corresponding to a layout configuration of the semiconductor integrated circuit of FIG. 1;

[Explanation of symbols]

100: standard cell, 107: Y-direction wiring (M2), 10
8 ... X-direction wiring (M1), 109 ... X-direction wiring (M
3), 111 to 118... Control signals (M
2) 127 to 132: bus wiring (M3), 201: input bus, 202: output bus, 209: arithmetic block, 2
11 Control block.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Susumu Narita 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Fumio Arakawa 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi, Ltd. In the Central Research Laboratory (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 H01L 27/04

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit in which three wiring layers of a lowermost layer, an intermediate layer, and an uppermost layer are used for wiring internal signals, wherein the semiconductor integrated circuit has a regular structure block having bus wiring on the same chip. A random block having a control circuit for controlling the rule structure block, wherein the rule structure block is configured by a two-dimensional array of bit cells, and the lowermost layer is used for wiring inside the bit cells. A top layer is used for the bus wiring, the intermediate layer is used for a control signal from the random block to the regular structure block, and the random block is configured by a plurality of one-dimensional arrays of standard cells; The one-dimensional array is arranged in parallel with the bus wiring of the regular structure block, and the lowermost layer is used for wiring inside the standard cell; In the wiring between the standard cells in the block and the regular structure block, the lowermost layer or the uppermost layer is used for wiring in the direction parallel to the one-dimensional array, and the wiring in the vertical direction to the one-dimensional array. A semiconductor integrated circuit using a multilayer wiring layer, wherein the intermediate layer is used. 2. The rule structure block is an operation block including an arithmetic logic unit, the random block is a control block for generating a control signal for controlling the operation block, and the semiconductor integrated circuit is a microprocessor. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a chip of a digital signal processor.