JP2968599B2 - Interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit, and more particularly to an interface circuit for multiplexing an auxiliary signal when converting a data sequence of a synchronous transmission network into a data sequence of wireless transmission.

At present, a synchronous transmission network SDH (Synchronous Dig) is used.
ital Hierarchy)
An example of an STM-1 frame as shown in FIG. 2 will be described, which is a SONET (Synchronous Optical Network).
When wirelessly transmitting a data sequence (corresponding to the STS-3 frame in the above) and a data sequence of the multi-level QAM method,
Since the transmission speed on the radio line side is higher than the transmission speed on the transmission network side, speed conversion is required. In addition, since various auxiliary signals are transmitted to the receiving side, this auxiliary signal is multiplexed with the speed-converted data. Need to be

[0003]

2. Description of the Related Art FIG. 4A shows a transmitting side of a conventional interface circuit as described above, and FIG. 4B shows a receiving side thereof.

First, an interface circuit on the transmission side shown in FIG. 1A includes, for example, a speed converter 41 composed of an elastic memory, a write counter and a read counter, and outputs data from the speed converter 41. A multiplexing unit 42 for multiplexing the auxiliary signal, a speed converting unit 41 and a multiplexing unit 4
And a timing generation section 43 for providing a timing signal to the P.2.

In operation, first, data of an STM-1 frame from the synchronous transmission network is input to the speed converter 41. This STM-1 frame IFD is shown in FIG.
As shown in FIG. 7, one frame is composed of nine subframes 1row to 9row, and each subframe is composed of an overhead part O for a 9-bit maintenance signal indicated by hatching and communication data of 261 bits. And a payload section P for the PDP, and is composed of 2430 bits in total.

[0006] The data of such an STM-1 frame IFD is written in the speed converter 41 by a write clock WCK.
And the read clock RCK, which has a higher speed than the write clock WCK, is converted by the speed converter 41 into the speed on the wireless line side. At this time, the timing generation section 43 receives the read clock RCK, generates an inhibit pulse IP for inhibiting the read clock RCK, and supplies the generated inhibit pulse IP to the speed conversion section 41, so that the parallel clock signal is output as shown in FIG. A 1-bit empty slot S is formed in each subframe of the bit output frame data RFD.

[0007] The frame data RFD output from the speed conversion section 41 in this manner is output to the multiplexing section 42 by the multiplexing section 42.
In accordance with the timing signal from the timing generator 43, an auxiliary signal is inserted into the empty slot S and multiplexed to obtain wireless transmission data.

On the receiving side receiving such radio transmission data RFD, as shown in FIG. 4 (b), the received data is converted into an auxiliary signal of an empty slot S in accordance with a timing signal from a timing generating section 46 in a separating section 44. The 8-bit parallel data other than the auxiliary signal is separated by the speed converter 45.
, The write clock WCK and the read clock RC
K and the timing signal from the timing generator 46, the STM-1 frame data I returned to the speed of the synchronous transmission network and from which the empty slots S generated on the transmitting side have been removed.
It will be output as FD.

[0009]

As described above, in the conventional interface circuit, at the transmission side, FIG.
Since the 1-bit empty slot S is added as shown in (1), the format of the STM-1 frame changes, and the transmission speed must be increased in order to maintain the same frame period for these additional bits. Thus, there is a problem that the occupied band is widened.

Accordingly, the present invention realizes an interface circuit capable of multiplexing auxiliary signals without changing a predetermined frame format of input data such as STM-1 frame data and without increasing a transmission speed. The purpose is to:

[0011]

FIG. 1 (a) shows in principle the configuration of the transmission side of an interface circuit according to the present invention. In the present invention, in order to solve the above-mentioned problems, input data is A speed conversion unit 1 for speed conversion and a timing signal for specifying an empty slot of a predetermined format of output data of the speed conversion unit 1 are read by a read clock RC of the speed conversion unit 1.
A timing generator 2 which generates a signal based on K, and a multiplexer 3 which inserts an auxiliary signal into the empty slot of the output data of the speed converter 1 using the timing signal and transmits the auxiliary signal.

FIG. 1B shows in principle the configuration of the receiving side of the interface circuit according to the present invention. In the present invention, in order to solve the above-mentioned problem, an empty space in a predetermined format of received data is provided. A timing generator 4 for generating a timing signal for designating a slot; a separator 5 for separating an auxiliary signal in the empty slot from the received data by the timing signal; A restoring unit 6 for returning a signal of an empty slot to an original predetermined value by the timing signal; and a speed converting unit 7 for speed-converting received data output from the restoring unit 6; The signal is generated based on the write clock WCK of the speed converter 7. The interface circuit according to the present invention is shown in FIG.
The above problem can be solved even with only the configuration on the receiving side in (b).
Can be done.

[0013]

First, in the STM-1 frame as described above, as shown in FIG. 2, an overhead section (FIG. 5A)
A section overhead S) for exchanging a control signal between the terminal station and the intermediate relay station further comprises a section O) shown in FIG.
OH and a line overhead LOH for exchanging control signals between the terminal stations, and each one byte A1, A2, B1, B2, C1, D1 to D1 shown in FIG.
2, E1, E2, F1, H1-1-3, H2-1-3,
H3-1 to 3, K1, K2, Z1, and Z2 have already been standardized for use, but the hatched portion is usually "1".
Is a slot to be set, and its use is not standardized as a domestic specification.

As described above, in a predetermined frame format such as an STM-1 frame, there is a slot whose specification is not determined. If this slot is used, it is not necessary to provide an additional bit as in the conventional case.

Therefore, on the transmitting side of the interface circuit shown in FIG. 1 (a), when the speed converter 1 converts the speed of the input data, the transmission clock on the transmitting side (for example, the radio side) is read by the read clock RCK. The timing generator 2 supplies a timing signal designating an empty slot in a predetermined format to the multiplexer 3 so that the multiplexer 3 can insert an auxiliary signal into the empty slot to generate transmission data. .

On the receiving side, as shown in FIG. 2B, the timing generator 4 inserts an auxiliary signal at the transmission rate (on the radio side) of the write clock WCK of the speed converter 7. By providing a timing signal designating a slot to the separation unit 5, the separation unit 5 separates the auxiliary signal from the received data, and the restoration unit 6 converts the auxiliary signal slot into the original slot based on the timing signal from the timing generation unit 4. By returning to a predetermined value and giving it to the speed conversion unit 7,
The speed converter 7 outputs the input data shown in FIG.

In this way, the auxiliary signal can be transmitted without providing a new slot, and the predetermined frame data can be transmitted without error.

[0018]

3 (a) and 3 (b) show an embodiment of the interface circuit according to the present invention shown in FIGS. 1 (a) and 1 (b), respectively. On the transmitting side, a counter is used as the timing generator 2 and a frame pulse FP corresponding to the input data supplied to the speed converter 1 (this is the first A1 byte in the format shown in FIG. The read clock RCK of the speed conversion unit 1 is counted based on the corresponding timing, and when the count value reaches a predetermined count value, a timing signal designating an empty slot (the shaded portion in the figure) is output to the multiplexing unit 3. Give to 1
One auxiliary signal is inserted into one subframe.

On the receiving side shown in FIG. 3B, the timing generator 4 is also constituted by a counter, and the restoration unit 6 to which the timing signal is applied is constituted by an OR gate.

That is, based on the frame pulse FP of the received data, the counter 4 sets the write clock W
CK is counted, and when a predetermined count value in each subframe described with reference to FIG. 3A is reached, the auxiliary signal is separated by the separation unit 5 and the OR gate 6 inserts the auxiliary signal into the portion where the auxiliary signal was inserted. Set “1” and Figure 2
Return to the original frame state (domestic specification) shown in (b). As a result, a desired function can be achieved without any problem as an STM-1 frame.

[0021]

As described above, according to the interface circuit of the present invention, an auxiliary signal is multiplexed on an empty slot in a predetermined format on the transmitting side, the auxiliary signal is extracted on the receiving side, and the Since the configuration is such that the original predetermined value is returned, the auxiliary signal can be transmitted in the format of the input data without adding a new slot and therefore without increasing the transmission speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a principle configuration of an interface circuit according to the present invention.

FIG. 2 is a diagram showing an STM-1 frame format of a synchronous transmission network used for the interface circuit according to the present invention.

FIG. 3 is a block diagram showing an embodiment of an interface circuit according to the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram showing a change in frame data in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 speed conversion unit 2 timing generation unit 3 multiplexing unit 4 timing generation unit 5 separation unit 6 restoration unit 7 speed conversion unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/00

Claims (2)

(57) [Claims] 1. A speed converter for converting the speed of input data.
(1) and a timing signal specifying an empty slot of a predetermined format of the output data of the speed conversion unit (1).
A timing generator (2) generated based on the read clock (RCK) of (1), and a multiplex for transmitting an auxiliary signal by inserting an auxiliary signal into the empty slot of the output data of the speed converter (1) by the timing signal. The transmitting side is provided with the converting section (3) and, and an empty slot in a predetermined format of the received data is specified.
Timing generator (4) that generates a timing signal
And the empty slot from the received data by the timing signal.
A separating unit (5) for separating an auxiliary signal in the data, and an empty slot in the received data from the separating unit (5).
A restoration unit for returning a signal to an original predetermined value by the timing signal
(6) and speed conversion of the received data output from the restoration unit (6)
A speed conversion unit (7) is provided on the reception side, and the timing generation unit (4) on the reception side
Timing signal of the receiving side
An interface circuit generated based on a lock (WCK) . 2. A timing generator (4) for generating a timing signal designating an empty slot in a predetermined format of received data, and a separating unit for separating an auxiliary signal in the empty slot from the received data based on the timing signal. (5) a restoring unit for returning the signal of the empty slot in the received data from the separating unit (5) to an original predetermined value by the timing signal.
(6), and a speed conversion unit (7) for speed-converting the received data output from the restoration unit (6), and the timing signal from the timing generation unit (4) is used for the speed conversion unit (7 ) Is generated on the basis of the write clock (WCK).