JP2969735B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a memory cell structure in which the area of a bipolar memory cell is reduced.

[Conventional technology]

Conventionally, a bipolar memory cell having a circuit configuration shown in FIG. 4 has been proposed. This bipolar memory cell is a cross-coupled PNP with a horizontal PNP transistor as a load.
This is an N-type memory cell, which includes horizontal PNP transistors Q1 and Q2 as loads and NPN transistors Q3 and Q4. These NPN transistors Q3 and Q4 have their base and collector cross-connected to each other.

In this memory cell, as shown in the top view of FIG. 5, the connection of the emitters E of the PNP transistors Q1 and Q2 is made by the first layer aluminum wiring 10a and the NPN transistor Q1.
3, the connection of the writing / reading emitter E1 of Q4 is made by the first layer aluminum wiring 10b, and the connection of the holding emitter E2 of the NPN transistors Q3, Q4 is made by the first layer aluminum wiring 10c.
Thus, the connection between the collector and the base of the NPN transistors Q3 and Q4 is made by the first layer aluminum wiring 10d.
A first layer aluminum wiring 10a connected to the emitters of the PNP transistors Q1 and Q2 through the through hole 11;
The first-layer aluminum wiring 10c connected to the holding emitter E2 of the transistors Q3 and Q4 is connected to the second-layer aluminum wiring 12, respectively. The first-layer aluminum wiring 10b forms a bit line, and the second-layer aluminum wiring 12 forms a word line.

In FIG. 5, reference numeral 2 denotes a groove separation region.

[Problems to be solved by the invention]

Incidentally, miniaturization of this type of memory cell structure is important not only for improving the integration degree of the memory LSI, but also for improving the operation speed by reducing the parasitic capacitance in the cell. However, in the conventional wiring structure described above, even if elements such as transistors can be miniaturized, it is difficult to miniaturize the wiring structure itself for the following two reasons.

First, in order to obtain high-speed operation with a memory LSI, a memory cell is driven by a large read / write current,
It is necessary to charge and discharge each node of the cell array and the sense circuit at high speed. However, due to problems such as electromigration, it is difficult to flow a large read / write current through the miniaturized wiring.

Secondly, when driving a memory cell located far from the driver circuit, it is necessary to lower the wiring resistance in order to avoid a potential drop due to a large current, but it is also difficult to satisfy both the fine wiring and the low resistance at the same time. It is.

For the reasons described above, the wiring passing through the cell requires a certain wiring width, which hinders miniaturization. For example,
The above-described cross-coupled PNPN memory cell is characterized in that the cell area can be reduced. However, in the above-described wiring structure including the first and second layers of aluminum wiring, it is necessary to secure a wiring area. The cell area is restricted, which hinders high integration.

An object of the present invention is to provide a semiconductor device having a memory cell structure capable of high-speed operation by reducing the resistance and miniaturization of wiring.

[Means for solving the problem]

In the semiconductor device of the present invention, a conductive portion made of a metal conductor is formed in a part of the trench isolation region that defines a plurality of element regions,
Impurity regions of different conductivity types of adjacent elements are connected to each other via this conductive portion.

For example, a PNPN element in which a PNP transistor and an NPN transistor are integrated in each element region is formed, and a conductive region provided in a part of the trench isolation region is opposed to a collector region of one conductivity type of an adjacent PNPN element. A cross-coupled PNPN memory cell is formed by cross-connecting the conductive type base region.

Here, the conductive portion is formed by etching away a part of the insulating material forming the groove separation region and burying a metal conductive material in this portion.

[Action]

ADVANTAGE OF THE INVENTION According to this invention, the wiring for connecting an image element is unnecessary by connecting an adjacent element mutually via the conductive part provided in the groove isolation | separation area | region, and high integration of an element is attained.

For example, in a cross-coupled memory cell, the base region and the collector region of the adjacent PNPN element are electrically connected to each other via a conductive portion provided in the trench isolation region, whereby the first region is formed.
A part of the layered aluminum wiring is omitted, and the wiring area is reduced to enable high integration of memory cells.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a top view of one embodiment of the present invention, in which the present invention is applied to the cross-coupled PNPN memory cell shown in FIG. FIG. 2 is an enlarged sectional view taken along line AA of FIG. 1, and FIG. 3 (c) is an enlarged sectional view taken along line BB of FIG.

In these figures, an element region is defined by a trench isolation region 2 in a p-type semiconductor substrate 1, and an n ⁺ buried region 3 and an n ^- region 4 are formed in this element region. This the n ^- part of the area 4 forms the n ⁺ collector region 5 connected to the n ⁺ buried region 3. The n ^- region 4 includes a p base region 6.
And ap ⁺ region 7 are formed, and an n ⁺ emitter region 8 is formed in the p base region 6.

Then, an insulating film 9 is formed on the front surface, a contact hole is opened, and first-layer aluminum wirings 10a to 10c are formed to make contact with the p ⁺ region 7 and the n ⁺ emitter region 8. .

As a result, the load PNP transistors Q1 and Q1 shown in FIG.
Q2 and NPN transistors Q3 and Q4 are integrally formed.

On the other hand, part of the groove separation region 2 is shown in FIG.
Is configured to have conductivity, and the conductive portion 20
The n ⁺ collector region 5 and the p base region 6 are directly connected.

That is, the trench isolation region 2 has a silicon oxide film 21 and a silicon nitride film on the inner surface of the deep trench formed in the p-type semiconductor substrate 1.
22 are sequentially formed, and a borophossilicate glass (BPSG) 23 is buried in the groove to insulate the element region. Here, the silicon oxide film 21, the silicon nitride film 22 and the BPSG 23 on the upper portion of the trench are removed, and instead, a metal 24 such as CVD-tungsten is filled, so that the n ⁺ Region 5 and p base region 6
Are short-circuited.

Then, the first-layer aluminum wiring 10c connects the holding emitters E2 of the NPN transistors Q3 and Q4 to each other, and the first-layer aluminum wiring 10b connects the reading emitter E1 to form a bit line. Further, the emitters E of the PNP transistors Q1 and Q2 are connected to each other by the first layer aluminum wiring 10a. On the other hand, the first-layer aluminum wiring 10b connected to the hold emitter E2 and the first-layer aluminum wiring 10a connected to the p ⁺ region 7 are connected to the second-layer aluminum wiring 12 through the through hole 11 to connect the word line. Form. Thereby, a cross-coupled PNPN type memory cell is formed.

Here, a method of manufacturing the conductive portion 20 will be described with reference to FIGS.

First, as shown in FIG. 3A, a narrow and deep groove is formed in the p-type semiconductor substrate 1 by an etching method, and then the inner surface of the groove is oxidized to form a thin silicon oxide film 21. The silicon nitride film 22 is formed thin. Then, BPSG23 is buried to fill the inside of the groove. A silicon oxide film 25 is formed on the surface of the BPSG 23.

Note that the p base region 6 is formed with ap ⁺ contact region 6A in contact with the groove isolation region 2 in order to make good connection with the n ⁺ collector region 5.

Next, as shown in FIG. 3 (b), after a photoresist 26 is formed on the surface by coating, this is selectively etched by a photographic method to selectively open only the groove. Then, using the photoresist 26 as a mask, the silicon oxide film 25 above the groove is removed by dry etching, the BPSG 23 is subsequently removed by wet etching, and the silicon nitride film on the inner surface of the groove is further etched by dry etching. 22, The silicon oxide film 21 is removed.

Note that the etching depth at this time is formed shallower than the p ⁺ contact region 6A.

Thereafter, as shown in FIG. 3 (c), after removing the photoresist 26, a CVD tungsten 24 is buried in the groove. As this method, if a selective CVD method using SiH ₄ and WF ₆ is used, tungsten growth starts from an exposed portion of the silicon on the side surface of the trench, and the trench can be buried. Thereafter, an insulating film (not shown) is grown on the tungsten 24 at a low temperature (about 400 ° C.).

The conductive portion 20 thus formed connects the n ⁺ collector region 5 and the p base region 6 directly, so that the first layer aluminum wiring 10d conventionally connecting them (see FIG. 5).
However, it is unnecessary in this part. As a result, the wiring space in this portion can be reduced, and the layout of the other first-layer aluminum wirings 10a to 10c can be given a degree of freedom, thereby reducing the cell area which is a characteristic of the cross-coupled PNPN memory cell. Can be further integrated without being limited by aluminum wiring.

〔The invention's effect〕

As described above, according to the present invention, the adjacent elements are connected to each other via the conductive portion formed of the metal conductor provided in the groove isolation region, so that wiring for connecting the two elements is unnecessary, and the height of the elements is reduced. Integration becomes possible. Therefore, even when a cross-coupled memory cell is configured, the collector region of one conductivity type and the base region of the opposite conductivity type are electrically connected to each other via the conductive portion provided in the trench isolation region. By doing so, the first layer aluminum wiring can be partially omitted, the wiring area can be reduced, and high integration of the memory cell can be realized without being limited by the wiring area.

In this case, since the conductive portion is a metal conductor, even if the collector region and the base region of different conductivity types are connected to each other, impurities of different conductivity types are mutually diffused by a subsequent heat treatment to form a PN diode. No problem arises.

[Brief description of the drawings]

1 is a top view of one embodiment of the present invention, FIG. 2 is an enlarged sectional view taken along line AA of FIG. 1, and FIG. 3 is an enlarged sectional view taken along line BB of FIG. FIGS. 3 (a) to 3 (c) are views showing the manufacturing method in the order of steps, FIG. 4 is a circuit diagram of a cross-coupled PNPN memory cell, and FIG. 5 is a top view of a conventional memory cell. 1 ... p-type semiconductor substrate, 2 ... groove separation region, 3 ... n ⁺ buried region, 4 ... n ^- region, 5 ... n ⁺ collector region, 6 ...
p base region, 6A ... p ⁺ contact region, 7 ... p ⁺ region, 8 ... n ⁺ emitter region, 9 ... insulating film, 10a-10d ...
... First layer aluminum wiring, 11 ... Through hole, 12 ...
... First layer aluminum wiring, 20 ... Conducting part, 21 ... Silicon oxide film, 22 ... Silicon nitride film, 23 ... BPSG, 24 ...
... CVD-tungsten, 25 ... silicon oxide film, 26 ...
Photoresist.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 27/102 H01L 27/082 H01L 21/8229 H01L 21/8228 H01L 21/3205

Claims (3)

(57) [Claims] 1. A semiconductor device comprising a plurality of element regions defined by groove isolation regions formed in a semiconductor substrate, and each element region includes an element. A semiconductor device comprising: a conductive portion made of a conductive material; and impurity regions of different conductivity types of adjacent elements connected to each other via the conductive portion. 2. A PNP transistor and an NPN transistor are provided in each element region.
Forming a PNPN element in which a transistor is integrated, and adjacent PNPN via the conductive portion provided in a part of the trench isolation region;
2. The semiconductor device according to claim 1, wherein a cross-coupled PNPN memory cell is formed by cross-connecting a collector region of one conductivity type of the element and a base region of the opposite conductivity type. 3. The conductive part according to claim 1, wherein a part of the insulating material constituting the groove separation region is removed by etching, and a metal conductive material is buried in this part. Semiconductor device.