JP2969896B2 - Data write control method for RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a RAM data write control method, which aims to provide a RAM data write control method capable of writing data only to an arbitrary bit of a specified address. Comprising an address generating means for generating a read address, and data control means for selecting write data, wherein data read from RAM by the data control means,
By selecting any of the new write data and writing the data to the RAM, data writing of only an arbitrary bit is performed.

[Industrial applications]

 The present invention relates to a data write control method for a RAM.

RAM (Random Access Memory) is a storage element that can be read and written as needed, which is widely used in electronic devices and communication devices.

In recent years, as the functions of electronic devices and communication devices have become more sophisticated, the storage capacity required for the devices has increased, and the number of RAMs used has also increased.

Such electronic devices and communication devices have been reduced in size and power consumption,
Improvements in reliability are required, and it is necessary to minimize the number of RAMs used.

[Conventional technology]

FIG. 4 is a diagram for explaining a conventional example, and FIG. 5 is a diagram for explaining an example of write data to a RAM.

In the conventional example shown in FIG. 4, 11 to 1n are RAMs, and 22 is an address counter.

It is assumed that the RAM in the figure can write data of n bits (for example, 8 bits) with one address.

As shown in FIG. 5, data A is written to the first bit of address “i”, data B is written to the second bit of address “j”, and data C is written to the third bit of address “k”. In the case where the data of the bits other than the data to be written are kept in the previous state, in FIG. The data B is written to the second bit of the address "j" in the second RAM 12, and similarly, the data of the n-th bit is written to the RAM 1n.

[Problems to be solved by the invention]

As in the above-described conventional example, for example, only data A is written to the first bit of address "i" of one RAM 11, only data B is written to the second bit of address "j", and the third bit of address "k" is written. Even if it is attempted to write data to a different bit number of each address so that only data C is written to one RAM, there is only one write enable WE for one RAM, so data can be written independently for each bit. Impossible. (Data other than the bit to be written is also rewritten).

Therefore, RAMs 11 to 1n are required for the number n of bits, and the installation space and power consumption of the device are increased.

Therefore, even if the bit numbers for writing data are different, the number of RAMs used is reduced by writing data to an arbitrary bit of one RAM under the control of one write enable WE.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data write control method for a RAM that can write data only to an arbitrary bit of a specified address.

[Means for solving the problem]

 FIG. 1 is a block diagram illustrating the principle of the present invention.

In the principle block diagram of the present invention shown in FIG. 1, 10 is a RAM for writing and reading data, 20 is an address generating means for generating a write and read address, and 30 is data for selecting write data. Control means, data read from the RAM 10 by the data control means 30,
By selecting any of the new write data and writing the data to the RAM 10, this is a means for solving this problem.

(Operation)

When rewriting only data of an arbitrary bit of a specified address in the RAM 10, one address is divided into two, a read / write cycle is provided, and data is written after reading data of all bits of the specified address. I do.

At this time, new data is selected as a bit to which new data is to be written by the data control means 30, and old data read from the same bit is selected as a bit to which new data is not to be written, and the data is written to the RAM 10.

Therefore, data write control to an arbitrary bit of a specified address of the RAM 10 can be performed by controlling one write enable WE.

〔Example〕

Hereinafter, the gist of the present invention will be specifically described with reference to the embodiments shown in FIGS.

FIG. 2 is a diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a time chart of the embodiment of the present invention. The same reference numerals indicate the same objects throughout the drawings.

The embodiment of the present invention shown in FIG.
A RAM 10 for reading, a control unit 21 for generating a selection signal for selecting write data for each bit, an address counter 22 for generating an address according to an instruction from the control unit 21, a latch circuit 30A for latching data read from the RAM 10; Selector for selecting new write data or read data as write data for each bit (indicated as SEL in the figure) 31
1 to 3n.

 The operation will be described with reference to the time chart of FIG.

This is the address where data is read and written.

 Light Navel WE.

~ Indicates new write data.

The first bit data, the second bit data, and the third bit data are indicated as.

Also, only the data in the shaded part is new data.
Write to RAM10.

~ 1st bit data read from RAM10,
The second bit data and the third bit data.

To write data selected by the selectors 31 to 3n.

Here, the first and second bits of the address “1” select and output externally-written new write data,
In the third bit, old data read from the RAM 10 and latched by the latch circuit 30A is selected and transmitted.

The same operation is performed for the address “2” and below, and the data in the shaded portion is written as new data,
For the portions not shaded, the data read from the RAM 10 is written as it is.

With the above configuration, when the data to be written is n bits, the number of RAMs to be used can be reduced to 1 / n as compared with the conventional example.

〔The invention's effect〕

According to the present invention as described above, under the control of one write enable WE, by independently rewriting only the data of an arbitrary bit at a specified address, the data of the RAM that can reduce the number of RAMs used can be reduced. A write control method can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a time chart of the embodiment of the present invention, and FIG. FIG. 5 is a diagram for explaining an example, and FIG. 5 is a diagram for explaining an example of write data to the RAM. In the figure, 10 and 11 to 1n are RAMs, 20 is an address generation means, 21 is a control unit, 22 is an address counter, 30 is a data control means, 30A is a latch circuit, and 31 to 3n are selectors.

Claims (1)

(57) [Claims] 1. A data write control method for a RAM (10), comprising: an address generating means (20) for generating a write / read address; and a data control means (30) for selecting write data. By selecting either the data read from the RAM (10) or the new write data by the control means (30) and writing the data to the RAM (10), it is possible to perform data writing of only arbitrary bits. Feature
RAM data write control method.