JP2970540B2 - Duty correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty correction circuit.

[0002]

2. Description of the Related Art In a magnetic recording apparatus for recording digital signals on a magnetic disk, the duty ratio of a signal or a synchronous clock at the time of reproduction is always constant irrespective of the relative distance between the center of the magnetic disk and the magnetic head. As described above, there is provided a duty correction circuit for correcting the duty ratio of the digital signal or the synchronous clock before recording.

FIG. 5 is a circuit diagram of a conventional duty correction circuit, and FIGS. 6 and 7 are timing charts thereof. The delay circuit 11 raises the input signal p at the time of rising τ ₁ (nS),
The output is delayed by τ ₂ (nS) at the time of falling. The OR circuit 12 outputs the input signal p and the output signal m of the delay circuit 11
And outputs the operation result as an output signal n. In this case, the duty is τ ₂
The output signal n extended by the length is obtained.

In this example, the case where the correction for increasing the duty is performed is shown. However, the correction for reducing the duty can be realized by replacing the logical sum circuit 12 with a logical product circuit. FIG. 7 shows a timing chart at this time. In this case, an output signal n corrected so that the duty is reduced by τ ₁ from the input signal p is obtained.

[0005]

In the conventional duty correction circuit described above, when increasing the duty, the duty is reduced only by the delay time at the fall of the delay circuit, and when the duty is reduced, the duty is limited only by the delay time at the rise of the delay circuit. There was a problem that it could not be used for correction. That is, even if a delay circuit having different rise delay time and fall delay time is used, the rise delay time cannot be used for duty correction when the duty is increased, and the fall delay time is used when the duty is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a duty correction circuit capable of finely setting a duty correction width by using both delay times at rising and falling times for duty correction regardless of whether the duty is increased or reduced. It is to be.

[0007]

In order to achieve the above object, a duty correction circuit according to the present invention comprises one or more first delay circuits for delaying an input signal by different times at rising and falling, and A first gate circuit that receives the output signal of the delay circuit and the first selection signal and outputs the output signal of the first delay circuit when the first selection signal is active, and logically inverts the input signal A first inverting circuit;
One or more second delay circuits for delaying the output signal of the inverting circuit by different times at the rising and falling edges, a second inverting circuit for logically inverting the output signal of the second delay circuit, and a second inverting circuit A second output circuit that receives an output signal of the circuit and a second selection signal that becomes active when the first selection signal is inactive, and that outputs an output signal of the second inversion circuit when the second selection signal is active; Two gate circuits and the first gate circuit.
Or the first selection signal output from the first gate circuit by the active selection signal of the second selection signals.
And a third gate circuit that performs a logical sum operation or an AND operation of the output signal of the delay circuit or the output signal of the second inversion circuit output from the second gate circuit and the input signal.

According to the present invention, a delay circuit having different rise delay time and fall delay time is used, and both delay times are used for duty correction.

Therefore, the correction width of the duty correction circuit can be set finely.

According to an embodiment of the present invention, the third gate circuit outputs the first signal output from the first gate circuit when the input signal and the first selection signal are active.
A fourth gate circuit for performing a logical sum operation with an output signal of the delay circuit of the third embodiment; an output of the fourth gate circuit;
And a fifth gate circuit that performs a logical OR operation with the output signal of the second inversion circuit output from the second gate circuit when the selection signal is active. In this embodiment, a correction for increasing the duty is performed.

According to another embodiment of the present invention, the third
A first delay circuit output from the first gate circuit when the first selection signal is active, and a second gate circuit when the second selection signal is active. A sixth gate circuit for performing a logical sum operation on an output signal of the second inverting circuit output from the circuit, and a seventh gate circuit for performing a logical AND operation on an output of the sixth gate circuit and the input signal It is composed of a gate circuit. In this embodiment, a correction for reducing the duty is performed.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a duty correction circuit according to a first embodiment of the present invention, and FIGS. 2 and 3 are timing charts showing the operation thereof.

The duty correction circuit according to the present embodiment comprises inversion circuits 4 and 6, delay circuits 1 and 5, and AND circuits 2 and 7.
And OR circuits 3 and 8. Here, the delay circuits 1 and 5 convert the input signals into τ ₁ (n
S), the output is delayed by τ ₂ (nS) at the time of falling.

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS.

First, the selection signal b is at a high level (hereinafter referred to as H), and the selection signal c is at a low level (hereinafter referred to as L).
2 will be described with reference to FIG. The input signal a is delayed by the delay circuit 1 by τ ₁ (nS) at the rise and τ ₂ (nS) at the fall, and is output as a signal d. Since the selection signal b is H, the AND circuit 2 outputs the signal d as it is to the signal g. Then, the OR operation of the input signal a and the signal g is performed by the OR circuit 3, and a waveform whose duty is expanded by τ ₂ from the input signal a is output as the signal i. The input signal a, the inversion circuit 4 is output to the logic inverted signal e, the signal e rises when tau ₁ by the delay circuit 5 (nS), at the fall tau ₂ (nS)
The signal is delayed by an amount of time and output as a signal f, and is again logically inverted by the inverting circuit 6 and output as a signal h.
Since AND is L, the AND circuit 7 outputs L to the signal j, and the OR circuit 8 outputs the signal i to the signal k as it is because the signal j is L. That is, a signal in which the duty is increased by τ ₂ (nS) with respect to the input signal a is obtained as the output signal k. In this case, the operation is the same as that of the conventional duty correction circuit.

Next, the case where the selection signal b is L and the selection signal c is H will be described with reference to FIG.

The input signal a is delayed by the delay circuit 1 by τ ₁ (nS) at the rise and τ ₂ (nS) at the fall, and is output as a signal d. Outputs L to the signal g. Then, since the signal g is L, the OR circuit 3 outputs the input signal a as it is to the signal i. The input signal a is logically inverted by the inverting circuit 4 and output as a signal e. The signal e is output by the delay circuit 5 at the rise time τ ₁ (nS) and at the fall time τ ₂ (nS).
S), the signal f is delayed and output to the signal f.
Is again inverted and output as a signal h. here,
Since the selection signal c is H, the AND circuit 7 outputs the signal h as it is to the signal j. The OR circuit 8 performs a logical OR operation on the signals i and j, and obtains, as the output signal k, a signal in which the duty of the input signal a is increased by τ ₁ (nS).

Next, the case where both the selection signals b and c are L will be described. In this case, as described above, since the selection signal b is L, the AND circuit 2 outputs L to the signal g, and the OR circuit 3 outputs the signal a to the signal i as it is. Also,
Since the selection signal c is L, the AND circuit 7 outputs L to the signal j, and the OR circuit 8 outputs the signal i as it is to the output signal k. Therefore, the input signal a is output as it is to the output signal k. This is a case where the input signal a is output without duty correction.

In the above circuit, the output signals of the AND circuit 2 and the AND circuit 7 are exchanged, that is, the output of the AND circuit 2 is output to the OR circuit 8 and the output of the AND circuit 7 is output to the OR circuit 3. , The same output is obtained as the output signal k.

According to the present embodiment as described above,
By selecting a combination of the selection signals b and c,
Output of the input signal
Τ _TwoOnly, or τ₁Selection to output only by spreading
Can be.

FIG. 4 is a block diagram of a duty correction circuit according to a second embodiment of the present invention. In the present embodiment, the duty is reduced.

This embodiment is different from FIG. 1 in that an OR circuit 9 for performing an OR operation of the output signal g of the AND circuit 2 and the output signal j of the AND circuit 7 in FIG. 9 is provided with an AND circuit 10 for performing an AND operation of the output signal r and the input signal a to obtain an output signal s.

In this embodiment, assuming that the selection signal b is H and the selection signal c is L, a corrected signal whose duty is reduced by τ ₁ with respect to the input signal a is obtained in the output signal s.
Assuming that the selection signal b is L and the selection signal c is H, the input signal a
, A signal whose duty is reduced by τ ₂ is obtained as the output signal s.

[0025]

As described above, according to the present invention, the duty correction width is finely set by using the delay circuits having different rise delay times and fall delay times and using both delay times for duty correction. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of a duty correction circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the duty correction circuit of FIG.

FIG. 3 is a timing chart showing an operation of the duty correction circuit of FIG. 1;

FIG. 4 is a block diagram of a duty correction circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a conventional duty correction circuit.

FIG. 6 is a timing chart showing the operation of the duty correction circuit of FIG.

FIG. 7 is a timing chart showing an operation of the duty correction circuit of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 delay circuit 2 AND circuit 3 OR circuit 4 inverter circuit 5 delay circuit 6 inverter circuit 7 AND circuit 8 OR circuit 9 OR circuit 10 AND circuit 11 delay circuit 12 OR circuit

Claims (3)

(57) [Claims] A first delay circuit for delaying an input signal by different times at rising and falling edges, an output signal of the first delay circuit and a first selection signal,
A first gate circuit that outputs an output signal of the first delay circuit when the first selection signal is active; a first inverter that logically inverts the input signal; an output signal of the first inverter One or more second delay circuits that delay different times at rising and falling times, a second inverting circuit that logically inverts an output signal of the second delay circuit, an output signal of the second inverting circuit, A second gate circuit that inputs a second selection signal that becomes active when the first selection signal is inactive, and outputs an output signal of a second inversion circuit when the second selection signal is active; An output signal of the first delay circuit output from the first gate circuit or a second output signal output from the second gate circuit according to the active selection signal of the first selection signal or the second selection signal. Inverting circuit output Duty correction circuit having a third gate circuit which performs a logical OR operation or a logical AND operation of the signal and the input signal. 2. The logical sum of the input signal and an output signal of a first delay circuit output from the first gate circuit when the first selection signal is active, wherein the third gate circuit performs an OR operation on the input signal. A fourth gate circuit for performing an operation, an output of the fourth gate circuit, and an output signal of the second inversion circuit output from the second gate circuit when the second selection signal is active. 2. The duty correction circuit according to claim 1, comprising a fifth gate circuit that performs an OR operation. 3. The method according to claim 2, wherein the third gate circuit outputs an output signal of the first delay circuit output from the first gate circuit when the first selection signal is active, and the second selection signal. A sixth gate circuit that performs a logical sum operation on an output signal of the second inversion circuit output from the second gate circuit when active, and an output of the sixth gate circuit and the input signal. 2. The duty correction circuit according to claim 1, comprising a seventh gate circuit that performs a logical product operation.