JP2971282B2 - Display device drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a matrix type display device such as a liquid crystal display device, an electroluminescence display device, and a plasma display, and more particularly to a driving device for switching a driving method by a control device for controlling a video signal. It is related to the circuit.

[0002]

2. Description of the Related Art A block circuit diagram showing a configuration of a driving circuit of a conventional liquid crystal display device will be described with reference to FIG. In FIG. 2, the control unit 1 receives various signals SALL such as a clock signal and a synchronization signal. The control unit 1 generates a sampling pulse PSA, a hold pulse PHO, a switching pulse PT, and a line control signal PH based on the various signals SALL, and these are respectively generated by the sampling unit S of the source driver 2.
am, the hold unit H, the switch unit Sw, and the gate driver 4.

[0003] A video signal V1 whose polarity is inverted.
(Hereinafter referred to as “+ polarity”) and V2 (hereinafter referred to as “−polarity”) are externally applied to the terminals T3 and T4. The video signals V1 and V2 are for reproducing a moving image by a television, an audio video, or the like. From the terminal T3 to the sampling circuit Sa of the sampling unit Sam
The video signal V1 is supplied to 1,..., Sai,.
, Sbi,..., Sbn of the sampling section Sam are supplied with the video signal V2 from the terminal T4.

The sampling circuits Sa1, Sb1,..., Sai,
Sbi,..., San, Sbn are sequentially sequenced in time series within one horizontal line period according to the sampling pulse PSA, and the picture element signals A1, B1,.
.., An, and Bn are respectively held and sampled.

When the hold pulse PHO rises after one horizontal line period is completed and the above-described sampling operation is completed, the hold circuits Ha1, Hb1,.
, Han, Hbn are sampling circuits Sa.
, A1, B1,..., Ai, Bi,..., An, and Bn are taken from 1, Sb1,..., Sai, Sbi,.

[0006] The switching unit Sw is provided with a switching pulse P
According to T, by switching the state in which all of the terminal marks conduct simultaneously or all of the terminal marks conduct simultaneously, the hold circuits Ha1,..., Hai,.
Alternatively, one of the hold circuits Hb1,..., Hbi,.
, And En. Specifically, when the odd-numbered gate lines A, C,... Are turned on in the first half of the one-line period, all of the terminal marks are simultaneously turned on, and the second half of the one-line period is turned on. When the gate lines B, D,... Of the even-numbered rows are turned on during the period, all of the terminal peaks conduct simultaneously.

The output buffers E1,..., Ei,
, En are the picture element signals A1, B1, ..., Ai, Bi,
, An, and Bn, which are selected by the switch unit Sw and given from the hold unit H, are amplified and supplied to the source lines SL1,..., SLi,.

In the display panel 3, gate lines A, B, C, D,... , GAi,..., GAn are arranged on the gate line A in order from the left when viewed from the viewing direction 7,
The supply of picture element signals is received from the source lines SL1,..., SLi,. Similarly, n picture elements GB1, ..., G
, GBn are arranged on the gate line B in order from the left as viewed from the viewing direction 7, and the source lines SL1,.
.., Each receives supply of a picture element signal from SLn. , GCi,..., GCn are arranged on the gate line C in order from the left when viewed from the viewing direction 7 and the source line S
, SLi,..., SLn, respectively, receives supply of picture element signals. , GDi,..., GDn are sequentially arranged on the gate line D from the left when viewed from the viewing direction 7,
The supply of picture element signals is received from the source lines SL1,..., SLi,. Picture elements are similarly arranged in other gate lines.

Since the gate line A is turned on during the first half of one line period, n picture elements GA1,.
GAi, ..., GAn are picture element signals A1, ..., Ai, ..., An
, The gate line B is turned on during the latter half of one line period, so that n picture elements GB1,.
, GBn take in the picture element signals B1, ..., Bi, ..., Bn. Thereafter, this operation is repeated, and all picture elements take in picture element signals. Therefore, the odd-numbered gate lines A,
.., An image based on the video signal V1 is reproduced, and on the even-numbered gate lines B, D,.

FIG. 4 shows an image reproduced by the line inversion driving reproduced in this manner. In the figure, odd-numbered gate lines A, C and source lines SLi, SLi + 1, SLi +
2. Picture elements GAi, GA arranged at the intersection of SLi + 3
i + 1, GAi + 2, GAi + 3, GCi, GCi + 1, GCi + 2, GCi + 3
Captures the picture element signal of the video signal V1 having the polarity of "-", and is indicated by "-" in the figure. On the other hand, even-numbered gate lines B, D and source lines SLi, SLi + 1,
Picture element GB arranged at the intersection of SLi + 2 and SLi + 3
i, GBi + 1, GBi + 2, GBi + 3, GDi, GDi + 1, GDi + 2,
Since GDi + 3 takes in the picture element signal of the video signal V2 of “+” polarity, it is described as “+” in the figure.

[0011]

As described above, since the conventional driving circuit can cope only with, for example, line inversion driving, when driving by another driving method, a driving circuit having a dedicated control device for each driving method. Must be designed
There is a problem that the manufacturing cost increases. Further, when changing the driving method, it is troublesome to replace the driving circuit with a dedicated driving circuit.

The present invention solves such a problem and solves the above problem.
It is an object of the present invention to provide a drive circuit of a display device which can be controlled by any one of a plurality of drive systems with one drive circuit.

[0013]

In order to achieve the above object, a driving circuit for a display device according to the present invention comprises first and second holding means for holding first and second video signals for each picture element signal. In order to reproduce an image on a display panel in which a plurality of picture elements are arranged in a matrix at intersections of a gate line and a source line, when the gate lines to be turned on are odd-numbered and even-numbered, The first holding means and the second holding means apply each picture element signal to each picture element on a gate line which is turned on via each source line. A switching circuit for selecting the first and second video signals,
A drive system selection unit for selecting a drive system of the display panel, and a unit for determining a time unit of the switching circuit based on the drive system selected by the drive system selection unit.

[0014]

In this manner, the polarity of each picture element signal constituting each of the first and second video signals can be freely selected and switched. In the liquid crystal display device, the mode can be switched according to the drive system, and the polarity of each picture element signal constituting each of the first and second video signals can be selected and switched according to the drive system.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A driving circuit of a liquid crystal display device embodying the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram showing a configuration of a driving circuit of a liquid crystal display device embodying the present invention.
Shown in In FIG. 1, the same reference numerals are given to the portions shown in FIG. 2 and described as the conventional example, and the description will be omitted. FIG. 3 shows a table of the driving method selected by the selection circuit 5 according to the combination of the signals PA and PB.

As shown in FIG. 3, the selection circuit 5 outputs the signal PA
, PB are both at the “Low” level L, the line inversion drive mode is selected, and the signal PA becomes “Low”.
When the signal PB is at "High" level H at level L, the dot / line inversion drive mode is selected and the signal PA
Is the "High" level and the signal PB is at the "Low" level L, the dot inversion drive mode is selected, or when both the signals PA and PB are at the "High" level H, the one-field inversion drive mode is selected. select.

In FIG. 1, the selection circuit 5 has terminals T1, T
2, the signals PA and PB are taken in from outside. Signal PA
, PB, the control signal PD given from the control unit 1 in the mode of the driving method selected as described above.
Generates a control signal PC and supplies it to the switching circuit 6.
The control signal PD is generated in synchronization with the sampling pulse PSA, and transmits the operating state of the source driver 2.

The terminals T3 and T4 of the switching circuit 6 are supplied with video signals V1 and V2 whose polarities are inverted, respectively. That is, the video signal V1 is composed of the picture element signals A1,..., Ai,
.. An are arranged in chronological order, and the video signal V2
, Bi,..., Bn are arranged in chronological order, but the pixel signals A1 and B1,.
,..., An and Bn have exactly the same signal if their absolute values are taken, although the positive and negative voltage levels are inverted. Each of the picture element signals A1,..., Ai,.
Since Bi,..., And Bn have the same time-axis occupation period, and this is hereinafter referred to as one dot period, n picture elements are arranged on one gate line.
Double is equal to one line period.

The switching circuit 6, based on the control signal PC, in a dot period unit, either between the terminal A and the terminal A, and between the terminal I or the terminal U. Switching is performed so as to make one conductive, and one of the picture element signals (A1, B1) of the video signals V1, V2 is supplied to the terminal D and the other to the terminal E,..., The picture signal (Ai) of the video signals V1, V2 , Bi) to one terminal D and the other to terminal E,..., The picture element signals (An, Bn) of the video signals V1, V2.
) Is applied to the terminal d and the other to the terminal e, thereby generating video signals Sa and Sb at the terminals d and e.

For convenience, the picture element signals of the video signal Sa are represented by a1,
, Ai, ..., an, and the picture element signal of the video signal Sb is b.
,..., Bn will be described below. Therefore,
The combination of the picture element signals (a1, b1) corresponds to the picture element signals (A1,
B1) or (B1, A1) is one of the two combinations, and the other combinations are the same.

, San,..., San of the sampling section Sam are supplied with a video signal Sa from a terminal D. , Sbi,..., Sbn of the sampling section Sam are supplied with the video signal Sb from the terminal (e). Sampling circuits Sa1, Sb1,..., Sai,
Sbi,..., San, and Sbn are sequentially output in one horizontal line period according to the sampling pulse PSA.
Sb picture element signals a1, b1,..., Ai, bi,.
, Bn are held and sampled.

When the hold pulse PHO rises after one horizontal line period is completed and all the sampling operations are completed, the hold circuits Ha1 and Hb of the hold section H are activated.
, Hai, Hbi, ..., Han, Hbn are pixel signals a1, b1, ..., ai, bi, ..., an, from the sampling circuits Sa1, Sb1, ..., Sai, Sbi, ..., San, Sbn. bn
Are simultaneously captured and retained.

In the switch section Sw, when the odd-numbered gate line A is turned on during the first half of the one-line period, all of the terminal marks are simultaneously turned on, and the pixel signals a1,. ,..., An are respectively connected to the source lines S1 through the output buffers E1,..., Ei,.
, SLi,..., SLn, and are taken into n picture elements GA1,..., GAi,.

When the even-numbered gate line B is turned on during the latter half of one line period, all of the terminals and the terminals are simultaneously turned on, and the pixel signals b1,..., Bi,.
, Bn are hold circuits Hb1, ..., Hbi, respectively.
,..., SLi,.
Ln, and n picture elements GB1, ..., GBi,
..., are taken in by GBn. Thereafter, this operation is repeated, and all picture elements take in picture element signals. Therefore, an image based on the video signal Sa is reproduced on the odd-numbered gate lines A, C,..., And an image based on the video signal Sb is reproduced on the even-numbered gate lines B, D,.

Images reproduced by line inversion driving, dot / line inversion, dot inversion, and one-field inversion reproduced in this manner are shown in FIGS. 4, 5, 6 and 7, respectively. 4, 5, 6, and 7, the odd-numbered gate lines A and C and the source lines SLi, SLi + 1, and SLi + 2,
The picture elements GAi, GAi + arranged at the intersection of SLi + 3
1, a picture element signal of the video signal Sa is given to GAi + 2, GAi + 3, GCi, GCi + 1, GCi + 2, and GCi + 3. The gate lines B and D and the source lines SLi and SLi + 1 of the even-numbered rows
Picture element GB arranged at the intersection of SLi + 2 and SLi + 3
i, GBi + 1, GBi + 2, GBi + 3, GDi, GDi + 1, GDi + 2,
The picture element signal of the GDi + 3 video signal Sb is provided. A picture element which was originally a picture element signal of the video signal V1 of "-" polarity is given "-", and a picture element signal of the video signal V2 of "+" polarity is given. "+" Is written on the picture element.

When the line inversion drive mode is selected, conduction is always established between the terminal A and the terminal I. As a result, as shown in the following equation (1), the video signals Sa,
Sb become video signals V1 and V2, respectively, and as shown in FIG. 4, "-" appears on the odd-numbered gate lines A, C,.
An image is reproduced by the picture element signal of the polarity video signal V1,
On the even-numbered gate lines B, D,..., An image is reproduced by the picture element signal of the video signal V2 having the “+” polarity. Sa = (a1, ..., ai, ..., an) = (A1, ..., Ai, ..., An) = V1 Sb = (b1, ..., bi, ..., bn) = (B1, ..., Bi, ...,) Bn) = V2 (1)

When the dot-line inversion drive mode is selected, a state in which conduction is established between the terminals A and E, and a state in which conduction is established between the terminals A and B. And are switched for each dot period. As a result, the video signals Sa and Sb are expressed by the following equation (2).
As shown in FIG. 5, the picture elements GAi, GAi +
2, GCi, GCi + 2 and even row and even column picture elements GBi + 1,
In GBi + 3, GDi + 1, and GDi + 3, a video signal V1 having a "-" polarity
An image is reproduced by the picture element signals of the picture elements GAi + 1, GAi + 3, GCi + 1, and GCi + 3 in the odd rows and the even columns, and the picture elements GBi, GBi + 2, GDi in the even rows and the odd columns. In GDi + 2, an image is reproduced by the picture element signal of the video signal V2 having the “+” polarity. Sa = (a1, a2,..., Ai-1, ai,..., An-1, an) = (A1, B2,..., Ai-1, Bi,..., An-1, Bn) Sb = (b1,. b2, ..., bi-1, bi, ..., bn-1, bn) = (B1, A2, ..., Bi-1, Ai, ..., Bn-1, An)) (2)

When the dot inversion drive mode is selected, a state in which conduction is established between the terminals A and E and a state in which conduction is established between the terminals A and E are performed. Switch every dot period. As a result, the video signals Sa and Sb are expressed by the following equation (3). As shown in FIG. 6, on the odd-numbered source lines SLi, SLi + 2,. An image is reproduced by the picture element signal, and on the even-numbered source lines SLi + 1, SLi + 3,..., The picture is reproduced by the picture element signal of the video signal V2 of the “+” polarity. Sa = (a1, a2,..., Ai-1, ai,..., An-1, an) = (A1, B2,..., Ai-1, Bi,..., An-1, Bn) Sb = (b1,. b2, ..., bi-1, bi, ..., bn-1, bn) = (A1, B2, ..., Ai-1, Bi, ..., An-1, Bn) ... (3)

When the one-field inversion drive mode is selected, the connection between the terminal A and the terminal W is conducted during one field period. As a result, both the video signals Sa and Sb become the video signal V1 as shown in the following equation (4), and as shown in FIG. 7, an image is formed on the entire screen by the picture element signal of the video signal V1 having the "-" polarity. Will be played. Further, during the next one field period, conduction is established between the terminal I and the terminal I. As a result, both the video signals Sa and Sb become the video signal V2 as shown in the following equation (5). Although not shown, an image is reproduced on the entire screen by the picture element signal of the video signal V2 of the "+" polarity. You. Sa = (a1, ..., ai, ..., an) = (A1, ..., Ai, ..., An) = V1 Sb = (b1, ..., bi, ..., bn) = (A1, ..., Ai, ...,) An) = V1 (4) Sa = (a1,..., Ai,..., Ann) = (B1,..., Bi,..., Bn) = V2 Sb = (b1,. B1,..., Bi,..., Bn) = V2 (5)

In the above-described embodiment, four driving systems are selected by the selection circuit 5 for simplicity. However, other driving systems such as line-field inversion driving and dot-field inversion driving can be controlled. May be increased.

Further, two video signals (the video signal S
a, Sb) for each pixel signal (the above-mentioned hold circuits Ha1,..., Hai,.
, Hbi,..., Hbn-side source driver 2), and a gate line (the gate line A,
B, C, D,...), Source lines (the above source lines S
L1,..., SLi,..., SLn) when an image is reproduced on a display panel in which a plurality of picture elements are arranged in a matrix at intersections with each other. The display device is not limited to a liquid crystal display device as long as it is a display device that applies each pixel signal of the first holding unit and the second holding unit to each pixel on a gate line that is turned on via each source line. A display device by other means may be used.

[0032]

As described above, according to the present invention,
Since the polarity of each picture element signal constituting each of the first and second video signals held in the first and second holding means can be freely selected and switched, the polarity of each picture element on the display screen can be freely set. Can be selected and switched. As a result, it is possible to prevent a complicated process and an increase in cost, such as designing and manufacturing a dedicated drive circuit for each combination of the polarities of the picture elements on the display screen.

In the case of a liquid crystal display device, it is possible to switch the mode according to the driving method, and to select and switch the polarity of each picture element on the display screen according to the mode. As a result, it is possible to prevent a complicated process and an increase in cost, such as designing, manufacturing and combining a dedicated driving circuit for each driving method. Further, it is possible to easily switch to a mode of an optimal driving method capable of coping with a display defect occurring at the time of forming a pattern on the display panel.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a configuration of a driving circuit of a liquid crystal display device embodying the present invention.

FIG. 2 is a block circuit diagram illustrating a configuration of a driving circuit of a conventional liquid crystal display device.

FIG. 3 is a diagram showing a table of a driving method selected by a selection circuit.

FIG. 4 is a diagram showing an image obtained by line inversion driving.

FIG. 5 is a diagram showing an image by dot / line inversion driving.

FIG. 6 is a diagram showing an image obtained by dot inversion driving.

FIG. 7 is a diagram showing an image obtained by one-field inversion driving.

[Description of Signs] 1 Control Unit 2 Source Driver Sam Sampling Unit Sa1, ..., Sai, ..., San Sampling Circuit Sb1, ..., Sbi, ..., Sbn Sampling Circuit H Hold Unit Ha1, ..., Hai, ..., Han Hold Circuit Hb1,..., Hbi,..., Hbn hold circuit Sw switch section E output section E1,..., Ei,..., En output buffer SL1,..., SLi,. Source line A, B, C, D, ... Gate line 3 Display panel GA1, ..., GAi, ..., GAn picture element GAi + 1, GAi + 2, GAi + 3 Picture element GB1, ..., GBi, ..., GBn picture Element GBi + 1, GBi + 2, GBi + 3 Picture element GC1, ..., GCi, ..., GCn Picture element GCi + 1, GCi + 2, GCi + 3 Picture element GD1, ..., GDi, ..., GDn Picture element GDi +1, GDi + 2, GDi + 3 Pixel +,-Polarity Line inversion drive Dot / line inversion drive Dot inversion drive Field inversion drive L “Low” level H “High” level 4 Gate driver 5 Select circuit 6 Switching circuit 7 Viewing direction T1 terminal T2 terminal T3 terminal T4 terminal A to A terminal SALL Various signals PA signal PB signal PC control signal PD control signal PSA sampling pulse PHO hold pulse PT switching pulse PH line control signal V1 video signal V2 video signal Sa video signal Sb video signal a1, ..., ai, ..., an picture element signal b1, ..., bi, ..., bn picture element signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 3/00-3/38 G02F 1/133

Claims (1)

(57) [Claims] An image processing apparatus comprising: first and second holding means for holding first and second video signals for each picture element signal, wherein a plurality of picture elements are arranged in a matrix at intersections of gate lines and source lines. In order to reproduce an image on the arranged display panel, when the gate lines to be turned on are odd-numbered and even-numbered gate lines, the respective picture element signals of the first holding means and the second holding means are turned on via the respective source lines. A driving circuit for a display device for applying to each picture element on a gate line, a switching circuit for selecting two video signals having inverted polarities at predetermined time intervals to form the first and second video signals; A drive system selection unit that selects a drive system of the display panel; and a unit that determines a time unit of the switching circuit based on the drive system selected by the drive system selection unit. A driving circuit of a display device.