JP2972376B2 - Microwave monolithic multi-stage power amplifier IC - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave monolithic multi-stage power amplifying IC, and more particularly to an integrated circuit using a compound semiconductor.
The present invention relates to a microwave monolithic multi-stage power amplifier IC of 0 GHz or more.

[0002]

2. Description of the Related Art A conventional microwave monolithic multi-stage power amplifier IC will be described with reference to FIG. 3 showing a plan view of a chip pattern.

[0003] A first stage FET 1 having a small gate width to a last stage FET 5 having a large gate width are formed on a GaAs substrate. The source electrode (not shown) is grounded by via holes 22 to 31 at both ends. Gate-
The direction of the drain electrode (the direction of the input terminal and the output terminal of the FET) is arranged in a fixed direction from the RF input pad 37 to the RF output pad 38. RF input pad 37 to RF
The FETs 1 to 5 of each stage are sequentially connected to the output pad 38.

In the case of a multistage amplifier, even if the area occupied by the intermittent impedance matching circuits 11 to 16 is reduced, it is not possible to prevent the IC chip from becoming longer in the RF input / output direction.

[0005]

The conventional microwave monolithic multistage power amplifier ICs are arranged in a line from the RF input section to the output section even from the first stage to the middle stage having a small gate width. As a result, the size of the IC chip in the RF input / output direction becomes longer, the aspect ratio of the chip becomes larger, and the yield is reduced due to chip cracking.

[0006] Further, the chip area becomes large, resulting in high cost.

[0007]

Means for Solving the Problems A microwave monolithic multi-stage power amplifier IC according to the present invention comprises an input terminal and an output terminal.
In the microwave monolithic multistage power amplifier IC with at least three stages multi-stage cascaded FET to the output drain inputs the gate between the child, the gate of the first FET of the FET - direction of the drain electrode and the second F
The direction of the gate-drain electrode of the ET is configured to be opposite, and the first and second FETs are connected to the input port.
A straight line in the direction perpendicular to the direction of the output terminal from the force terminal
And a third FET among the FETs is connected to the first FET.
And a second FET from the input terminal to the output terminal
Are arranged in a direction horizontal to the direction of .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of the present invention, a monolithic 5
The step power amplifier IC will be described with reference to FIG. 1A showing a plan view of a chip pattern.

The direction of the gate-drain electrode of the FET 2 (the direction of the input terminal and the output terminal of the FET) is different from that of the other FETs.
They are arranged in the opposite direction to 1, 3, 4, and 5, that is, the RF input 37 side is a gate electrode and the RF output 37 side is a drain electrode.

The source electrode of the FET 2 is connected to the via hole 23 for grounding the source electrode of the FET 1 and the via hole 24 for grounding the source electrode of the FET 3 and is grounded in common.

The signal reaches the RF output pad 38 from the RF input pad 37 via the FETs 1 to 5 via the impedance matching circuits 11 to 16.

The chip area can be reduced by arranging the first to middle power amplifying sections from FET1 to FET3 so as to reduce the gap. As a result, IC chip RF
The length in the input / output direction can be reduced to about 70% as compared with the conventional FIG.

Next, as a second embodiment of the present invention, a monolithic 10-stage power amplifier IC will be described with reference to FIG. 1B showing a plan view of a chip pattern.

In the first to seventh FET stages 1 to 7, the gate drain electrodes of the FETs 2, 4, and 6 are arranged in the direction opposite to that of the other FETs 1, 3, 5, and 7. The via hole 23 is a common ground for the FET1 and the FET2, the via hole 24 is a common ground for the FET2 and the FET3, the via hole 25 is a common ground for the FET3 and the FET4, and the via hole 29 is a common ground for the FET5 and the FET6. Thus, the parts of FET1 to FET7 are made compact,
A 10-stage power amplifier circuit can be formed in the same chip size as that of FIG.

For example, if the gain is 5 dB per stage in FIG. 3 of the related art, it is 25 dB in 5 stages, whereas in FIG. 1B of this embodiment, there are 10 stages, so that a gain of 50 dB can be obtained.

[0016]

The first to middle FETs having a small gate width
In this section, the gate electrodes of several FETs are arranged on the RF output side, the drain electrodes are arranged on the RF input side, and the via holes are commonly grounded with the adjacent FETs. Compared to a system in which FETs are sequentially arranged from the RF input unit to the output unit, the chip length in the RF input / output direction can be made very short and the chip area can be reduced.

By improving the aspect ratio of the chip, R
It is possible to eliminate a chip crack that has been generated in the F input / output direction. The chip size can be reduced and the price can be reduced. Further, it is easy to increase the number of FETs.

[0018] Even if the gate-drain electrodes of the FET are arranged in the opposite direction, it is not difficult to form an impedance matching circuit arranged between the FETs.

Abnormal oscillation due to feedback between stages is prevented by separating adjacent signal wirings by at least 1/20 of the wavelength of the operating frequency or by providing a ground line 39 as shown in FIG. be able to.
Feedback from the output of the FET 3 to the input of the FET 2 is blocked by the ground line 39.

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a plan view showing one embodiment of the present invention.

FIG. 3 is a schematic plan view showing a chip pattern of a conventional microwave monolithic multi-stage power amplifier IC.

[Explanation of symbols]

 1-10 FET 11-21 Impedance matching circuit 22-36 Via hole 37 RF input pad 38 RF output pad 39 Ground line

Claims (2)

(57) [Claims] 1. A least three stages FET to output an input gate between the input terminal and the output terminal drain multi
In the microwave monolithic multi-stage power amplifier IC connected in stages, the direction of the gate-drain electrode of the first FET and the direction of the gate-drain electrode of the second FET are opposite to each other. , The first and second FETs are connected from the input terminal to the
Arrange linearly in the direction perpendicular to the direction of the output terminal, and
The third of the FETs is replaced with the first and second FEs.
With respect to T, in the direction from the input terminal to the output terminal.
A microwave monolithic multi-stage power amplifier IC characterized by being arranged in a direction . 2. The source voltage of said first and second FETs.
The poles are commonly grounded through via holes.
Microwave Monolithic multistage power amplifier IC of claim 1, wherein that.