JP2972508B2 - MOS transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor having an LDD structure and a method of manufacturing the same, and more particularly to a structure of a gate electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art For high performance and high integration of LSI,
Although the gate length of a MOS transistor has been reduced, it is necessary to ensure the reliability of the device against hot carriers generated in a depletion layer near the drain, which is accompanied by an increasingly high electric field. As a countermeasure, an LDD (Lightly Doped Drain) structure in which a low-concentration drain region is used for a drain junction to moderate the electric field and the impurity concentration distribution in the drain region is gentle is used. In order to realize this LDD structure, usually, after processing the gate electrode, ion implantation for forming a low-concentration drain region is performed, side walls (sidewalls) are formed on side surfaces of the gate electrode, and then the high-concentration drain region is formed. It is formed by ion implantation. Therefore, in order to realize a CMOS structure, a total of four masking steps are required.

As described above, the conventional method of manufacturing a MOS transistor using sidewalls not only requires a large number of masks and is expensive, but also damages the silicon substrate during the etch-back for forming the sidewalls, thereby lowering the yield. There was a problem that it was easy to do. To solve this problem, Japanese Patent Laid-Open No. 5-29337 discloses a method of forming an eaves type electrode and implementing an LDD structure by performing two ion implantations in the same masking step while changing the ion implantation angle and the implantation dose.
No. FIG.
The process will be described with reference to FIGS.

After forming a field insulating film (3) for element isolation on P-type silicon (1), a gate oxide film (7) is formed.
Grow and form. After sequentially depositing a polycrystalline silicon layer (8) and a refractory metal silicide layer (9), the gate electrode is patterned. Then, the polycrystalline silicon layer (8) is etched to form a gate electrode having an eave structure [FIG.
(A)]. Using this eave structure, ions are implanted from an oblique direction to form an N ⁻ type LDD region (10) [FIG. 7 (b)]. Arsenic from a direction perpendicular to the substrate is ion-implanted with N ^+. The source / drain region (11) is formed to form an NMOS transistor [FIG.
(C)].

[0005]

The eaves type gate electrode as described above is formed by wet etching the polycrystalline silicon layer (8) using a mixed solution of hydrofluoric acid and nitric acid. When the polycrystalline silicon layer (8) is wet-etched from the side surface, the etching proceeds from the central portion, so that the side surface of the polycrystalline silicon layer (8) is rounded as shown in FIG. Further, since the etching rate of the polycrystalline silicon layer largely depends on the size of the crystal grains, the variation in the impurity concentration, the temperature and the concentration of the etching solution, etc., the shape of the side surface of the polycrystalline silicon layer (8) is reduced. Variations are large, and it is very difficult to control the eave length (50) with good reproducibility. If the eave length (50) varies, the width of the N ^- type LDD region (10) and the electrode length of the polycrystalline silicon layer (8) vary, and as a result, the manufacturing variation of device characteristics becomes extremely large. Gate length 0.4μm
N ^- type LD for submicron MOS transistors
Although it is necessary to suppress the manufacturing variation of the width of the D region (10) to about 0.02 μm, it is difficult to realize the above-described structure by wet etching.

In the above-mentioned eaves-type electrode structure, the refractory metal silicide layer (9) serves as a mask for ion implantation when forming the N ⁺ -type source / drain regions (11). . For example, in order to form a 0.4 μm MOS transistor using W silicide for the refractory metal silicide layer, W silicide having a thickness of 0.2 μm or more is required. As a result, in the CMOS process, impurities cannot be introduced into the polycrystalline silicon under the W silicide during ion implantation for forming a high concentration source / drain region. In a deep submicron CMOS having a gate length of 0.3 μm or less, P ⁺ type polysilicon is used for a gate electrode of a PMOS transistor, and an NMOS transistor is used.
An essential technology is a PN type CMOS configuration using N ⁺ type polycrystalline silicon for the gate electrode of the transistor. This is usually realized by introducing impurities into polycrystalline silicon during ion implantation for forming high-concentration source / drain regions. However, as described above, this is impossible with the eaves-type electrode structure, and there is a problem that it is difficult to realize a deep submicron CMOS.

Further, not only in the above-mentioned example, but also in a normal LDD transistor, an ion implantation (hereinafter abbreviated as channel implantation) region for controlling a threshold voltage VT and a gate electrode cannot be provided in a self-aligned manner. According to the scaling rule, as the gate length of the MOS transistor becomes shorter, the impurity concentration of the channel region increases, and if the threshold voltage VT is not scaled, the rate of increase further increases. However, as the concentration of the P-type silicon (1) shown in FIG. 7 is increased, the junction capacitance between the N ⁺ -type drain region (11) and the P-type substrate (1) increases. Prior to formation, channel implantation is performed to set only the channel region to a required impurity concentration [FIG. 9A]. In this case, it is necessary to secure a misalignment margin with respect to the feed insulating film in each of the channel implantation step and the PR step for forming a gate electrode. As a result, as shown by the overlap length (51) in FIG. There is a problem that the channel region (5) expands more than necessary and the drain junction capacitance increases.

[0008]

An LDD structure according to the present invention is provided.
The manufacturing method of the MOS transistor to perform
After forming a P-type well (2) on the plate (1-a),
(2) Selective oxidation using silicon nitride film
Field insulating film (3) and channel for element separation
Forming a topper (17);
A first oxide film (4-a) was formed on the exposed surface of the well (2).
Thereafter, a step of depositing a second oxide film (4-b) on the entire surface,
Mask the turned photoresist (18-a)
Then, the second oxide film (4-b) and the first oxide film (4-a) are etched.
Step of forming an opening by etching,
Prevents punch-through between transistor source and drain
Voltage of 150 to 300 KV and dose of 1 to 5 for
× 10 ¹² cm ^-2 boron ion implantation and threshold voltage
Acceleration voltage for VT control 20 to 50 KV, dose 1
Ion implantation of boron of ~ 5 × 10 ¹² cm ^-2 and channel
Forming a metal injection region (5) and a photoresist
After removing (18-a), the third oxide film (4
-C) forming a hole in the opening, and a nitride film (6) on the entire surface.
Is grown by the CVD method, and then the entire surface is etched back.
Then, a sidewall is formed on the side surface of the second oxide film (4-b).
Forming a side nitride film (6-a), and a third oxide film
After removing (4-c), a gate oxide film is formed by a thermal oxidation method.
(7) forming a polycrystalline silicon by a CVD method;
After growing the etching layer (8-a), the entire surface is etched back to open
Process of embedding a polycrystalline silicon layer in the
Of the polycrystalline silicon layer (8-b) on the
After growth, perform etch back so that the surface becomes flat
The polycrystalline silicon (8-b) is converted into a polycrystalline silicon layer (8-b).
a) for embedding in the dent and wet etching
Part or all of the second oxide film (4-b) is further removed.
And the side nitride film (6-
a) removing the first oxide film (4-a);
Depositing a fourth oxide film on the entire surface after the
N by rotation ion implantation from the direction ^- -type LDD region (1
0) forming the arsenic in a direction perpendicular to the substrate
N ⁺ type source / drain by ion implantation from
At the same time as forming the region (11), the polysilicon layer (8
-A) and arsenic is introduced into the polycrystalline silicon layer (8-b).
Forming a N ⁺ -type polycrystalline silicon layer (8-c );
The side oxide film (12) is formed by oxidation or CVD.
And N ⁺ type by etching back the entire surface of the oxide film
The surface of the polycrystalline silicon layer (8-c) and the N ⁺ type source
A step of exposing the surface of the drain region (11);
Process of depositing titanium (Ti) and annealing
Performing a step of selectively removing reaction Ti and annealing,
N ⁺ -type poly-surface and the N ⁺ -type source crystal silicon layer (8-c)
Ti silicide on the surface of the source / drain region (11)
Step of forming (13) and BPSG film (14) on the entire surface
And forming a contact on the BPSG film (14).
A step of forming a hole, and a step of forming an embedded electrode (15) in the contact.
Forming a wiring electrode on the upper surface of the buried electrode (15)
(16) performing the formation .

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional structural view of an NMOS transistor according to an embodiment of the present invention. P in a region separated by the field insulating film (3) and the channel stopper (17)
An NMOS transistor is formed on the mold well (2). An N ⁺ -type polycrystalline silicon layer (8-C) is provided via a gate oxide film (7), and the length of the N ⁺ -type polycrystalline silicon layer (8-C) is lower in the channel direction than in the upper part. Has a short inverted tapered shape. The channel implantation region (5) is set to have a higher impurity concentration than the P-type well region (2) and to obtain a desired threshold voltage VT. This region is an N ⁺ type polysilicon layer (8−
C) is formed in a self-aligned manner.

Then, an N ⁺ type polycrystalline silicon layer (8−
An N ⁻ type LDD region (10) and an N ⁺ type source / drain region (11) are provided in a P type well (2) in a self-alignment manner with respect to C). The overlap between the channel implantation region (5) and the N ⁺ -type source / drain region (11) is as small as about the lateral diffusion width of the impurity. Ti silicide (13) is provided in a self-aligned manner using the feed oxide film (3) and the side oxide film as masks in the extraction regions of the source, drain, and gate electrodes, thereby realizing a salicide structure. A buried electrode such as W is buried in the contact opening of the BPSG film (14), and a wiring electrode (16) having a laminated structure of, for example, Al-SiCu and TiN is present above the buried electrode.

Next, the manufacturing process of the above embodiment will be described with reference to the process sectional view of FIG. P-type silicon substrate (1-
a) The surface temperature is 5 × 10 ¹⁶ to 1 × 10 ¹⁷ cm on top
After forming the P-type well (2) ^-3 , a field insulating film (3) having a thickness of about 0.5 μm for element isolation and a channel stopper (4) are formed by using a known technique of selective oxidation using a silicon nitride film. 17) is formed. Thereafter, a first oxide film (4) having a thickness of about 50 nm is formed by a thermal oxidation method at about 900 ° C.
-A), and a second layer having a thickness of 300 to 400 nm is formed on the entire surface.
An oxide film (4-b) is deposited. Then, using the patterned photoresist (18-a) as a mask, the second oxide film (4-b) and the first oxide film (4-a) are etched, and an acceleration voltage of 150 to 300 KV and a dose of 1 to 5 × 10 ¹²
cm ⁻² boron ion implantation and an acceleration voltage of 20-50.
A channel implantation region (5) is formed by ion implantation of boron having a KV and a dose of 1 to 5 × 10 ¹² cm ⁻² [FIG. 2- (a)]. The former ion implantation is performed to prevent punch-through between the source and the drain of the MOS transistor, and the latter ion implantation is performed to control the threshold voltage VT. Thereafter, the photoresist (18-a) is removed, the opening is oxidized, the side nitride film (6-a) is formed, the gate oxide film (7) is formed, and the opening of the polycrystalline silicon layer (8) is formed. To form a gate electrode [FIG. 2- (b)].

The process during this time will be described in detail with reference to FIGS. 4 and 5, which are enlarged sectional views of the opening shown in FIG. After removing the photoresist (18-a) in FIG. 2A, a third oxide film (4-c) having a thickness of about 30 nm is formed in the opening by a thermal oxidation method at about 900 ° C. Thereafter, a nitride film (6) having a thickness of about 50 to 200 nm is grown on the entire surface by a CVD method (FIG. 4A). Next, etch back is performed on the entire surface to form a side nitride film (6-a) serving as a sidewall on the side surface of the second oxide film (4-b). At this time,
The third oxide film (4-c) serves as an etching stopper to prevent the channel implantation region (5) from being damaged. Then, after removing the third oxide film (4-c), the temperature is reduced to 700-400.
A gate oxide film (7) having a thickness of 8 to 15 nm is formed by a thermal oxidation method at 900 ° C. [FIG. 4 (b)].

Then, after growing a polycrystalline silicon layer (8-a) having a thickness of 0.5 to 2 μm by the CVD method (FIG. 4C),
The whole surface is etched back to bury polycrystalline silicon in the opening [FIG. 4 (d)]. At this time, the second oxide film (4-c) serves as an etching stopper, and the end point of the etching can be easily detected by the end point detector (EPD). When a dent is formed in the center of the polycrystalline silicon layer (8-a) and the embedding is incomplete, the thickness is again 0.5 to 2 μm.
Growth of the polycrystalline silicon layer (8-b) to the extent shown in FIG.
(A)], etch-back is performed, and polycrystalline silicon (8-b) is embedded so that the surface becomes flat [FIG.
(B)].

At this time, it is also possible to realize a polycide structure using a refractory metal silicide such as W silicide without using the polycrystalline silicon layer (8-b). Thereafter, part or all of the second oxide film (4-b) is removed by wet etching, and the side nitride film (6-a) is removed by wet etching using phosphoric acid [FIG.
(C)]. At this time, the etching rate ratio between the nitride film (6-a) and the polycrystalline silicon layers (8-a) and (8-b) is 4
Since the ratio is about 0: 1, the amount of the polycrystalline silicon removed is very small. Then, after removing the first oxide film (4-a), a fourth oxide film having a thickness of about 20 nm is deposited on the entire surface (omitted in the drawing). Next, an N ^- type LDD region (10) is formed by rotating ion implantation of phosphorus. For example,
Accelerating voltage 50-100KV, dose 1-5 × 10 ¹³
Ion implantation is performed under the conditions of cm ⁻² and an implantation angle of 45 ° [FIG. 2C].

Thereafter, N ⁺ -type source / drain regions (11) are formed by implanting arsenic ions in a direction perpendicular to the substrate. For example, acceleration voltage 50 to 80K
Ion implantation is performed under the conditions of V and a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² (FIG. 2D). At this time, arsenic is introduced into the polycrystalline silicon (8-a) and (8-b),
It becomes an N ⁺ type polycrystalline silicon layer (8-c). Thereafter, by thermal oxidation or CVD temperature 700 to 800 ° C. to form a side surface oxide film having a thickness: 10 to 20 nm (12) [Fig. 3 (a)], by etching back the entire surface of the oxide film, ^{N +} -type poly The surface of the crystalline silicon layer (8-c) and the surface of the N ⁺ -type source / drain region (11) are exposed, and the entire surface has a thickness of 3n.
About m of titanium (Ti) is deposited. And 600-7
Lamp annealing at 00 ° C, selective removal of unreacted Ti, 8
Lamp annealing at 00 to 900 ° C. is performed to form Ti silicide (13) (FIG. 3B).

Thereafter, formation of a fourth oxide film (omitted in the figure) by CVD, formation of a BPSG film (14), opening of a contact, for example, a buried electrode (1) made of Ti / TiN / W
By forming 5), for example, forming a wiring electrode (16) made of Al-Si-Cu, an NMOS transistor having desired characteristics as shown in FIG. 1 is realized. In this embodiment, N
Although the MOS transistor has been described, application to a PMOS transistor is also easily possible. P-type well (2)
Instead of an N-type well, an N-type channel injection region instead of a P-type channel injection region, and an N ⁻ type LDD region (1
P instead of 0) ^- type LDD region, ^{P +} type source and drain regions in place of the ^{N +} -type source and drain regions (11), instead of the ^{N +} -type polycrystalline silicon layer (8-c) ^{P +}
By using the type polycrystalline silicon layer, a PMOS transistor having desired characteristics can be realized.

[0017]

[Embodiment 2] FIGS. 6A to 6C show a process of forming an NMOS transistor having a one-sided LDD structure in which only the drain side is formed into an LDD structure by using a reverse tapered gate electrode. After forming a reverse-tapered polycrystalline silicon layer (8) in the same manner as in the previous embodiment, an N ⁻ -type LDD region (10) is formed by oblique ion implantation of phosphorus (P) from one direction [FIG. a)]. For example, an acceleration voltage of 50 to 100 KV,
Ion implantation is performed under the conditions of a dose of 1 to 5 × 10 ¹³ cm ⁻² and an implantation angle of 45 °. Then, an N ⁺ type source is formed by oblique ion implantation of arsenic from the opposite direction to the phosphorus ion implantation.
A drain region (11) is formed [FIG. 6 (b)]. For example, an acceleration voltage of 50 to 80 KV, a dose of 5 × 10 ¹⁴ to
Ion implantation is performed under the conditions of 2 × 10 ¹⁵ cm ⁻² and an implantation angle of 30 °. From the direction perpendicular to the substrate, for example, an acceleration voltage of 50 to 80 KV and a dose of 1 × 10 ¹⁵ to 1 × 10
N ^- type LD by arsenic ion implantation under the condition of ¹⁶ cm ^-2
The D region (10) is set to have a desired width [FIG. 6 (c)].

After that, similarly to the above-described embodiment, formation of Ti silicide, formation of an interlayer film, opening of a contact, and formation of an electrode are performed to form an NMOS transistor having a one-sided LDD structure. The transistor formed in this embodiment is
Since the N ⁻ -type LDD region (10) is provided only on the drain side where electric field relaxation is required, there is an advantage that the source resistance is reduced and the driving capability of the transistor is improved as compared with the above-described embodiment.

[0019]

As described above, in the present invention, the shape of the gate electrode is determined by the shape of the third insulating film. For example, in the above-described embodiment, the shape of the side nitride film (6-a) depends on the thickness of the second oxide film, the thickness of the nitride film and the shape of the opening before the etch back, and the amount of the etch back of the nitride film. However, these can be easily reduced by management in the production line. The height of the gate electrode can be easily detected by using an endpoint detector (EPD) at the time of etching back the polycrystalline silicon layers (8-a) and (8-b). it can. Therefore, a reverse tapered gate electrode with good controllability can be easily obtained.
It is sufficiently possible to control the variation in the width of the N ⁻ type LDD region to 0.02 μm or less in the m MOS transistor. Therefore, it is possible to obtain a MOS transistor with small manufacturing variations, which has been difficult with a conventional MOS transistor using an eave-shaped gate electrode by wet etching.

Further, in the present invention, as described above, the PMOS
It is possible to use P ⁺ -type polycrystalline silicon for the gate electrode of the transistor and use N ⁺ -type polycrystalline silicon for the gate electrode of the NMOS transistor.
The OS structure can be easily realized. Both PMOS and NMOS transistors can be of a surface channel type with small manufacturing variations in characteristics, and it is easy to realize a deep submicron CMOS, which has been difficult with conventional eaves type electrodes. Furthermore, in the present invention, since the channel injection region can be formed in a self-aligned manner with respect to the gate electrode, a desired threshold voltage can be obtained by increasing the concentration of the well only in a necessary region. For example, in the case where the impurity concentration of the channel implantation region is four times as high as that of a well in a MOS transistor having a gate length of 0.4 μm, the ratio of the area where a direct junction with the channel implantation region is formed in the drain region by using the present invention. Is reduced from 38% to 13%, so that the drain junction capacitance is reduced by about 25%. This effect can be similarly obtained for an LDD type MOS transistor using a conventional sidewall.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of one embodiment of the present invention.

FIG. 2 is a process sectional view of one embodiment of the present invention.

FIG. 3 is a process sectional view of one embodiment of the present invention (continued).

FIG. 4 is a process sectional view of an opening in one embodiment of the present invention.

FIG. 5 is a process sectional view of a hole in an embodiment of the present invention (continued).

FIG. 6 is a process sectional view of a second embodiment of the present invention.

FIG. 7 is a process sectional view of a conventional example.

FIG. 8 shows a shape of an eaves type gate electrode in a conventional example.

FIG. 9 shows a conventional method for forming a channel injection region.

[Explanation of symbols]

1: P-type silicon 1-a: P-type silicon substrate 2: P-type well 3: Field insulating film 4-a: First oxide film 4-b: Second oxide film 4-c: Third oxide film 5: Channel Implanted region 6: Nitride film 6-a: Side nitride film 7: Gate oxide film 8, 8-a, 8-b: Polycrystalline silicon layer 9: Refractory metal silicide layer 10: N ^- type LDD region 11: N ⁺ Type source / drain region 12: side surface oxide film 13: Ti silicide 14: BDSG film 15: buried electrode 16: wiring electrode 17: channel stopper 18-a, 18-b: photoresist 50: eave length 51: overlap Long

Claims (1)

(57) [Claims] 1. A P-type silicon substrate is formed on a P-type silicon substrate.
After forming the well (2), silicon nitride is formed on the well (2).
Field for element isolation using selective oxidation method with membrane
Formed insulating film (3) and channel stopper (17)
And an exposed surface of the well (2) by a thermal oxidation method.
After the first oxide film (4-a) is formed on the entire surface, the second oxide film
Depositing a film (4-b) and masking the patterned photoresist (18-a).
The second oxide film (4-b) and the first oxide film (4
Forming a hole by etching a), and forming a hole between the source and the drain of the MOS transistor in the hole.
Acceleration voltage 150-300K to prevent punch-through
V ion implantation of boron with dose of 1-5 × 10 ¹² cm ^-2
Speed voltage 20 to 50 for ON and threshold voltage VT control
KV, boron ions with a dose of 1-5 × 10 ¹² cm ^-2
Implanting to form a channel implanted region (5), and removing the photoresist (18-a);
Forming a third oxide film (4-c) in the opening portion
Then, a nitride film (6) is grown on the entire surface by the CVD method.
To the side of the second oxide film (4-b).
Form side-wall nitride film (6-a) to be a sidewall on the surface
And removing the third oxide film (4-c), followed by thermal oxidation.
Forming a gate oxide film (7), and growing a polycrystalline silicon layer (8-a) by a CVD method.
The entire surface is etched back and the polycrystalline silicon layer
Embedding (8-a), and forming polycrystalline silicon on the polycrystalline silicon layer (8-a).
After the growth of the layer (8-b), etch back is performed, and the surface becomes flat.
The polycrystalline silicon (8-b) is mixed with
Embedding in the recesses of the monocrystalline silicon layer (8-a), and wet etching of the second oxide film (4-b).
Removing a part or all of the side nitride film (6-a) by wet etching;
Removing the first oxide film (4-a), and removing the fourth oxide film on the entire surface after removing the first oxide film (4-a).
The process of depositing the film and the rotating ions from the oblique direction of phosphorus
Step of forming N ^- type LDD region (10) by implantation
When ions are implanted from the direction perpendicular to the substrate arsenic
To form N ⁺ type source / drain regions (11)
At the same time, the polycrystalline silicon layer (8-a) and the
The arsenic is introduced into the polycrystalline silicon layer (8-b) to form an N ⁺ type
Forming a polycrystalline silicon layer (8-c) and forming a side oxide film (12) by a thermal oxidation method or a CVD method.
Forming step and etching back the entire surface of the oxide film to form the N ⁺ -type polycrystalline silicon.
The surface of the con-layer (8-c) and the N ⁺ type source / drain
Exposing a surface of the emission region (11), depositing a titanium (Ti) on the entire surface, and the annealing, a step of selective removal of the unreacted Ti, an annealing, the N ⁺ -type poly Crystalline silicon layer (8-
c) and the N ⁺ type source / drain regions (1)
Step of forming Ti silicide (13) on the surface of 1)
Forming a BPSG film (14) on the entire surface; and forming a contact hole in the BPSG film (14).
And a step of performing the formation of the buried electrode (15) in the contact
And forming a wiring electrode (16) on the upper surface of the buried electrode (15).
Performing an LDD structure.
Manufacturing method of a MOS transistor.