JP2973004B2 - Control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device suitable for controlling a power supply of an image forming apparatus such as a copying machine and a printer.

[Conventional technology]

2. Description of the Related Art Conventionally, electric components of an image forming apparatus such as a copying machine and a printer are composed of a sequence controller circuit centered on a microprocessor for controlling the entire print sequence,
Various devices such as a power source, an exposure power source, and a high voltage power source such as charging were independent. Therefore, there is a limit to reducing the size and cost of this type of image forming apparatus.

Therefore, in order to form the above components on one board, one chip includes a microprocessor, a RAM, a ROM, a digital peripheral circuit, an A / D converter, a D / A converter, a PMW circuit for controlling a power supply system, and the like. It has been proposed to accumulate.

[Problems to be solved by the invention]

However, as described above, simply integrating each element increases the circuit scale, and in particular, increases the circuit scale of the PWM circuit, increases the chip area as a whole, and makes it difficult to reduce the cost.

The present invention has been made under such circumstances,
It is an object of the present invention to provide a control device capable of controlling multiple outputs, reducing the chip area when integrating each element on one chip, and reducing the cost.

[Means for solving the problem]

In order to achieve the above object, in the present invention, the control device is configured as in the following (1), (2), and (3).

(1) In a control device including a control mechanism for controlling a plurality of power supply circuits, a plurality of analog input terminals for inputting analog signals from the plurality of power supply circuits and another analog signal source; A multiplexer for selecting one of the plurality of analog signals to be input, a first reference signal for comparison with an analog signal from the power supply circuit selected by the multiplexer, and the analog signal source selected by the multiplexer Reference signal generating means for generating a second reference signal for comparison with the analog signal from the first switch, a first switch for turning on and off the input of the analog signal selected by the multiplexer, and a parallel connection to the first switch. And a second switch for turning on and off the input of the first or second reference signal from the reference signal generating means. A switch, a capacitor connected in series to a parallel circuit of the first switch and the second switch, an inverter connected in series to the capacitor, and a third switch connected to both ends of the inverter. The first to third switches are operated at a predetermined timing to repeat charging and discharging of the capacitor, so that an analog signal from the power supply circuit and an analog signal from the first reference signal or the analog signal source are output. Comparing means for comparing a signal with the second reference signal; and outputting the output of the comparing means when comparing the analog signal from the power supply circuit with the first reference signal to one of the plurality of power supply circuits. Control signal generating means for outputting a control signal, and comparing means for comparing the analog signal from the analog signal source with the second reference signal Based on the comparison result, a reference value for generating a new second reference signal for comparison with the analog signal from the analog signal source is calculated, and the reference value is supplied to the reference signal generating means. An arithmetic circuit, controlling the plurality of power supplies, and weighting each of the plurality of power supply circuits and the analog signal source so as to output the calculated reference value as a digital signal; the multiplexer, the comparing means,
The control signal generating means, a timing control means for repeatedly controlling each operation timing of the digital arithmetic circuit,
A control device having:

(2) The control device according to (1), wherein the control signal generation means generates a control signal of a pulse width modulation circuit for performing switching control of a primary side of each transformer of the plurality of power supply circuits.

(3) A control device in which the control device according to (2) is integrated on the same chip together with a microprocessor for controlling the operation of the image forming apparatus, a digital circuit such as a memory, and the pulse width modulation circuit.

[Action]

With the above configurations (1), (2) and (3), the comparison means and the reference signal generation means can be used for the control signal generation and the analog-to-digital conversion of the power supply circuit. Can be controlled to desired timings.

EXAMPLES Hereinafter, the present invention will be described with reference to examples.

FIG. 1 is a block diagram of a "control device" according to a first embodiment of the present invention, FIG. 2 is a timing chart of the embodiment,
FIG. 3 is a circuit diagram of a comparator used in the embodiment.

This control device consists of an A / D converter and a PWM (Pulse Width Modu
lation, pulse width modulation) There are two modes of operation as a control circuit.

In FIG. 1, 1 is a comparator, 3 is a multiplexer (MPX circuit) for switching an external input of the analog input terminal 20, 4 is a latch having a plurality of latch means, and 5 is D / A.
The converter 2 controls the timing of each block, and is a timing generator that changes the timing speed according to the type of output of the multiplexer.

The operation will be described with reference to the timing chart of FIG.

The MPX circuit 3 is switched so that the timing generator 2 inputs external detection data (external input) serving as a comparison value. By turning on SW1 and SW3 and turning off SW2 shown in FIG. 3, the detection value selected by the MPX circuit 3 is input to the comparator 1. At the same time, D / A conversion data is stored in RAM
6. Select from the D / A conversion table above and set in the D / A converter 5. Next, by turning on SW2 and turning off SW1 and SW3, M
The value selected by the PX circuit 3 is compared with the reference D / A conversion value, and the result is held in the latch 4.

In FIG. 1, a selector 7 inputs and selects the output of a normal arithmetic unit 8 and outputs it to a RAM 6.

The A / D converter compares the analog value of the external input selected by the MPX circuit 3 and the reference voltage from the D / A converter 5 with a comparator 1
Then, based on the result, the next reference voltage to be compared with the input (the second group of reference signals) is determined by the arithmetic unit 8 and compared with the analog value. Such comparison is performed by the arithmetic unit 8 from the most significant bit to the least significant bit until the reference voltage by the D / A converter 5 approaches the input analog value, and when all bits are determined, the A / A It is latched in the register B as a D conversion value.

The operation as a PWM control circuit will be described. The output of the D / A converter 5 that uses the external input via the MPX circuit 3 as a reference value (first
The reference signal of the group is compared with the comparator 1, and the comparison result is held in the latch 4. One of the outputs of the latch 4 is supplied to the MAIN / PWM circuit 9, and the other is the SUB-PWM circuits 13-1.
Supplied to 5.

The transfer of data between the control device and the CPU is performed via the registers 10 to 12 (register A, register B, register C) in FIG. The register A is a register for setting data on the D / A conversion table. The register B is a register for reading out the result of the A / D conversion on the CPU / BUS16. Register C is used for setting the status of A / D / D / A conversion operation and RAM
6, a register for setting each address of the MPX circuit 3, the latch 4, and the like.

As described above, the present control device has two modes of operation as (PWM) control signal generation means and operation as A / D conversion signal generation means, and the timing generator controls the timing of each operation. Block, CPU / B
The exchange of data between the US is performed via each register.

FIG. 4 is a block diagram of a MAIN / PWM circuit connected to the control device.

In the preceding control device, the input of the multiplexer 3 is compared by the analog comparator 1 and the results are held in the latch means of the latch 4, respectively. In the MAIN / PWM circuit, the result is held in one of the latch means. FLIP results
-Input to FLOP31. The input comparison result of the analog comparator is clock-synchronized by the FLIP-FLOP 31, and is input to the UP / DOWN determination terminal of the next-stage UP / DOUN COUNTER 32. At this time, the initial value of the counter is input to the UP / DOUN COUNTER 32 from the CPU / BUS 39 via the 4-bit register 47. The initial value is counted up / down with the UP / DOWN value of FLIP / FLOP31.
・ Sent to COUNTER33. The value of the sent count is UP
・ Reads in synchronization with the LOAD signal of COUNTER33 and starts counting. The output signal of UPCOUNTER33 is DIG
ITAL / COMPARETER34, 4bit register 48 from CPU / BUS39
And the result of the comparison is provided as a pulse width modulation (PWM) output result. In Fig. 4, UP
・ The output of COUNTER33 is connected to 7bitAND35, which detects the end of counting. UP ・ DOUN COUN based on this signal
Read the data of TER 32. Here, UP ・ DOUN COUNTER
The 32, UP, COUNTER 33 and DIGITAL, COMPATERTER 34 have a 7-bit configuration and have the required precision.

FIG. 5 is a block diagram of the second embodiment. The stage preceding the selector 16 has the same configuration as that of the first embodiment shown in FIG.
The MAIN / PWM circuit 9 has the same configuration as that shown in FIG. 4 and is omitted.

In the figure, A-1 is the output of the MAIN / PWM circuit 9, drives the main transistor A-13, drives the primary side of the transformer A-10, and outputs the output A from the secondary winding.
−11 is obtained. The output A-11 is divided and fed back as an A-3 signal to become one input of the MAX circuit 3. Also, the sub PW from the other winding on the secondary side of the transformer A-10
The output is taken out to A-12 which is M output, and A-12
On the low-voltage side of the output, one end is connected to the other terminal of A-8, which is a capacitor C _X1 grounded, and one end is connected to a collector of a transistor _Trx1 , A-5 as a control element. The other terminal of _X22 , A-7 is connected. The emitter of the transistor _Trx1 , A-5 has one terminal connected to the other terminal of the resistor Rx1, A-6 whose ground is grounded. A-2, which is one output of the latch 4, drives a base, which is a control pole of the transistor A-5, via a resistor. High side of the emitter That resistance R _X1 of the transistor, as a feedback signal A-4, becomes one input of the MPX circuit 3.
The feedback signals of A-3 and A-4 are output from the MPX circuit 3,
The voltage dividing ratio is appropriately selected so as to fall within the operating range of the comparator 1 and the like.
Pull up to _CC or pull down to GND.

A-9 is a varistor and a current control resistor for protecting the transistor A-5 when the low voltage side A-12b of the output A-12 rises excessively. A-14 is another sub
This is a PWM output and has the same configuration as that of the above-mentioned sub PWM.

 Hereinafter, the operation of this embodiment will be described in detail.

In this embodiment, the comparator 1 is a normal analog comparator for simplicity. First, the timing generator 2 drives the MPX circuit 3 to select the A-3 input and inputs it to the comparator 1. At the same time, selector 16
To select the latch 17, read the data of the latch 17, and input the data to the D / A converter 5. D / A converter 5
Generates an analog voltage according to the input and uses the analog voltage as the other input of the comparator 1. The comparator 1 compares the output of the MPX circuit 3 with the output of the D / A converter 5 by the above-described operation, and outputs high or low according to the magnitude of the comparison. At this time, the timing generator 2 supplies a bit corresponding to the MAIN / PWM circuit 9 to the latch 4 and, at the same time, outputs a latch signal and latches the high / low output of the comparator 1. As described above, the output of the latch 4 is connected to the UP / DOWN selection input of the UP / DOWN counter in the MAIN / PWM circuit 9 as an input signal of the MAIN / PWM circuit 9, and as a result, the pulse width modulated MAIN / PWM The output A-1 of the PWM circuit 9 drives the main transistor A-13, and controls the output of A-11 to a constant voltage. The above is the MAIN / PWM operation.

Next, the timing generator 2 drives the MPX circuit 3 so as to select the A-4 input and inputs it to the comparator 1. At the same time, drive the selector 16 to select RAM6,
Further, an address storing the set value of the A-12 output is given to the RAM 6 and read out, input to the D / A converter 5, and the D / A converter 5 converts the input value to an analog voltage, and Input to one terminal.

As described above, the comparator 1 compares the two, generates a high / low signal according to the magnitude of the signal, and inputs the signal to the latch 4. The latch 4 uses the signal of the timing generator 2 to change the bit corresponding to the A-2 output. Selected and latched. The A-2 output drives the transistor A-5 through a resistor and a capacitor _CX2 , one side of which is grounded, and performs the operation described later. The above is the SUB / PWM SUB0 operation.

 Next, the aforementioned MAIN / PWM operation is performed.

Further, the timing generator 2 drives the MPX circuit 3 so as to select the A-16 input, and inputs the same to the comparator 1. At the same time, the selector 16 is driven to select the RAM 6, and the address storing the set value of the A-14 output is given to the RAM 6, input to the read D / A converter 5, and the D / A converter 5 The value is converted to an analog voltage and input to the other terminal of the comparator 1. The comparator 1 compares the two and generates a high / low signal, which is used as an input to the latch 4. The latch 4 selects and latches the bit corresponding to the A-15 output by the signal of the timing generator 2. A-15 performs the same operation as SUB0 described later. The above is the operation of the SUB / PWM SUB1.

Next, the MAIN / PWM operation is performed, and then the A / D conversion operation described in the first embodiment is performed. The above operation is repeated as one cycle.

FIG. 6 shows a timing chart of the present embodiment. As mentioned above, MAIN → SUB0 → MAIN → SUB1 → MAIN → A /
The operation is repeated with D as one cycle, and when this cycle is T, the SUB · PWM (SUB0, SUB1) becomes a pulse train for selecting high / low by comparing the set value and the output value for each T. That is, the pulse train has a high period of nT and a low period of mT (where n and m are integers).

Now, the A-12 output is stabilized as follows.
The low voltage side A-12b and the high voltage side A-12a of the A-12 output winding are
Since the primary side of the transformer A-10 is controlled by the feedback signal from the output A-11, a voltage that follows the output of the A-11 is generated. Now the A-11 output is that in a steady state, which is a constant voltage V ₀ that is between the A-12a and A-12b. At this time, FIG. 7 shows the main part of the A-12 output extracted and rewritten as an equivalent circuit. In FIG. 7, A-12 output voltage is V _out , and load impedance is R _L
And keep it.

With the configuration shown in the figure, all the current flowing through the load _RL passes through the secondary winding of the transformer and passes through the transistor _Trx1 , so that the A-4 voltage signal has a value proportional to the current flowing through the load _RL. Become. This value is fed back and compared with the reference value to form a pulse train of the A-2 signal. Therefore, the present embodiment operates at a constant current.

Now, A-2 pulse train is converted into DC voltage by the configured low-pass filter by resistor R _x3 and capacitor C _X2. Current flowing through the load R _L and this DC voltage is Vd, also the T _rx1 that it ideal _{transistor, i 0 = (Vd-V} BE) / R X1 and expressed.

Therefore, the transistor _Trx1 of this embodiment performs the same operation as a normal series regulator, and these operations are conceptually shown in FIG.

Actually, a ripple component that cannot be completely removed by the low-pass filter is superimposed on Vd, and i ₀ includes a ripple current. Therefore, a stable output is obtained by smoothing with a filter of a resistor R _X2 and a capacitor C _X1 .

FIG. 9 shows a microcomputer (microprocessor), a peripheral memory, and a digital circuit through a timer.
The above control device, the MAIN / PWM1 circuit and the SUB / PWM3 circuit are integrated on the same chip for control control, ie, the third control.
1 shows an overall configuration diagram of a “control device” of an embodiment. With this chip, most control such as copying machine and printer sequence control and power supply control can be performed.

The configuration of the controller is DATA
・ CPU with built-in MEMORY PROGRAM, MEMORY INTERRUPT, CONTROL etc. D / A converter 5 that performs digital-to-analog conversion based on the A / D conversion block, D / A converter / A / A A D / A / A / D controller 56 that controls the D conversion block and each operation timing is arranged.

The A / D conversion block includes a multiplexer circuit (MP) that performs input switching according to the operation timing of the D / A / A / D controller 56 before the A / D conversion in order to A / D convert a plurality of analog values.
X circuit) 3 is built in.

The A / D conversion is used for reading various voltage of the volume for adjusting the fixing thermistor and copy density of the copying machine. The D / A converter is used as a reference voltage for a comparator 1 of a pulse width modulation (PWM) circuit such as a fluorescent light dimming control and a high voltage control of a copying machine.

The development AC bias drive pulse generator includes a 4-bit divider 55 for dividing the CPU internal clock and a 1/2 divider 5 for setting the development AC bias drive pulse to 50% duty.
4 is used.

Pulse width modulation (PWM) circuits 9,13,14,15 are used for low-voltage power supply control, high-voltage power supply, and fluorescent lamp dimming control. For low-voltage power supply control, a digital 7-bit MAIN / PWM circuit 9 is used. In other PWM circuits, the output result of the comparator is directly P
The SUB / PWM circuits 13 to 15 having the configuration of WM output are used. In addition, the low-voltage power supply control PWM circuit has a PWM output instantaneous shutdown function when the power supply is abnormal, and the input is composed of a comparator 58.
The PWM output is turned off immediately to protect the circuit and enhance the safety of the copier.

The controller has other ports such as an input port 62 for inputting key switch information of the operation unit such as various sensor inputs and setting of copy start and number of copies, and a motor / port.
Output port 6 for controlling heaters, solenoids, etc.
1. There is an output port 59 for the LED drive for display.

A checker is connected to the main body of the machine in order to check the operation of the copying machine at a factory or a market. The checker also has a serial communication port 60 and the like.

In FIG. 9, D / A CONT 56 is the timing generator 2, RAM 6, selector 7, arithmetic unit 8, register 1 in FIG.
Includes 0-12 equivalents. The CPU is, for example, as shown below:
Data is set in each block to control each output of MAIN / PWM and SUB / PWM.

Register A10, register B11, register C12,
The 4-bit registers 47 and 48 shown in FIG. 4 are assigned independent addresses in the case of, for example, memory-mapped I / O, and similarly assigned independent port numbers in the case of port I / O. Is done.

Since the 4-bit registers 47 and 48 in FIG. 4 can be set independently, the CPU addresses each register and sets a predetermined value, thereby designating a parameter defining the operation of MAIN / PWM. The D / A conversion value, that is, the set value of each PWM of SUB and A
The RAM for storing the / D conversion data is composed of, for example, a shift register, and the set values of MAIN / PWM are stored in the latch, and communicate with the CPU as described below.

First, FIG. 10 shows the bit configuration of the register C. Bits 0 to 3 are designated No. or M of RAM 6 or latch 17 in FIG.
Is the designated No. of PX circuit 3 and bit 4 Read?
In the case of Read, one of the eight channel inputs of the MPX circuit 3 to be A / D is indicated by the value of the RAM No. (bits 0 to 3) and stored in the latch in the timing generator 2. Also, ▲
In the case of ▼, the address or latch 17 in the RAM 6 to be D / A converted is indicated by the value of the RAM No. (bits 0 to 3). Bit 5 specifies that each output of MAIN / PWM and SUB / PWM is not output. Bit 7 is a timing signal for communication between the CPU and the timing generator. For example, when bit 7 is changed from 0 to 1, The data of 0 to 5 and the data of the register A10 become valid. In the bit configuration, the RAM No. is assigned 4 bits from bit 0 to bit 3.
In this embodiment, since there are five types of RAM 6 and eight external input channels,
Actually, 3 bits is enough.

The output value of each PWM is set in the RAM 6 or the latch 17 according to the following procedure. The CPU first addresses the register A10 and writes data corresponding to the output to be set. Next, the register C is addressed, and the RAM No. of the output to be set to bits 0 to 3, for example, 0, SUB,
If it is PWM0, write a value such as 1 and bit4 in the state of ▲ ▼ and further change the bit from 0 to 1. When MAIN / PWM is designated, that is, when 0 is set, the timing generator 2 sets the input of the selector 7 to the register A side,
The value of the register A is taken into the latch 17 by setting the output to the latch 17 side and outputting a latch pulse to the latch 17. After that, the selector 7 is shifted to the RAM 6 side. Since the RAM 6 has the shift register configuration in the present embodiment as described above, the timing generator 2 refers to the RAM No. of the register C12, and the data of the corresponding RAM No. At the same time as the output to / A5, the selector 7 which normally selects the computing unit 8 is set to the register A side, and the data of the register A is written to the RAM 6 by the next shift clock. When the above-mentioned shift lock is completed, the selector 7 selects the data on the computing unit 8 side again. Here, the arithmetic unit 8 outputs the input, that is, the output of the RAM 6 as it is, and uses it as the input of the selector 7.

As described above, the set value of each PWM output can be set in the RAM 6. Note that, when setting the MAIN / PWM data described above, it is limited to the case where the shift clock of the RAM 6 is invalid.
To set the A / D conversion address, the CPU addresses the register C and sets the channel number (0 to 0) to be A / D converted.
7) is set to bits 0-3 (actually 0-2)
When t4 is set to Read and bit 7 is changed from 0 to 1 and written, the values of bits 0 to 3 of the register C are set in the latch in the timing generator 2. The timing generator 2 supplies the channel number indicated by the latch to the MPX circuit 3 at the timing at which the A / D conversion is to be performed. At this time, the arithmetic unit 8 sets the bi to be determined based on the result of the comparator.
The data of t is set to 0 or 1 and output to the selector 7. The arithmetic unit 8 sets 1 in order from the most significant bit, repeats the above-described comparator operation, and rewrites the data in the RAM 6 until the least significant bit is determined. When the least significant bit is determined, the timing generator 2 supplies a latch pulse to the register B, stores the latch pulse as A / D conversion data in the register B, and performs the comparison operation again from the most significant bit. Only the upper bit is set to 1 and the other bits are set to 0 and written to the RAM 6 through the selector 7. C
The PU can know the A / D converted value by addressing and reading the register B.

 FIG. 11 is a block diagram of the fourth embodiment.

In this embodiment, high-speed A / D conversion is performed. FIG. 12 is an example of the timing chart. In the second embodiment, when the resolution is 7 bits, a conversion time of 7T is required (see FIG. 6). In this embodiment, the conversion can be performed at 3.5T.

When higher-speed A / D conversion is required, the operation is performed as shown in the timing chart of FIG. In this example, conversion can be performed at 7 / 4T ', that is, 7 / 3T, as shown.

〔The invention's effect〕

As described above, according to the present invention, a comparison unit required to generate control signals for a plurality of power supply circuits by comparing analog signals from the plurality of power supply circuits with a reference signal, A comparison means necessary for generating a digital signal by sequentially comparing the analog signal with a different reference signal, and a multiplexer, a comparison means, and a control signal generation means by a timing control means for also using the comparison means. In addition, each operation timing of the digital arithmetic circuit is controlled, and further, weighting is performed for each power supply circuit and the analog signal source to control the timing of the operation of each power supply circuit and the operation of analog-to-digital conversion.

This makes it possible to reduce the size and cost of the control device, and efficiently control the timing of the operation of each power supply circuit. Therefore, a plurality of power supply circuits having different response speeds can be efficiently controlled.

Further, when the power supply circuit is a pulse width modulation circuit, a plurality of power supply outputs can be obtained without generating a ripple.

In addition, since the comparison results can be sampled by turning on / off the first to third switch circuits at a predetermined timing, the comparison operation can be performed without malfunction even in the digital circuit. Since the comparison can be performed in synchronization with the operation, the comparison operation can be performed with high accuracy. Further, the dynamic range of the power supply control range and the analog / digital conversion range can be widened.

Further, a chip area can be reduced and an inexpensive image forming apparatus can be provided.

[Brief description of the drawings]

1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a timing chart of the embodiment, FIG. 3 is a circuit diagram of a comparator used in the embodiment, and FIG. 4 is a block of a MAIN / PWM circuit. FIG. 5, FIG. 5 is a block diagram of the second embodiment, FIG. 6 is a timing chart A of the timing generator, FIG. 7 is a circuit diagram of SUB0, FIG. 8 is a conceptual diagram of SUB0, and FIG.
FIG. 10 is a configuration diagram of an embodiment, FIG. 10 is a bit configuration diagram of a register C,
FIG. 11 is a block diagram of the fourth embodiment, FIG. 12 is a timing chart B of the timing generator, and FIG. 13 is a timing chart C of the timing generator. 3 Multiplexer (MPX circuit) 9 MAIN / PWM circuit 20 Analog input terminal 51 CPU core A-5 Control element (sub-transistor)

Claims (3)

(57) [Claims] 1. A control device including a control mechanism for controlling a plurality of power supply circuits, a plurality of analog input terminals for inputting analog signals from the plurality of power supply circuits and another analog signal source, and the plurality of analog inputs. A multiplexer for selecting one of a plurality of analog signals input from an end; a first reference signal for comparison with an analog signal from the power supply circuit selected by the multiplexer; and the analog selected by the multiplexer A reference signal generating means for generating a second reference signal for comparison with an analog signal from a signal source; a first switch for turning on and off an input of the analog signal selected by the multiplexer; Connected in parallel with each other, and
Or a second switch for turning on / off the input of a second reference signal, a capacitor connected in series to a parallel circuit of the first switch and the second switch, and an inverter connected in series to the capacitor. , A third switch connected to both ends of the inverter,
3 is operated at a predetermined timing to repeat charging and discharging of the capacitor, whereby the analog signal from the power supply circuit and the first reference signal or the analog signal from the analog signal source and the second reference signal Means for comparing the analog signal from the power supply circuit with the first reference signal and outputting the control signal as a control signal to one of the plurality of power supply circuits. Means for comparing the analog signal from the analog signal source with the analog signal from the analog signal source based on a comparison result of the comparing means when comparing the analog signal from the analog signal source with the second reference signal. A digital operation circuit for calculating a reference value for generating a reference signal for the reference signal and supplying the reference value to the reference signal generating means; Controlled, and in order to output the calculated reference value as a digital signal, performs weighting on the plurality of power supply circuits and each said analog signal source, the multiplexer, said comparison means, said control signal generating means,
A control device, comprising: timing control means for repeatedly controlling each operation timing of the digital arithmetic circuit. 2. The control system according to claim 1, wherein said control signal generation means generates a control signal of a pulse width modulation circuit for switching-controlling a primary side of each transformer of said plurality of power supply circuits. apparatus. 3. A control device, wherein the control device according to claim 2 is integrated on a single chip together with a microprocessor for controlling the operation of the image forming apparatus, a digital circuit such as a memory, and the pulse width modulation circuit.