JP2977342B2 - Manufacturing method of bipolar semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a bipolar semiconductor integrated circuit device, and more particularly to a method of forming an emitter portion thereof.

[0002]

2. Description of the Related Art In a field requiring high-speed operation as a use of a semiconductor integrated circuit device, an ECL / CML bipolar semiconductor integrated circuit device is generally used.
When the logic amplitude is constant in the ECL / CML system, the operation speed is determined by the elements constituting the circuit, the parasitic capacitance of the wiring, the base resistance of the transistor, and the product of the current gain bandwidth. To reduce the parasitic capacitance, the base electrode is drawn out of the element region using polycrystalline silicon to reduce the base area, especially in order to reduce the junction capacitance between the base and collector of the transistor, which greatly contributes to the operating speed. In addition, a method of forming a polycrystalline silicon resistor and a metal wiring on a thick isolation oxide film has been generally adopted.

To improve the current gain bandwidth product, it is effective to make the emitter and base junctions shallower and to make the collector epitaxial layer thinner.

The propagation delay time T _pd (ECL) of the ECL circuit
Is generally represented by the following equation.

[0005] _{t pd (ECL) = r bb} [AC TC1 + C d1] + [C TS1 + C de1] * V S / I CS here, r _bb ... the base resistance, C _TC1 ... collector-base junction capacitance, C _d1 ... diffusion capacitance of input transistor, C
_{TS1 represents the} junction capacitance between the collector and the substrate, C _{de1 represents} the diffusion capacitance of the output emitter follower transistor, V _{S represents the} logic amplitude voltage, I _{CS represents the} current switch current, and A represents the voltage amplification factor of the current switch circuit.

[0006] reduction of the apparent from the above equation Uri propagation delay time, increase of reduction and I _CS of parasitic resistance and parasitic capacitance is found to be effective.

[0007] Here, by increasing the I _CS to the second term on the right side of the equation is generally carried out at ultra high speed ECL circuit, it is possible to reduce. But,
Even in this case, the delay time according to the first term cannot be reduced.

Therefore, an ultra-high-speed ECL with high power consumption
To further increase the speed of the circuit, it is important to reduce the first term. In particular, the effect of the collector-base junction capacitance is large, and reduction is desired.

As a prior art proposed for the purpose of realizing these matters, the writer has disclosed a technique disclosed in Japanese Patent Application No. 3-94169.
FIGS. 3 and 4 show the manufacturing method proposed in the above-mentioned publication, and will be described below.

As shown in FIG. 3A, a single crystal silicon (303) containing phosphorus at about 10 ¹⁶ / cm ³ at 950 ° C. and about 40 Torr on a buried diffusion layer (302) of antimony or the like.
After about 0.8 μm is epitaxially grown, an element isolation oxide film (304) is formed, and then an oxide film (305) of about 3000 ° is formed on the entire surface. Thereafter, only the oxide film of the collector electrode portion is removed by a known photolithography and etching technique. Thereafter, polycrystalline silicon (306) of about 3000 ° is formed. Next, a silicon nitride film (307) is formed thereon by a CVD (chemical vapor deposition) method, and this is selectively left on the base electrode and the collector electrode by a known photolithography and etching technique (307a). , 307b, 307c).
At this time, no nitride film exists on the emitter. Here, (301) is a P ^- type silicon substrate, (302)
Is an N ⁺ type region, (306) is polycrystalline silicon, (3
07) indicates silicon nitride films, respectively.

Subsequently, silicon nitride films (307a, b,
The polycrystalline silicon (306) is selectively oxidized using c) as a mask. The polycrystalline silicon (3a) is formed by the polycrystalline silicon oxide film (308a, b, c, d).
06a, b, c) are separated. (FIG. 3
(B)) Subsequently, after selectively removing only the silicon nitride film (307c) on the polycrystalline silicon (306c), the polycrystalline silicon (306c) has a dose of 10 ¹⁶ / cm ³ and an acceleration energy of about 200 keV. Then, phosphorus is ion-implanted and heat treatment is performed to form an N ⁺ type collector electrode lead-out region.

Further, silicon nitride films (307a, b)
Through polycrystalline silicon (306a, b) to 10 ¹⁵ /
Ion implantation of about ² cm ² of boron. Next, only the polycrystalline silicon oxide film (308b) on the emitter formation region is selectively removed.

Next, silicon is selectively deposited near the emitter formation region by a hydrogen reduction reaction of dichlorsilane at 800 ° C. and about 20 Torr. At this time, a single crystal grows directly above the emitter by epitaxial growth,
Polycrystalline silicon is produced on the surrounding polycrystals and these are continuously bonded. During the vapor phase growth, by mixing an appropriate amount of diborane, one boron is contained in the deposited film.
Mix at a high concentration of 0 ¹⁸ to 10 ¹⁹ / cm ³ . Thus, a P-type epitaxial base (310) is formed.
(FIG. 3 (C)) Since this base is selectively grown at a low temperature of about 800 ° C., boron hardly diffuses into the N ⁻ -type epitaxial layer, and the bottom of the base to the collector region having a boron concentration which is problematic in ion implantation. No spread, that is, no tail occurs.

Thereafter, a silicon oxide film (311) is formed on the entire surface by low pressure CVD at about 2000 to 3000 °. (FIG. 4D) Thereafter, the silicon oxide film (311) is entirely etched back by using a reactive ion etching method, and a polycrystalline silicon oxide film is formed by using the nitride film (307a, 307b). A sidewall oxide film (31)
1a, 311b), and a fine emitter window is opened on the selectively grown single crystal silicon by self-alignment reduction. (FIG. 4E) Next, arsenic-doped polycrystalline silicon (312a, 312a)
b) is formed, and the emitter (31) is diffused therefrom.
Form 3).

Further, after forming the insulating film (314),
Open the contacts and open the metal electrodes (315a, b, c,
d) is formed. (FIG. 4 (F)) As described above, according to this method, a polycrystalline silicon base electrode is formed on a thick oxide film, and this is connected to a future active base region by selective epitaxial growth. As a result, the area of the inert base was significantly reduced. As a result, the junction capacitance component due to the PN junction between the inert base and the N-type epitaxial layer, that is, the base-collector junction capacitance can be significantly reduced, and the high-speed performance of the transistor can be improved.

[0016]

However, even the device obtained by using the above-mentioned manufacturing method has the following problems in order to further improve the performance.

That is, the polycrystalline silicon oxide film (308b)
After the formation, the oxide film and the oxide film immediately thereunder (305)
When etching the polycrystalline silicon (306a, 30
In order to expose the side wall of 6b), isotropic etching using a buffered hydrofluoric acid solution or the like is required. At that time, since it is necessary to surely expose the N ⁻ type epitaxial layer (303),
Normally, it is necessary to perform over-etching of at least about 10 to 20% with respect to the total thickness of both the polycrystalline silicon oxide film (308b) and the oxide film (305) immediately below. Therefore, the opening end (31a) of the oxide film is compared with the opening end (316a, 316b) of the polycrystalline silicon shown in FIG.
7a and 317b) are largely retreated by side etching of the oxide film. As a result, as shown in FIG. 3D, the N ⁻ -type epitaxial layer (303) and the P ⁺ -type epitaxial layer (3
10), there is a problem that the area of the base junction formed by the method cannot be sufficiently reduced as expected.

In order to reduce the parasitic capacitance between the base and the collector, the oxide film 305 is preferably made as thick as possible. On the other hand, the P ⁺ -type epitaxial layer (310) for forming the shallow junction base is formed at a high speed. It is preferable to make it thinner for the purpose of forming a thin film. However, since it is necessary to connect the polycrystalline silicon layers (306a, 306b) and the N ⁻ type epitaxial layer (303) by the P ⁺ type epitaxial layer (310) formed by the selective epitaxial growth technique, the oxide film (305) is eventually formed. The thickness of the P ⁺ -type epitaxial layer (310) could not be set independently, and there was no other way to find a compromise between the two. Thus there is a major disadvantage of giving reduction and the parasitic capacitance between the base and collector in the conventional method, a restriction to f _T improvement by shallow junction base form.

Furthermore since the conventional method for forming a base region in P ⁺ epitaxial layer (310) N ^- -type epitaxial layer (303) there is no need to form a base into, N ^- -type epitaxial layer (303) regions of the Although the structure can be reduced in area, the element isolation oxide film is still required, and the alignment margin of the element isolation oxide film region (304) with respect to the N ⁺ region (302) and the element isolation oxide film region (304) The alignment margin of the nitride film pattern (307) formation region cannot be reduced, and there is a limit to the reduction of the element area, that is, the reduction of the junction capacitance between the collector substrates. In the separation step, the N ⁺ region (30
2), the formation of an N ⁻ -type epitaxial region (303), and the formation of an element isolation oxide film region (304) are required, which requires a complicated isolation process similar to the conventional one.

The present invention has the problems that the base junction area is not sufficiently reduced due to the side etching of the oxide film as described above, and that the oxide film thickness and the P ⁺ epitaxial layer film thickness cannot be set independently, thereby increasing the speed. Bipolar semiconductor with excellent high-speed performance that eliminates the problems that limit the device size and further promotes the self-alignment of the device isolation process and device formation process, enabling the reduction of device area and parasitic capacitance. An object of the present invention is to provide a method for manufacturing an integrated circuit device.

[0021]

According to the present invention, there is provided a method of manufacturing a bipolar semiconductor integrated circuit device, comprising the steps of: forming an oxide film, a polycrystalline silicon film on a substrate surface having a crystal orientation (111) in which an N ⁺ region is formed; After forming an opening in a region where the base of the three-layer film is to be formed, alkali etching such as KOH is performed to form a side surface of the polycrystalline silicon layer on the side wall of the opening. Etching followed by N ^- type selective epitaxial growth
After backfilling the opening portion, the N said nitride film as a mask ^- -type is selectively oxidized part of the selective epitaxial regions, likewise P ⁺ -type selective and conventional methods then the removal of the selective oxide regions In this case, an epitaxial base layer is formed.

[0022]

The present invention employs the above-described method to produce the following effects.

(1) The opening of the oxide film and the selective oxidation region are self-aligned, so that the oxide film opening is not side-etched when the selective oxide film is removed, so that a base-collector junction area is required. The base-collector junction capacitance can be sufficiently reduced without being expanded as described above.

(2) Since the thickness of the oxide film and the thickness of the P-type epitaxial base layer can be set independently, the parasitic capacitance between the base and the collector can be sufficiently reduced.
And it is possible to sufficiently achieve the improvement of f _T by shallow junction of the base layer.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 (A) to 1 (H) are process sectional views showing an embodiment of the present invention.

First, a silicon (Si) substrate (101) whose main crystal plane is the (111) plane is coated with N such as antimony.
⁺ After forming the buried diffusion layer (island-like region) (102), the entire surface is thermally oxidized or CVD to a thickness of, for example, 0.5 μm.
A first oxide film (103) is formed as an insulating film having a thickness of about 0.3 μm, and a first polycrystalline silicon layer (104) having a thickness of about 0.3 μm, for example, and a thickness of about 0.2 μm, for example. Nitride film (105) as oxidation resistant film
Are sequentially formed.

Next, as shown in FIG. 1A, an opening (106) having a width of about 1 μm and having a substantially vertical side wall is formed in a region where a base is to be formed by a known photolithography and etching technique.

Next, as shown in FIG. 1B, the first polycrystalline silicon layer (104) is side-etched from the side wall of the opening (106) using an alkaline etching solution such as KOH. Overhangs 107a and 107b, which are substantially the same as the thickness of the oxide film 103 (about 0.5 μm). The alkali Si etch rate of KOH or the like is extremely lower than the single-crystal Si on the crystal plane (111), and the N ⁺ region (102) exposed during the side etching of the first polycrystalline silicon (104). ) Is hardly etched.

Next, silicon is selectively deposited in the opening 106 by a hydrogen reduction reaction of dichlorsilane at 800 ° C. and about 20 Torr. At this time, single-crystal silicon (108) grows from the bottom surface of opening 106, and polycrystalline silicon (109a, b) grows from the side wall of first polycrystalline silicon (104). The connection is made, resulting in the structure shown in FIG. By mixing an appropriate amount of phosphine during the vapor phase growth, about 10 ¹⁶ to 10 ¹⁷ cm ^-3 of phosphorus is mixed into the deposited film to form an N ⁻ -type epitaxial layer.

Subsequently, using the silicon nitride film (105) as a mask, a part of the N ⁻ -type single crystal silicon (108) and a part of the polycrystalline silicon regions (109a, 109b) are selectively oxidized. A second oxide film (110) is formed. In this selective oxidation step, the second oxide film 110 is preferably controlled to a thickness that does not reach the first oxide film 103, for example, about 0.5 μm.

Next, through a silicon nitride film (105),
Boron of about 10 ¹⁵ / cm ² is ion-implanted into the first polycrystalline silicon (104). Then, a second oxide film (110)
Is selectively removed.

Subsequently, the second oxide film (11) is subjected to a hydrogen reduction reaction of dichlorosilane at 800 ° C. and about 20 Torr.
0) Selective silicon (0.1 to 0.2 μm) in the removal area
m) is deposited. At this time, a single crystal is grown immediately above the emitter by epitaxial growth, and polycrystalline silicon is generated on the surrounding polycrystal, and these are continuously bonded.
During the vapor phase growth, an appropriate amount of diborane is mixed in, so that boron is mixed into the deposited film at a high concentration of 10 ¹⁸ to 10 ¹⁹ / cm ³ . Thereby, as shown in FIG. 2E, a P-type epitaxial base layer (111) is formed. This epitaxial base layer (111) has a thickness of 800
Since the selective growth is performed at a low temperature of about ° C., there is almost no diffusion of boron into the N ⁻ -type epitaxial layer (108), and a base region with a high-concentration shallow junction can be formed. Thereafter, a first CVD oxide film (11
2) is generated at about 0.2 to 0.3 μm.

After that, the first CVD oxide film (112) is entirely etched back by the reactive ion etching method, and the second oxide film removal area is removed by using the silicon nitride film (105). As shown in FIG. 1 (F),
The side wall oxide films (113a, 113b) are formed and the single crystal silicon (11
1) A fine emitter window is opened on the top by self-alignment shrinkage.

Next, as shown in FIG. 1 (G), a pattern of base electrode polycrystalline silicon (114a, 114b) is formed by known photolithography and etching techniques.
Further, an opening (115) for taking out a collector electrode is formed in the first oxide film (103) by known photolithography and etching techniques.

Next, as shown in FIG. 1H, an arsenic-doped second polysilicon layer (116a, 116b) is formed, and the emitter (117) is diffused from the 116a.
To form Also, 116b serves as a collector extraction electrode.

After the formation of the insulating film (118), the contact is opened and the metal electrodes (119a, 119b, 11b) are opened.
9c and 119d) are completed to complete the bipolar transistor portion according to the present embodiment.

[0037]

As described in detail above, according to the present invention, a three-layered film of a thick oxide film, polycrystalline silicon, and a silicon nitride film is formed after forming an N ⁺ region using a (111) substrate. Forming an opening in a region where a base of the three-layer film is to be formed, side-etching the polycrystalline silicon layer with an alkaline etchant, and selectively performing epitaxial growth in the opening; Is used as a mask, selective oxidation is performed on the epitaxial growth region so as not to reach the thick oxide film, and thereafter, after removing the selective oxide film, a base and an emitter are formed in the selective oxide film removed region. The following effects can be expected.

(1) The thick oxide film (first oxide film 10)
3) The opening and the selective oxidation region are self-aligned, and the thick oxide opening is not side-etched when the selective oxide film is removed, so that the base-collector junction area is increased more than necessary. Therefore, the base-collector junction capacitance can be sufficiently reduced.

(2) The thick oxide film (the first oxide film 10)
Since the thickness 3) and the thickness of the P-type epitaxial base layer can be independently set, the parasitic capacitance between the base and the collector can be sufficiently reduced, and the f _T Can be sufficiently improved.

(3) Since the collector region is formed of the selective epitaxial layer (108), the conventionally required isolation oxide film (304 in FIG. 3) becomes unnecessary, and as a result, the position of the isolation oxide film region is reduced. Since the photolithography step for determining the threshold voltage is not required, and it is not necessary to secure a margin for mask alignment, the area of the N ⁺ region (102) can be greatly reduced, and the parasitic capacitance C _TS between the collector and the substrate can be greatly reduced. Can be reduced.

(4) The lead region of the collector electrode is N ⁺
Since the collector electrode polycrystalline silicon (116b) is formed directly on the region (102), the N ⁺ diffusion step for reducing the collector resistance becomes unnecessary, and the isolation oxide film becomes unnecessary. This eliminates the need for a selective oxidation step for forming the semiconductor layer, thereby simplifying the process.

As described above, according to the present invention, the base
Since the parasitic capacitance between the collector and the parasitic capacitance between the collector and the substrate can be greatly reduced, and the base / epitaxial layer can be made thinner, the f _T can be greatly improved and the propagation delay time t _pd can be reduced. A significant improvement can be expected.

[Brief description of the drawings]

FIG. 1 is a process sectional view of an embodiment of the present invention (part 1).

FIG. 2 is a process sectional view of an embodiment of the present invention (part 2).

FIG. 3 is a sectional view of a process of the prior art (part 1).

FIG. 4 is a sectional view of a process of the related art (part 2).

[Explanation of symbols]

103 first oxide film 104 first polycrystalline silicon film 105 nitride film 106 opening 107 overhang 108 N ^- type single crystal silicon 109 polycrystalline silicon region 110 second oxide film 111 p-type epitaxial layer 112 CVD oxide film 113 Sidewall oxide film

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/68-29/737 H01L 21/33-21/331

Claims (3)

(57) [Claims] (A) An island region of a first conductivity type is formed on one main surface of a semiconductor substrate, and an insulating film and a first
Forming a three-layer film comprising a polycrystalline semiconductor film and an oxidation-resistant film, providing an opening in a selected region of the three-layer film, and exposing a part of the island region; and (b) A step of selectively forming a first-conductivity-type single-crystal semiconductor layer in the exposed region and back-filling the opening so as to be connected to the first polycrystalline semiconductor film; Forming a selective oxide film by selectively oxidizing the selectively formed single-crystal semiconductor layer using the chemically active film as a mask; and (d) removing the selective oxide film. A method for manufacturing a bipolar semiconductor integrated circuit device. 2. A semiconductor substrate having a main surface whose crystal plane is (111) in plane direction, an opening is provided in a selected region of the three-layer film, and a part of the island region is exposed. 2. The method according to claim 1, further comprising the step of side-etching the first polycrystalline semiconductor layer exposed on the inner wall of the opening after the step. 3. The bipolar semiconductor according to claim 1, wherein when selectively oxidizing the selectively formed single crystal semiconductor layer, the selective oxide film is formed so as not to be connected to the insulating film. A method for manufacturing an integrated circuit device.