JP2977837B2 - Time-division multiplex receiver with adaptive array - Google Patents

Description

The present invention relates to a time-division multiplex receiving apparatus with an adaptive array,
In particular, the present invention relates to a receiving device used in a time division multiplex wireless communication system in land mobile communication.

[Prior art] In land mobile communications, transmission speeds are several hundred kbps, as represented by a wideband TDMA (Time Division Multiple Access) system.
When performing the above communication, the communication quality is significantly degraded due to frequency selective fading.

Frequency-selective fading is caused by the fact that incoming waves having various delay times come from various directions, and the received waves are subjected to complicated intersymbol interference.

For this reason, the conventional receiver uses an adaptive equalizer as a measure against selective fading. The adaptive equalizer is a technology that has a plurality of taps on a time axis, weights tap inputs, and combines them to remove distortion such as intersymbol interference.

[Problems to be Solved by the Invention] An adaptive equalizer is a technique suitable for reducing intersymbol interference. However, when the delay time of the delay wave increases or the symbol length decreases due to the increase in the transmission rate, the ratio of the delay time of the delay wave to the symbol length increases, and the circuit scale required for equalization increases. . For example, even in a metropolitan area where the maximum delay time is relatively small, the maximum delay time is several μs.
Therefore, when the transmission speed is several hundred kbps or more, it is difficult to realize the device.

On the other hand, there is an adaptive array technique as another measure against selective fading. The adaptive array is a technique for controlling the directivity and suppressing the influence of a delayed wave by weighting and combining a plurality of spatially arranged antenna inputs. Further, as the delay time of the delayed wave increases, the correlation with the direct wave decreases, and the characteristic of suppressing the delayed wave is improved. Therefore, the size of the apparatus is not dependent on the delay time of the delay wave, and is particularly effective when the transmission speed is high.

However, when realizing an adaptive array device, since processing is conventionally performed in the IF and RF bands, it is difficult to perform processing using a complicated algorithm, and it has not yet been put to practical use as a land mobile communication system.

Accordingly, a main object of the present invention is to realize a time-division multiplex receiving apparatus employing an adaptive array apparatus as a measure against selective fading.

A specific object of the present invention is that when digital signal processing is applied to a signal processing unit, the processing speed of a current digital signal processing processor (abbreviated as DSP) is high speed (several tens of kbps or more).
Processing of complex control continuously and in real time for the data of

When the accumulated batch demodulation is performed by using the time when unnecessary data is transmitted, an output clock recovery circuit is simply realized.

Further, in land mobile communication, since the electric field strength fluctuates greatly due to fading, AGC (automatic gain control) must be used from the viewpoint of securing a dynamic range during A / D conversion. Moreover, in the case of an adaptive array device, the control of the AGC gain in each branch is closely related to the algorithm of the adaptive array, and is a large parameter that affects the characteristics. Therefore, a method of controlling the AGC gain of each branch of the adaptive array should be established. It is another object of the present invention to improve the stability and capture of flake synchronization in a TDMA system.

Means for Solving the Problems In order to achieve the above object, the present invention applies an adaptive array technique as a measure against selective fading to improve signal quality when delay time is large. Therefore, the time division multiplex receiving apparatus is constituted by the following constituent means.

A plurality of branches in which a receiving antenna, a frequency conversion circuit, an AGC circuit, a quadrature detector, and an A / D converter are sequentially connected; and a plurality of memories that store a complex baseband signal output from the A / D converter. An adaptive array processing unit that adaptively combines the data of the plurality of memories and controls so that the output after the combining is always optimal; and demodulates data from the adaptive array processing unit and continuously outputs the demodulated burst data. A data conversion unit to output the selected branch, a branch having the maximum level is selected from the complex baseband signals of the plurality of branches, and the AGC gains of the plurality of branches are determined from the level of the selected branch. A maximum power branch detection circuit to be fed back, and a power of a signal of a branch selected by the maximum power branch detection circuit being fixed by a limiter. Calculating a complex correlation between the limiter output signal and a known frame synchronization waveform, outputting a frame synchronization signal based on a threshold determination, and multiplying the frame synchronization signal, smoothing by a PLL, and outputting external data. And a clock recovery circuit for recovering a clock for use.

[Operation] According to the present invention, a signal subjected to quasi-synchronous detection by a plurality of branches is subjected to digital signal processing by a DSP in a baseband, so that it is possible to perform complicated signal processing in a control unit of an adaptive array.

In the case of a time-division multiplex receiving system, real-time processing can be performed with an existing DSP by performing the accumulation batch demodulation method using the time when unnecessary data is transmitted.

In the case of an adaptive array device,
AGC gain control is closely related to the adaptive array algorithm and is a large parameter that affects the characteristics.However, the maximum power branch detection circuit controls the AGC gain of each branch in common, so the input signal of the adaptive array The linearity of is maintained.

In addition, since a frame synchronization signal is used for reproducing the output clock which is a problem in the case of accumulation batch demodulation, a dedicated circuit is not required.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a time division multiplex receiving apparatus with an adaptive array according to the present invention. Here, a system configured with n antennas will be described as an example.
Each of the n antennas 1-i (i = 1, 2, 3,..., n and below) is converted into an IF band by a frequency conversion circuit 3-i, and then gain is adjusted by an AGC circuit 4-i. At this time, the feedback amount F of the AGC output that determines the AGC gain
Are common, and the feedback amount F is determined using the maximum input power in all the branches 5-i. This allows
The signal after AGC between the branches maintains the linearity and the dynamic range at the time of A / D conversion is maintained.

The signal after AGC is converted to a quadrature detector 7 using a local oscillator 8.
Quasi-synchronous detection is performed at -i. Further, after being converted into digital values I1, Q1... In, Qn by the A / D converter 9, the digital values are sent to the adaptive array processing unit 11.

On the other hand, the maximum power branch detection circuit 10 outputs the complex baseband signals (I1, Q1) of the n branches after the A / D conversion.
Branches (Imax, Qma) with the highest power among (In, Qn)
x), apply a limiter 17 to the signal,
The frame synchronization word is detected by the frame synchronization unit 18 and the frame synchronization signal SF is output.

This frame synchronization signal SF is applied to the adaptive array processing unit.
11, is used as a synchronization signal for the demodulation unit 22 and the data conversion unit 23, and is also multiplied by the clock recovery circuit 24 to become the data output clock CLK.

The complex baseband signals (I1, Q1)... (In, Qn) sent to the adaptive array control unit 11 are stored in the memory 6 for one desired frame.

Further, each signal processing unit 1 is controlled by the frame synchronization signal SF.
Processing of 1, 22, and 23 starts, and the adaptive array processing unit 1
1 reads data from the memory 6 and performs processing, and thereafter, the demodulation unit 22 and the data synchronization word detection / data output 23
And each process is processed by a pipeline. By using a digital signal processing processor for these, complicated signal processing can be easily performed.

FIG. 2 shows a time chart of the accumulated batch demodulation. In the case of a TDMA system in which one frame is composed of n slots, even if the control cannot be performed in the time 30 in which the desired slot # 1 is transmitted, the time Tf in which data for one frame is transmitted by accumulated batch demodulation is used. Further, by using the pipeline processing together, the processing of the adaptive array control 32, the demodulation 33, and the data conversion 34 can be performed in real time.

FIG. 3 shows a block diagram of another embodiment of the time division multiplex receiving apparatus according to the present invention. Here, the slot structure of the transmission signal is shown in FIG. Transmission data with a channel transmission speed of 8 kbps is divided into blocks (70) every 384 bits, and multiplexing of 24 channels is performed. The transmission speed is 256kbps and each slot has 3
FS, PR, DS, GS, etc. added to the header of 84-bit information IW
Consists of 512-bit data. At this time, one frame length is 48 msec, and one slot length is 2 msec. Note that a PN code is used for the frame synchronization word FS.

The modulation method is GMSK (Gaussian filtered minimum shift keying "Gaussian filtered Minimum Sh
"ift Keying") and a CMA (Constant Modulus Algorithm), which is an algorithm suitable for constant envelope modulation, is applied as a control algorithm for the adaptive array.

As shown in FIG. 3, in this embodiment, four antennas Ii (i = 1, 2, 3, 4) are arranged, and four frequency conversion units are provided. The received signal is supplied to the first IF conversion circuit 3-
The frequency is converted by the 1-i and the second IF conversion circuit 3-2-i, and the noise is removed by the reception filter 12-i. Further, each received signal is subjected to AGC4-i in order to secure a dynamic range at the time of A / D conversion.

At this time, in order to equalize the AGC gain of each branch, the maximum power branch detection circuit 10 calculates the electric field strength of the maximum branch of each branch, and outputs the common feedback signal F of the AGC of each branch.

The detailed configuration of the maximum power branch detection circuit 10 is shown in FIG. Signals Ii and Qi of both I and Q channels of each branch are stored in ROM13.
-Input to i and the envelope value Is output. The envelope value R of each branch is compared in magnitude by the comparator 14, and the maximum power branch is detected.

The branch selection circuit 19 selects the maximum power branch based on the signal indicating the maximum power branch, and outputs signals Imax and Qmax of each of the I and Q channels. Further, the feedback value F of the AGC gain is determined by averaging the envelope value Rmax of the maximum power branch output from the comparator 14 by an integrator.

The IF signal output from the AGC circuit 4-i in FIG. 3 is obtained by using a non-regenerated carrier generated by the local oscillator 8,
The quasi-synchronous detection is performed by the quadrature detector 7-i to be a complex baseband signal. The complex baseband signal is converted into digital values Ii and Qi by an A / D converter 9 having a sampling frequency of 1 MHz (4 samples per bit) for each branch.

The complex baseband signals (Ii, Qi) digitized by the A / D converter 9 are sent to the CMA processing unit 20, and the correlation processing is performed by the frame synchronization unit 18 via the maximum branch detection circuit 10.

FIG. 6 shows the configuration of the frame synchronization unit 18. A PN code is used for the frame synchronization word, and a frame synchronization signal SF is generated by a correlation process. In the present embodiment, this correlation processing is performed by digital signal processing by the DSP 28.

The maximum branch I-channel signal Imax output from the maximum power branch detection circuit 10 is standardized by the ROM 25 using the maximum power branch envelope value Rmax (Imax / Rmax).
Is performed. Similarly, the Q-channel signal Qmax is also standardized, and the DSP 28 has a complex baseband signal (Imax, Qmax).
Is input with a limiter.

In DSP 28, the complex signal output from ROMs 25 and 26 and RO
A correlation value between the frame synchronization word stored in M27 and the complex waveform data is calculated.

The correlation value SR calculated by the DSP 28 is subjected to threshold determination in the ROM 29. At this time, since the power of the input signal of the DSP 28 is constant, the threshold value for detecting the frame synchronization signal can be constant.

The frame synchronization signal SF for which the threshold value has been determined is used as a trigger of each signal processing unit. Also, the frame synchronization signal
Since the SF period is 48 ms, the frame synchronization signal is multiplied by the multiplier 35 and smoothed by the PLL (phase synchronization circuit) 36 to reproduce the 8 kHz external output clock CLK.

In FIG. 3, the complex baseband signals (Ii, Qi) sent to the CMA processing unit 20 are processed by accumulated batch demodulation.

FIG. 7 shows the configuration of one embodiment of the CMA processing unit 20. The data (Ii, Qi) sent to the CMA processing unit 20 has a desired slot for DPRAM (Dual Port RA “Dual Port RA”).
M ") 40-i. Then, the frame synchronization unit 18
, The signal of each branch is taken into the corresponding DSP 41-1 and weighted by an algorithm called CMA.

The weighted signals are slave DSPs 41-2 ... 41-4
Is sent to the DSP 41-1 via the FIFO (First In First Out "First In First Out") 42. The host DSP 41-1 synthesizes the signal from each DSP,
The combined signals Y _I and Y _Q are output. Furthermore, the host DSP41-
1 calculates an error signal and outputs it to the slave DSPs 41-2 ... 41-4 via the FIFO 42-i-1. And each DSP 41-1
And 41-2 ... 41-4 update the weighting value with the error signal.

In the CMA processing unit 20, processing is speeded up by performing processing in parallel by four DSPs.

The synthesized signal Y _I output from the CMA processing unit 20 in FIG.
And _YQ are sent to demodulation and data conversion units 22 and 23.

FIG. 8 shows the configuration of the demodulation 22 and the data conversion unit 23. cm
The data Y _I and Y _Q from the A processing unit 20 are stored in the DPRAM 43-1.
, And 43-2, and the carrier wave and the clock are reproduced by the Costas loop realized by digital signal processing in the baseband.

The phase-compensated I and Q channel signals, Q channel signal and GMSK synchronous detection clock are DPRAM 45-1, 4
Output to the DSP 46 via 5-2 and 45-3. The DSP46 performs GMSK synchronous detection, and the demodulated data is stored in the DPRAM47.
Is output to the DSP 48 via the. The DSP 48 extracts only the information bits from the data sent in a burst, and continuously outputs the same with the external output clock CLK reproduced by the frame synchronization unit 18. At this time, the FIFO 349 is used as a buffer to absorb the jitter of the external output data clock CLK.

The plurality of DSPs 44, 46, and 48 and the host DSP 41-1 of the CMA processing unit 20 perform data transfer via the DPRAM, and speed up the processing by pipeline processing.

[Effect of the Invention] By applying digital signal processing to the control unit of the adaptive array, it is possible to manufacture an apparatus capable of performing complicated signal processing.

On the other hand, since the frame synchronization signal is used to reproduce the output clock, which is a problem in the case of accumulated batch demodulation, the necessity of separately preparing a conventional clock recovery circuit is eliminated.

In addition, the control of the AGC gain to secure the dynamic range during A / D conversion is based on the common method of each branch, and the relationship between the input signals of the adaptive array becomes equal to that before AGC, which affects the control of the adaptive array. Absent. According to the above invention, it is possible to reduce the influence of frequency-selective fading that occurs in a TDMA receiver that requires high-speed transmission, and to perform frame synchronization that is resistant to fading.

[Brief description of the drawings]

1 and 3 are configuration diagrams of an embodiment of a time division multiplex receiving apparatus according to the present invention, FIG. 2 is a time chart of accumulated batch demodulation, FIG. 4 is a time slot configuration diagram of signals in a TDMA system, FIG. 3 is a diagram showing the configuration of the maximum power branch detection circuit 56 in FIG. 3, FIG. 6 is a diagram showing the configuration of the frame synchronization unit 61 in FIG. 3, and FIG. 7 is a CMA processing unit 57 in FIG.
FIG. 8 is a block diagram of the demodulation unit and the data conversion processing unit 64 in FIG. 1: receiving antenna, 3: frequency conversion circuit, 4: AGC circuit, 5: branch, 6, 42, 49: memory, 7: quadrature detector for quasi-synchronous detection, 8: local oscillator, 9: A / D converter , 10: maximum power branch detection circuit, 11: adaptive array processing unit, 13, 25, 2
6, 27, 29: ROM, 14: comparator, 17: limiter, 18: frame synchronization unit, 19: maximum power branch selection circuit, 20: CMA processing unit, 2
2: demodulation unit, 23: data conversion unit, 28, 41, 44, 46: DSP, 35:
Multiplier, 36: PLL, 40, 43, 45, 4745: DPRAM.

Continued on the front page (72) Inventor Seiichi Sampei 4-2-1 Nukikitamachi, Koganei-shi, Tokyo Inside the Communications Research Laboratory, Ministry of Posts and Telecommunications (72) Inventor Yoshihide Kamio 4-2-1 Nukikitamachi, Koganei-shi, Tokyo Within the Communications Research Laboratory, Ministry of Posts and Telecommunications (72) Inventor Takanori Shimura 1-280, Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kunito Usui 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-109382 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01Q 3/26

Claims (1)

(57) [Claims] 1. A plurality of branches in which a receiving antenna, a frequency conversion circuit, an AGC circuit, a quadrature detector, and an A / D converter are sequentially connected, and a complex baseband signal output from the A / D converter is stored. A plurality of memories to adaptively combine data from the plurality of memories, and demodulate data from the adaptive array processing unit and the adaptive array processing unit for controlling the combined output to be always optimal;
A data converter for continuously outputting the burst data after demodulation, and selecting a branch having a maximum level from the complex baseband signals of the plurality of branches, and selecting an AGC of the plurality of branches from the level of the selected branch. A maximum power branch detection circuit that determines a gain and feeds back in common; a power of a signal of a branch selected by the maximum power branch detection circuit is fixed by a limiter, and a complex between the limiter output signal and a known frame synchronization waveform is determined. Calculate the correlation,
An adaptive array, comprising: a frame synchronization section that outputs a frame synchronization signal based on a threshold value determination; and a clock recovery circuit that multiplies the frame synchronization signal and smoothes the data by a PLL to recover a clock for external data output. With time division multiplex receiver.