JP2978656B2 - Semiconductor integrated circuit test apparatus and test method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test apparatus, and more particularly to a load capacitance connection circuit for measuring terminals and a load capacitance connection circuit .
Related to the measurement method .

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional semiconductor integrated circuit test apparatus main body (hereinafter referred to as a tester) 2 is a measuring socket for electrically extracting a terminal 29 of a semiconductor integrated circuit 30 (hereinafter referred to as a device). 3 and the contact 26 on
Furthermore, the measuring pin 2 of the tester 2 is
7 is connected. If the state of the terminal 29 of the device 30 is the input state, the relay 24 is turned on on the tester 2 side,
The driver 4 is connected, a signal is input, and if it is in the output state, the relay 25 is turned on, the comparator 5 is connected, the output signal is measured, and an electrical characteristic test according to the operation state of the device is performed.

[0003]

When assuring the characteristics of the device in the evaluation and measurement by the tester, it is necessary to add a capacitance load in the specification and perform the measurement. In the above-described conventional tester, the insufficient capacitance 8 is added to the measurement substrate 1 in addition to the parasitic capacitances 7, 32, and 33 on the line. However, it is difficult to accurately calculate the parasitic capacitance value, and there is also a large variation in the wiring length and the like. Since the correction capacitance value can only be given as a rough value, the load varies greatly at each terminal. At present, accurate measurement has not been possible even with the development of an accurate tester.
In addition, since a capacitance is added for each product type, measurement board, and measurement terminal, the cost of the measurement board increases, and the number of components including the product type and the number of boards increases.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide a semiconductor integrated circuit test device capable of measuring with high accuracy.

[0005]

According to a semiconductor integrated circuit test apparatus of the present invention, an external connection terminal of a measurement substrate on which a semiconductor integrated circuit is set is connected to a measurement pin of a semiconductor integrated circuit test apparatus main body. in the semiconductor integrated circuit testing apparatus for testing at the body side, and a variable capacitance, measuring
Means for charging the load capacity associated with the
Distributed charge to the load capacitance and the variable capacitance
Means, and the load capacitance is determined by the result of the charge distribution.
And means for seeking . Also, the measurement system
The parasitic capacitance added to the
The measurement system wiring
The upper potential is raised to the first potential and the load capacity is charged.
Power, then set the desired capacitance value in advance,
Connect the correction capacitor discharged to ground potential to the wiring
Distribution of the electric charge charged to the load capacitance,
The potential of the capacitor of the comparator portion
The potential of this second potential is changed to
Data from the first potential to the second potential
The load capacity is obtained from the amount of change to. In addition, measurement
The parasitic capacitance added to the system and the
The load on the measuring system is taken as the load capacity of the
The potential on the line is raised to the first potential, and the load capacitance is increased.
Charge the battery and measure the rate at this time with the comparator.
Next, discharge this potential to a predetermined value, and then
Set to the desired capacitance value, and the supplement that has been discharged to ground potential
Connect a positive capacity to the wiring and charge again.
The rate of potential rise is measured by the comparator, and the
The load capacity is determined from the difference between the rate and the rate.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit test apparatus according to a first embodiment of the present invention.

As shown in FIG. 1, in this embodiment, a contact 26 on a measuring socket 3 is connected to a terminal 29 of a device 30.
The signal is taken out by the
Is connected to the measuring pin 27 of the tester 2 and relays 34 to
37, a driver 4, a comparator 5,
The variable additional capacitance 38 and the DC power supply 39 are connected.

In this embodiment, in a test apparatus for a semiconductor integrated circuit, an arbitrary capacitance is added to each measurement terminal to perform measurement.

Next, the setting of the correction capacitance 38 according to this embodiment will be described with reference to the timing chart of FIG. In FIG. 2, first, the DC power supply 39 is set to a constant level V1, then the relay 35 is turned on, and the comparator 5 is turned on.
Connect. At this time, the load capacitance on the measurement line is the parasitic capacitance 7 on the measurement substrate 3 and the wiring on the tester side.
And a capacitor 33 attached to the comparator where the relay 35 is turned on. Therefore, the relay 37 is turned on, the potential on the wiring is raised to V1, and the load capacitance is charged up. Next, when the relay 37 is turned off and the relay 36 is turned on, the value of the correction capacitor 38 set to an arbitrary capacitance value in advance and discharged to the GND potential and the original parasitic capacitance 7, 33 And the potential of the capacitor 33 in the comparator 5 changes to V2. By measuring the level of V2 by the comparator, the following relational expression is established. If the total parasitic capacitance is CX, CX · V1 =
(CX + C38) · V2.

CX is obtained from this relational expression, and it becomes possible to correct and set the load capacity to be guaranteed as the original specification for each terminal.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit test apparatus according to a second embodiment of the present invention. In the second embodiment of the present invention, as shown in FIG. 3, a signal is taken out from a terminal 29 of a device 30 by a contact 26 on a measuring socket 3, and a signal of a tester 2 is taken out from a terminal 31 on a measuring board 1. It is connected to a measurement pin 27 and is connected to a resistor 9, a driver 4, a comparator 5, and a variable additional capacitor 6 via relays 10 to 13, respectively. A driver 41 is connected to the opposite side of the resistor 9.

Next, the setting of the correction capacitor 6 according to this embodiment will be described with reference to the timing chart of FIG. FIG.
First, the relays 10 and 12 are turned on, and the resistor 9 and the comparator 5 are connected. At this time, the load capacitance on the measurement line is the parasitic capacitance 7 on the measurement substrate 3 and the wiring on the tester side, and the capacitance 33 on the comparator 5 where the relay 12 is turned on. Therefore, when the potential 40 of the driver 41 rises from the 0 level to the V3 level, the level on the measurement line changes transiently by charging up the capacitance via the resistor 9. The change in the potential of this measurement line is determined by the comparator 5
And a time t1 until a certain level V4 is obtained.

Next, the relay 13 is turned on, the correction capacitance 6 set to a certain value is added to the measurement line, and the potential 40 of the driver 41 is changed from the 0 level to V3 as described above.
When the level rises to the level, the level on the measurement line changes transiently by charging up the capacitance via the resistor 9. The potential change of this measurement line is observed by the comparator 5, and a time t2 until a certain level V4 is obtained.

Here, if the value of the resistor 9 is set relatively large, the following relationship is established.

[0015]

From this relational expression, the total parasitic capacitance CX =
C6 · t2 / (t1−t2) is obtained, and it is possible to correct and set the load capacity to be guaranteed as the original specification for each terminal.

[0017]

As described above, according to the present invention, it is possible to add an accurate capacitance to each terminal of a semiconductor integrated circuit, and to realize a highly accurate and accurate measurement.
In addition, since there is no need to attach a capacitive component to each product and each terminal on the measurement substrate, there is an effect that the cost of manufacturing the substrate can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit test apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of FIG.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit test device according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of the second embodiment of FIG. 3;

FIG. 5 is a circuit diagram of a conventional semiconductor integrated circuit test device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 measurement board 2 semiconductor integrated circuit test apparatus main body 3 measurement socket 4, 41 driver 5 comparator 6, 38 variable capacitance 7 parasitic capacitance 8 external correction capacitance 9 resistance 10 to 13, 24, 25, 34, to 37 relay 26 contact Terminal 27 Semiconductor integrated circuit measurement pin 29 Semiconductor integrated circuit terminal 30 Semiconductor integrated circuit 31 Measurement board terminal 32 Driver parasitic capacitance 33 Comparator parasitic capacitance 39 DC power supply 40 Contact V1 to V4 Potential t1, t2 Time

Claims (3)

(57) [Claims] An external connection terminal of a measurement substrate on which a semiconductor integrated circuit is set is connected to a measurement pin of a semiconductor integrated circuit test device main body, and the semiconductor integrated circuit is tested on the main body side. Variable capacity,
Means for charging the load capacity associated with the measurement system, and
Charge distributed to the load capacitance and the variable capacitance.
Means and the load capacity
Means for obtaining a semiconductor integrated circuit.
Road test equipment . 2. A potential on a wiring of the measurement system is raised to a first potential using a parasitic capacitance added to the measurement system and a capacitance attached to a comparator belonging to the measurement system as a load capacitance. Charge, then set the capacitance value to an arbitrary value in advance, and connect the correction capacitance that has been discharged to the ground potential to the wiring, distribute the charge charged to the load capacitance, and distribute the charge to the comparator. The potential of the capacitance of the portion is changed to a second potential. The potential of the second potential is measured by the comparator, and the load capacitance is obtained from the amount of change from the first potential to the second potential. Test method. 3. A potential on a wiring of the measurement system is raised to a first potential by using a parasitic capacitance added to the measurement system and a capacitance attached to a comparator belonging to the measurement system as a load capacitance, and the load capacitance is reduced. Charge, the rate at this time is measured by the comparator, then this potential is discharged to a predetermined value, and then a predetermined capacitance value is set in advance, and the correction capacitance that has been discharged to the ground potential is connected to the wiring. And charging the battery again. The comparator measures the rate of potential rise at this time, and determines the load capacity from the difference between the rate and the rate.