JP2978680B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for planarizing an interlayer insulating film constituting a semiconductor device.

[0002]

2. Description of the Related Art As the degree of integration of a semiconductor integrated circuit increases, the three-dimensional structure of the circuit becomes more and more complicated. On the other hand, the need for lithography technology places higher demands on the high flatness of an interlayer insulating film. It has become. Conventionally, the most commonly used planarization method is to form an interlayer insulating film using a low-melting-point silicon oxide film to which impurities such as phosphorus and boron (hereinafter abbreviated as P and B) are added, (Hereinafter, referred to as reflow), and the flattening can be performed most easily.
Further, a method has been proposed in which a photoresist is applied to the film surface after reflow of PSG and BPSG, and thereafter, is etched back to planarize the film (see Japanese Patent Application Laid-Open No. 62-1232). Hereinafter, a conventional process for planarizing an interlayer insulating film will be described with reference to FIG.

First, as shown in FIG. 2A, a circuit pattern 2 is already formed using a chemical vapor deposition method (hereinafter, referred to as a CVD method).
2 is formed on the semiconductor substrate 21 with the P concentration of 3 to 6 mo.
The BPSG film 23 to which 1% and the B concentration of about 8 to 13 mol% are added is grown to a desired thickness. Next, as shown in FIG. 2 (b), after performing a heat treatment for about 5 to 30 minutes in a nitrogen atmosphere at about 900 ° C. to reflow the BPSG film, a photoresist 26 is spin-coated to a thickness of about 1 μm. 10 more
A heat treatment is performed for 10 to 30 minutes in a nitrogen atmosphere at about 0 to 150 ° C. to solidify the photoresist. Then, a BPS gas such as CF ₄ and a O ₂ gas are used as etchants.
Using an anisotropic etching method under the condition that the selectivity between the G film 23 and the photoresist is 1: 1, the photoresist and the B
The PSG film 23 is etched back, and the planarization is completed as shown in FIG.

[0004]

According to this conventional method for manufacturing a semiconductor device, first, when reflow is performed only by heat treatment in a nitrogen atmosphere, if a BPSG film or the like is used during the heat treatment.
The impurity added from the surface of the interlayer insulating film to be reflowed diffuses outward without maintaining its chemical composition, and the surface layer concentration is reduced, thereby deteriorating the reflow shape. For this reason, in film formation of BPSG or the like, an impurity with a margin is added, but on the other hand, the margin for precipitates due to heat treatment that becomes particles such as BPO ₄ becomes narrow.

The deposition limit concentration of the BPSG film in the heat treatment in a nitrogen atmosphere at 900 ° C. is 18 mol% in total of the P concentration and the B concentration in the silane-based BPSG, and 16% in the TEOS-based.
It is about mol%. At such a concentration, sufficient flatness cannot be obtained due to the phenomenon of heat history due to the lowering of the temperature, so that the reflow treatment at a lower temperature in the future cannot be dealt with by reflow using only heat treatment.

Secondly, when reflow and resist etch-back are used together, when this resist etch-back is performed by a parallel plate dry etching apparatus, a large amount of resist boil-off usually occurs in a chamber for etching an oxide film. In addition to adhering and contaminating the inside of the chamber, the semiconductor device itself causes serious resist contamination and causes a problem of deteriorating the characteristics of the device.

Further, if the resist etch-back is performed by an ashing apparatus, the chamber made of quartz is etched by the fluorinated gas such as CF ₄ , and the frequency of replacement of quartz parts increases, so that productivity is deteriorated. In addition, since the etchant is consumed by the quartz and the etching rate around the wafer is reduced, the in-plane uniformity is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and is intended to reduce the time required for flattening and improve the productivity and yield. An object of the present invention is to realize a device manufacturing method.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming an interlayer insulating film constituting a semiconductor device using a low-melting-point silicon oxide film containing impurities such as phosphorus and boron. Performing a heat treatment at a temperature equal to or higher than the melting point of the formed film, and performing a heat treatment step of planarizing the silicon oxide film by flowing the silicon oxide film. Performed in an atmosphere containing the same element as the impurity in the film at a saturation vapor pressure or higher to fluidize the silicon oxide film and to form a glass layer having a flatter surface than the surface of the silicon oxide film on the surface of the silicon oxide film. It is characterized in that it is grown. The method may further include a step of removing the glass layer by etch back by anisotropic etching after the heat treatment step.

[0010]

According to the present invention, since the heat treatment step is performed in an atmosphere at or above the saturated vapor pressure of the impurities in the silicon oxide film, outward diffusion is very small. In such a situation, a glass layer is formed on the film surface,
Outward diffusion is further prevented.

[0011]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor device shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a semiconductor substrate 11 having a circuit pattern 12 formed thereon is formed by a CVD method.
On top, P concentration 3-6 mol%, B concentration 8-13 mol%
The BPSG film 13 with a certain degree of addition is grown to a desired thickness. Next, in order to prevent the outward diffusion of P and B from the film surface during the heat treatment, a gas obtained by bubbling a liquid material such as TMP and TMB by bubbling in a thermostat is used for each of 20 to 20 gases.
When the heat treatment is performed for about 5 to 30 minutes while maintaining the temperature of 900 ° C. in an atmosphere diluted with flowing nitrogen of about 2 to 10 SLM with respect to 100 sccm, heat treatment in a normal nitrogen atmosphere is performed as shown in FIG. BPSG films 13 'and P which have better flatness than the reflow shape of similar BPSG films
A phosphorus glass and boron glass layer 14 grown on the BSG film 13 'is obtained. The BPSG film 13 ′ is completely flattened in appearance by the phosphorus glass and the boron glass layer 14 and suppresses outward diffusion.
The flatness of 3 ′ is also good.

Next, as shown in FIG. 1C, BPSG is used as an etchant with a fluorinated gas such as CF ₄ and an O ₂ gas.
The entire surface is etched back using an anisotropic etching method under the condition that the selectivity of the film 13 to the phosphorus glass and the boron glass layer 14 is 1: 1 to complete the planarization. Where BPSG
The reason why the film 13 'has better flatness than the film subjected to the heat treatment in the nitrogen atmosphere is that the outward diffusion of P and B from the film surface layer is hindered by the P and B in the atmosphere.

In the first embodiment, the reflow was performed using a heat treatment at 900 ° C., but in the second embodiment,
The case of performing low-temperature reflow of about ° C will be described. First, a BPSG film 3 is grown in the same manner as in FIG.
In the same manner as in the embodiment, TMP and TMB
When heat treatment is performed for 5 to 30 minutes while maintaining the temperature of 800 ° C. in an atmosphere diluted with flowing nitrogen gas at about 2 to 10 SLM with respect to sccm, P and B in the atmosphere are diffused into the film surface layer, and P and B of the film surface layer are diffused. The B concentration becomes higher than in the first embodiment, and a shape equivalent to that of FIG. 1B is obtained. Thereafter, the entire surface is etched back using anisotropic etching as in the first embodiment, and the planarization is completed. In this embodiment, etch back by anisotropic etching is used as a method for removing the glass layer, because safe flattening can be realized by the etch back.

[0016]

As described above, according to the present invention, a low-melting-point silicon oxide film such as BPSG is formed as an interlayer insulating film, and furthermore, a saturated vapor pressure of impurities added to the formed silicon oxide film is obtained. By combining the step of performing a heat treatment at a temperature equal to or higher than the melting point in the atmosphere with the step of removing the phosphorus glass and boron glass layers grown on the film surface by anisotropic etching, the conventional flattening method has no disadvantages. In addition, excellent flatness of the interlayer insulating film can be realized. By applying the present invention and flattening, the yield can be improved by 20% by reducing short-circuit failure due to residue at the step portion of the interlayer film of the metal wiring and reducing focus failure during lithography exposure. .
Further, in the present invention, by using the second embodiment, it is possible to cope with a lowering of the reflow temperature in the future, so that the thermal history is shortened and the effect of preventing the shallow diffusion layer from expanding is exhibited.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in a process order for describing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Circuit pattern 13 Interlayer insulating film (BPSG) 14 Phosphor glass, boron glass layer 15 Silicon oxide film 16 Photoresist

Claims (2)

(57) [Claims] An interlayer insulating film constituting a semiconductor device is made of phosphorus,
A step of forming using a low-melting-point silicon oxide film containing an impurity such as boron, and a heat-treating step of performing heat treatment at a temperature equal to or higher than the melting point of the formed film and flowing the silicon oxide film to perform planarization. In the method for manufacturing a semiconductor device, the heat treatment step is performed in an atmosphere containing the same element as the impurity in the silicon oxide film to be subjected to the heat treatment at a saturation vapor pressure or higher to fluidize the silicon oxide film and A method for manufacturing a semiconductor device, comprising: growing a glass layer having a flatter surface than the surface of a silicon film on the surface of the silicon oxide film. 2. The method according to claim 1, further comprising a step of removing the glass layer by etch-back by anisotropic etching after the heat treatment step.