JP2979095B2 - Thin film memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a non-volatile thin film memory.

[Conventional technology]

As a non-volatile memory, there is a thin film memory using a thin film element. As this thin film memory, a thin film transistor using a thin film transistor is conventionally known.

FIG. 9 shows a conventional thin-film memory. In FIG. 9, reference numeral 1 denotes an insulating substrate made of glass or the like, on which a gate electrode 2 is formed. Further, the substrate 1
A memory gate insulating film 3 covering the entire gate electrode 2 is formed thereon. This memory gate insulating film 3
Is made of silicon-rich silicon nitride having a charge trapping function by increasing the composition ratio of silicon.
A semiconductor layer 4 made of i-type amorphous silicon or poly silicon (i-Si) is formed on the memory gate insulating film 3 so as to face the gate electrode 2. On both sides of 4 is n-type amorphous silicon or polysilicon (n ⁺ -Si)
A source electrode 6 and a drain electrode 7 are formed via an ohmic contact layer 5 made of. The gate electrode 2 is connected to a gate line (address line) (not shown) wired on the substrate 1, and the source electrode 6 and the drain electrode 7 are respectively wired on the memory gate insulating film 3 (not shown). It is connected to a source line (data line) and a drain line (data line).

This thin-film memory performs writing and erasing by applying a high-voltage write / erase voltage between the gate electrode 2 and the source / drain electrodes 6 and 7. When a write voltage is applied,
Charges are trapped at the interface between the memory gate insulating film 3 and the i-type semiconductor layer 4 to enter a write state. When an erase voltage is applied, the charges in the memory gate insulating film 3 are released to enter an erase state. Reading is performed by applying a low read voltage to the gate electrode 2.

[Problems to be solved by the invention]

However, in the conventional thin film memory using the thin film transistor, the source electrode 6 and the drain electrode 7 must be formed on the same surface at an interval corresponding to the channel portion of the transistor because of the structure of the thin film transistor. Due to the large element area of the memory, the degree of integration could not be increased.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a thin film memory that can reduce the element area and increase the degree of integration.

[Means for solving the problem]

The thin-film memory of the present invention forms a rectifying thin-film diode in which a lower electrode, a semiconductor layer, and an upper electrode are laminated on an insulating substrate, and forms a side of the semiconductor layer of the thin-film diode with a memory having a charge trapping function. It is characterized by being surrounded by an insulating film.

[Action]

The thin-film memory of the present invention performs writing by injecting electrons into the memory insulating film around the semiconductor layer by applying a high reverse bias voltage to the rectifying thin film diode. The injected electrons are trapped in the memory insulating film. In addition, reading may be performed by applying a low forward bias voltage to the thin-film diode. In a writing state in which electrons are trapped in the memory insulating film, the electric field generated by the trapped electrons in the memory insulating film causes an effect. A depletion layer is formed in the semiconductor layer, making it difficult for the forward current flowing between the two electrodes of the thin-film diode to flow. In a non-writing state in which the memory insulating film does not trap electrons, the depletion layer is formed in the semiconductor layer. Since there is no current, a forward current easily flows, so that reading can be performed depending on the magnitude of the forward current value.

This thin-film memory has a small element area because the side surface of the semiconductor layer of the thin-film diode in which the lower electrode, the semiconductor layer, and the upper electrode are stacked is surrounded by a memory insulating film having a charge trapping function. Thus, the degree of integration can be increased.

[Embodiment] One embodiment of the present invention will be described below with reference to FIGS.

FIGS. 1 and 2 are cross-sectional views of the thin film memory of the present embodiment. FIG. 1 shows a non-writing state, and FIG. 2 shows a writing state.

1 and 2, reference numeral 11 denotes an insulating substrate made of glass or the like, on which a rectifying thin-film diode D is formed. This thin film diode D
Is a Schottky diode, a lower electrode 12 formed on a substrate 11, a semiconductor layer 14 laminated on the lower electrode 12 via an ohmic contact layer 13, and formed on the semiconductor layer 14. , And a Schottky diode portion is formed between the semiconductor layer 14 and the upper electrode 15. The semiconductor layer 14
Is made of n-type amorphous silicon or poly-silicon (n ⁻ −Si) with a small amount of impurity added, and the ohmic contact layer 13 is made of n-type amorphous silicon or poly-silicon ( n ⁺ −S
i). The forward direction F in which the current of the thin film diode D flows is a direction from the upper electrode 15 to the lower electrode 12. Reference numeral 16 denotes a memory insulating film formed on the substrate 11 so as to surround the semiconductor layer 14 of the thin-film diode D. The memory insulating film 16 is formed by increasing the composition ratio of silicon, for example. It is made of silicon-rich silicon nitride having a charge trapping function. The memory insulating film 16 is formed to be thicker than the semiconductor layer 14 of the thin-film diode D, and the side surface of the memory insulating film 16 is in close contact with the peripheral side surface of the semiconductor layer 14. The lower electrode 12 of the thin-film diode D is connected to a lead line 12a wired on the substrate 11, and the upper electrode 15 is connected to a lead line 15a wired on the memory insulating film 16 (see FIG. 3). linked.

FIG. 3 is an equivalent circuit diagram of the thin film memory. In the thin film diode D, the forward current is controlled by the presence or absence of trapped electrons in the memory insulating film 16 surrounding the semiconductor layer 14. I have.

 Next, the operation of the thin film memory will be described.

FIG. 4 shows the VI characteristics of the thin-film diode D. The thin-film diode D has a lower electrode 12 and an upper electrode.
When a forward bias voltage _Vf is applied between the lower electrode 12 and the upper electrode 15, the forward current _If flows at a lower applied voltage.
High when the voltage applied to reverse bias voltage V _r of, have V-I characteristic of a large reverse current I _r flowing by the avalanche breakdown effect between.

This thin-film memory performs writing using the VI characteristic of the thin-film diode D.
High reverse bias voltage at which avalanche breakdown occurs between the lower electrode 12 and the upper electrode 15 of FIG.
When a voltage at a point is applied, hot carriers due to a high electric field are applied to the memory insulating film around the semiconductor layer 14 as shown in FIG.
Injected into 16. The injected electrons e are trapped near the interface between the memory insulating film 16 and the semiconductor layer 14 by the charge trapping function of the memory insulating film 16. In this write state, electrons e trapped in the memory insulating film 17
The effect of the electric field created by the semiconductor layer 14 of the thin film diode D
A depletion layer 14a is formed at the beginning. The depletion layer 14a extends from the interface with the memory insulating film 17 toward the center of the semiconductor layer 14, as shown in FIG.

Reading is performed by applying a low forward bias voltage between the lower electrode 12 and the upper electrode 15 of the thin film diode D. In this case, if the thin-film memory is in a writing state in which electrons e are trapped in the memory insulating film 16, in this writing state, the depletion layer is formed in the semiconductor layer 14 of the thin-film diode D.
14a, both electrodes 12, 14 of the thin film diode D
It becomes difficult for the forward current flowing between them to flow,
In the non-writing state (the state of FIG. 1) in which the memory insulating film 16 does not trap electrons, the forward current easily flows because the semiconductor layer 14 has no depletion layer. Reading can be performed.

FIG. 5 shows an effective voltage Vg caused by trapped electrons e in the memory insulating film 16 and a flow between the electrodes 12 and 15 when the forward bias voltage _Vf applied between the electrodes 12 and 15 is constant. It shows the relationship between the forward current _If and the electron trap density in the memory insulating film 16 and the thin film diode D so that the thin film diode D is in a pinch-off state in a write state.
Hot carrier injection efficiency into the memory insulating film 16 from the
The impurity concentration of the semiconductor layer 14 related to the extension of the depletion layer 14a and the thin film diode D in the direction in which the depletion layer 14a extends
The relationship between the forward current value in the written state shown by the solid line in FIG. 5 and the forward current in the non-written state (Vg = 0 V) shown by the broken line in FIG. The ratio with the value can be made sufficiently large.

In addition, erasing can be performed by ultraviolet irradiation. When the memory insulating film 16 is irradiated with ultraviolet light, the trapped electrons e are emitted and the memory insulating film 16 enters a non-writing state.

That is, the thin-film memory performs writing by injecting electrons into the memory insulating film 16 surrounding the periphery of the semiconductor layer 14 of the thin-film diode D, and the semiconductor layer 14 is formed by the effect of an electric field generated by trapped electrons in the memory insulating film. In this thin film memory, a lower electrode 12, a semiconductor layer 14, an upper electrode 15, and a depletion layer 14a are generated in the thin film memory. Is surrounded by a memory insulating film 16 having a charge trapping function around the semiconductor layer 14 of the thin film diode D in which
The degree of integration can be increased by reducing the element area.

FIG. 6 and FIG. 7 show a method of writing and reading a memory matrix constituted by the thin-film memory, in which X ₁ , X ₂ , X ₃ ... Are address lines, and Y ₁ , Y ₂ , Y ₃ ... are the data lines, and the thin film memory
_{X 1, X 2, X 3} ... and the data lines _{Y 1, Y 2, Y 3} ... and in each cross section, (in the flow direction of the forward current downstream) lead lines 12a of the lower electrode 12 is connected to the data line Are connected to Y ₁ , Y ₂ , Y ₃ , and the lead line 15 a (upstream in the forward current flow direction) to which the upper electrode 15 is connected is connected to the address lines X ₁ , X ₂ , X ₃ , etc. I have. R is a current limiting resistor connected in series to each thin film memory.

Writing and reading of this memory matrix are performed as follows. Note that here, the address line
For writing and reading it will be described with respect to (thin film memory of the leftmost top row in FIG. 6 and FIG. 7) thin film memory the intersection of X ₁ and the data line Y _1.

Write operation, as shown in FIG. 6, the potential of the address lines X ₁ to select the 0V, unselected address lines X _2, X
₃ ... the potential with the same as the write voltage V _H of the H point shown in FIG. 4, applying the write voltage V _H to the data line Y ₁ of the thin-film memory writes, other data lines
The potentials of Y ₂ , Y ₃ … are 0V. In this way, reverse bias voltage of the high voltage (V _H) is applied to the thin film diode D of the thin film memory of intersection of the address lines X ₁ and the data line Y _1, the thin film memory thin film diode D, the memory It enters a writing state in which electrons are trapped in the conductive insulating film 16. In the drawing, the thin-film memory in the written state is shown with its thin-film diode D painted out. In this case, other thin film memory that has led to the data lines Y ₁ to apply a write voltage V _H, the address lines X _2, X ₃ ...
Potential of being maintained in a non-write state is the same as the write voltage V _H. The thin-film memory that has led to the other data lines Y _2, Y ₃ ..., the data lines Y _2, Y ₃ ... potential 0V of address lines X _2, X ₃ ... potential write voltage V _H of the
Therefore, the thin film diode D of this thin film memory
A forward bias voltage is applied to the thin film memory because the electrons are not injected into the memory insulating film 16 by the application of the forward bias voltage. Although a forward current flows through the thin film diode D of the thin film memory to which the forward bias voltage is applied, the forward current is limited by the current limiting resistor R, and the forward current is applied to the thin film diode D. The direction bias voltage is also divided by the current limiting resistor R and becomes a low voltage.

The read time, as shown in FIG. 7, a read voltage V _L of the low voltage is applied to the address lines X ₁ to select, and the unselected address lines X _2, X ₃ ... of potential, all data The potentials of the lines Y ₁ , Y ₂ , Y ₃ ... Are set to 0V. This way,
Among the thin film memory that is connected to the address lines X ₁ selected, thin film memory (thin film diode D in the written state
The forward current hardly flows in the semiconductor layer 14 of which the depletion layer 14a is formed), and in the non-written thin film memory (the memory in which the semiconductor layer 14 of the thin film diode D does not have the depletion layer 14a). Forward current flows. The forward current flowing through each thin-film memory is
It is output via Y ₁ , Y ₂ , Y ₃ ….

FIG. 8 shows another embodiment of the present invention. In the thin film memory of this embodiment, an erasing gate electrode 17 surrounding a semiconductor layer 14 of a thin film diode D is provided in a memory insulating film 16. The other configuration is the same as that of the thin film memory of the above embodiment.

The thin-film memory of this embodiment is designed to erase a written state by applying an erasing voltage to the erasing gate electrode 17 to emit trapped electrons in the memory insulating film 16. When the memory matrix is composed of the thin film memories described above, not only the entire batch erasing such as erasing by ultraviolet irradiation but also erasing in block units such as for one line can be performed.

In the above embodiment, the thin film diode D is a Schottky diode, but this thin film diode has a pn junction in which a p-type semiconductor layer and an n-type semiconductor layer are stacked between a lower electrode and an upper electrode. A diode may be used.

〔The invention's effect〕

The thin-film memory of the present invention forms a rectifying thin-film diode in which a lower electrode, a semiconductor layer, and an upper electrode are laminated on an insulating substrate, and forms a side of the semiconductor layer of the thin-film diode with a memory having a charge trapping function. Since the element is surrounded by the insulating film, the element area can be reduced and the degree of integration can be increased.

[Brief description of the drawings]

FIGS. 1 to 7 show an embodiment of the present invention. FIGS. 1 and 2 are sectional views of a non-writing state and a writing state of a thin film memory, and FIG. 3 is an equivalent circuit of the thin film memory. Figure,
FIG. 4 is a diagram showing the VI characteristic of the thin film diode, FIG. 5 is a diagram showing the relationship between the effective voltage due to trapped electrons in the memory insulating film and the forward current of the thin film diode, and FIGS. FIG. 3 is an equivalent circuit diagram showing a method of writing and reading a memory matrix constituted by a thin film memory. FIG. 8 is a sectional view of a thin film memory showing another embodiment of the present invention, and FIG.
FIG. 1 is a sectional view of a conventional thin film memory. 11 ... substrate, 12 ... lower electrode, 13 ... ohmic contact layer, 14 ... semiconductor layer, 14 a ... depletion layer, 15 ... upper electrode, 16 ... memory insulating film, e ... electrons, 17 ... Erase gate electrode.

Claims (1)

(57) [Claims] A rectifying thin-film diode comprising a lower electrode, a semiconductor layer, and an upper electrode laminated on an insulating substrate, and a side surface of the semiconductor layer of the thin-film diode is formed as a memory insulating film having a charge trapping function. A thin-film memory characterized by being surrounded by.