JP2979778B2 - Signal line sharing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of sharing a signal line such as an interrupt signal line, for example, to an interrupt process relating to a bus architecture of a microcomputer system.

[0002]

2. Description of the Related Art FIG. 9 is a functional division drawing showing, for example, a conventional microcomputer system.
Is a system bus for performing data communication between the divided functional modules, 2 is provided in a required number, and a bus slave module (or simply referred to as a bus slave) in charge of each function, and 3 is each bus slave module. 2 is a bus master that provides a service to the server 2.

Next, the operation will be described. When the two bus slave modules (1) on the system bus 1 need to receive the service of the bus master 3 for some reason, the bus slave module (2) drives the interrupt signal line 1c assigned to itself. Bus master 3
Detects that there is an interrupt service request from the bus slave module (1) because the interrupt signal line 1c is driven, and provides services such as data transfer to the bus slave module (1). The process starts using another signal line group 1d. FIG. 10 shows bus slave 2,
FIG. 4 is an internal block diagram of the bus master 3. When the bus slave 2 needs to receive the service of the bus master 3, the signal line 5 of the interrupt factor (1) is made significant, and the bus driver 6 transmits the interrupt signal on the system bus 1. Drive line 1c. In the bus master, all the interrupt signal lines on the system bus are connected to the interrupt control circuit 8 via the bus receiver 7, and the interrupt control circuit 8 drives the interrupt line 1c. That the bus slave (1) has an interrupt service request.
The bus master 3 can start an interrupt service to the bus slave 2 by translating and transmitting the interpreted data so that the CPU can interpret it.

[0004]

In the conventional interrupt system, the above configuration is adopted, so that the number of interrupt signal lines is required as many as the number of bus slave modules requesting an interrupt service, and compatibility is taken into consideration. When the physical specifications of the system bus are not changed, the number of interrupt signal lines required for the system function cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a signal line connected to a plurality of bus slave modules can be shared and connected to the shared signal line. The purpose of the present invention is to obtain a signal line sharing system in which the number of bus slave modules is not limited.

[0006]

Means for Solving the Problems] signal lines sharing system according to the first invention, provided on the system bus an interrupt signal transmission timing signal line (an example of a timing signal line), Thailand
Timing signals with different periods by the
Interrupt signal by combining signal components
Signal line drive circuit (drive) that generates an interrupt signal (an example of a drive signal) synchronized with an interrupt signal transmission timing signal (an example of a timing signal) on a bus slave module (an example of a slave processing unit) In this case, an interrupt signal line (an example of a shared signal line) is time-division multiplexed, and an interrupt signal used by the bus master (an example of a master processing unit) is time-division multiplexed. By having a demodulation circuit (an example of a receiving means) for demodulating in (1), sharing of an interrupt signal line is achieved.

In the signal line sharing system according to the second invention, a bus clock line (an example of a clock signal line) is provided on a system bus, and the bus clock line is provided on a bus slave module (an example of a slave processing unit). An interrupt signal line driving circuit (an example of a driving unit) that generates an interrupt signal (an example of a driving signal) synchronized with a signal, and an interrupt mask register (an example of a prohibiting unit) that prohibits the operation of the interrupt signal line driving circuit. An interrupt signal line (an example of a shared signal line) is time-divisionally used, and an interrupt processing program (an example of a processing unit) activated by a time-divisionally used interrupt signal in a bus master (an example of a master processing unit) ) To query the bus slave module
Performed, by identifying the bus slave module that issued the interrupt signal is intended to reduce the share of the interrupt signal line.

[0008]

According to the first aspect, the interrupt signal line drive circuit (drive means) detects an asynchronous interrupt occurrence factor generated in the bus slave module by a timing signal having a different cycle.
Synchronization is performed in accordance with an interrupt signal transmission timing signal having a component, so that an interrupt signal line can be used in a time division manner. Further, the demodulation circuit (receiving means) on the bus master demodulates the shared interrupt signal in accordance with the interrupt signal transmission timing signal, and specifies the bus slave module which has requested the interrupt service.

In the second invention, the interrupt signal line drive circuit ( signal drive means) outputs an asynchronous interrupt generation factor generated in the bus slave module in synchronization with the bus clock signal line and outputs the interrupt mask register. The (prohibiting means) detects that another bus slave module uses the shared interrupt signal line, and detects its own interrupt signal line driving circuit ( signal driving means).
, The double driving of one interrupt signal line from a plurality of bus slave modules can be prevented. The interrupt processing program (processing means) on the bus master sends an inquiry to the bus slave module.
Then, the bus slave module that has requested the interrupt service is specified.

[0010]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, steps 1 to 3 have been described above, and will not be described. 1f is an interrupt transmission timing signal line, and 1e
Is a shared interrupt signal line. Each of 1e and 1f is a signal line on the system bus 1, and is connected to all the bus slave modules 2 requiring an interrupt service and the bus master 3.

FIG. 2 is an internal block diagram of the bus slave 2 and the bus master 3. The interrupt service request generated in the bus slave (1) is generated by the interrupt source (1).
By making the signal line 5 significant, the interrupt signal line drive circuit 9 sends, via the line driver 11, an interrupt signal synchronized with a predetermined timing to the interrupt sending timing signal 1f connected via the line receiver 10. Output to the shared interrupt signal line 1e.

Since a plurality of drivers drive one interrupt signal line, the line driver 11 uses an open collector or a line driver having a function equivalent thereto.

In the bus master 3, the shared interrupt signal line 1e is connected to the demodulation circuit 14 via the line receiver 12.
Is input to The pull-up resistor 13 stabilizes the potential of the signal line when no bus slave drives the interrupt signal line. The interrupt transmission timing generation circuit 15 has a specific signal pattern that enables the demodulation circuit 14 to identify the interrupt service request source of the interrupt signal used in time division multiplexing. The drive circuit 9 itself generates a specific signal pattern that can determine the usable time of the shared interrupt signal line.

FIG. 3 shows an example of an interrupt signal line drive circuit. The interrupt transmission timing signal 16 via the line receiver 10 is input to a one-shot multivibrator 17 and a counter 18. The counter 18 has its CLK
At the rising edge of the input, its outputs 0, 1, 2, 3,
, N operate in order to become significant, and the RST
The input is significant and at the rising edge of its CLK input, the output 0 is reset to be significant. The one-shot multivibrator 17 operates so that its output 19 becomes significant for a certain period from the rising edge of its input signal. Counter 18
FIG. 5 shows the operation timing of the one-shot multivibrator 17. As shown in FIG. 5, the interrupt transmission timing signal 16 via the line receiver 10 is a signal having a short period 20 from the rising edge to the next rising edge and a long period 21 (the same applies to the rising edge). The counter 18 is reset in the period 20 by using and setting the period in which the output 19 of the one-shot multivibrator 17 is significantly connected to between the periods 20 and 21, and the counter 18 is reset in the period 21. It can be counted in synchronization with the interrupt transmission timing signal. That is, all the counters 18 in all the bus slave modules 2 on the system bus can indicate the same count value. Therefore, an independent number is assigned to each bus slave module 2, and the number and the counter 1 are assigned.
If the interrupt signal lines can be driven when the count values of 8 match, one interrupt signal line can be shared and used by all bus slave modules. In FIG. 3, when the count value of the counter 18 is “1”, the signal line 22 becomes significant, and when the interrupt factor (1) of 5 is significant, 2
3, the output 24 of the AND gate becomes significant, and the shared interrupt signal line 1e is driven via the line driver 11.

FIG. 4 shows an example of the demodulation circuit 14 of the bus master 3. How interrupts transmission timing signal 1f from which bus slave module now determines whether the use the shared by interrupt signal line 1e are similar to the interrupt signal line driver circuit. There are two different points from the interrupt signal line drive circuit. One is that the interrupt signal is output from the inverter 25 so that it is sampled by the demodulation circuit 14 after the interrupt signal transmitted at the rising edge of the interrupt transmission timing signal is stabilized. 5, the interrupt signal drive timing and the sampling timing are shifted as shown in FIG. Second, since the shared interrupt signal line 1e indicates the interrupt request state of one bus slave module only for a certain period, the D flip-flop 27 is used to store the state. FIG.
During the period 28, the bus slave module (1) outputs an interrupt request to the shared interrupt signal line 1e, and the request output is output as a signal 21 via the line receiver 12 as a D flip-flop. Is input to step 27. The interrupt transmission timing signal 1f is sent to the inverter 25 via the signal line 20 in the bus master 3.
At the falling edge, the state of the interrupt signal line during the period 28 is stored in the D-flip-flop 27 as shown at 26. In the case of FIG. 4, the signal line 29 corresponds to the bus slave module (1).

The signal line group 30 including the signal lines 29 is output to the interrupt control circuit 8. This signal line group 30
Has the same effect as the signal group 31 in FIG.

Embodiment 2 FIG. Next, an interrupt signal line driving circuit in which a fixed cycle signal is used as an interrupt transmission timing signal and an interrupt processing program on the bus master side and an interrupt mask register on the bus slave side are added instead of the demodulation circuit is used. A description will be given of an embodiment for obtaining the effect described above.

FIG. 6 is a block diagram of this embodiment. Instead of the interrupt transmission timing signal generation circuit, the bus clock generation circuit 32 outputs a clock signal 33 having a fixed period, and the line clock 34 drives the bus clock signal line 1g. The rest is the same as the configuration of the bus master in FIG. The shared interrupt signal line 1e is input to the interrupt control circuit 8 via the line receiver 12, and an interrupt is generated at the rising edge of the signal.

The interrupt signal line drive circuit 35 of the bus slave module 2 outputs the bus clock signal 1g only when the interrupt disable output 37 of the interrupt mask register 36 is not significant and the interrupt factor (1) of 5 is significant. At the rising edge, the output 24 becomes significant, and the interrupt signal line 1e shared via the line driver 11 is set to 1
It is driven to logic "0" during the bus clock period. The shared interrupt signal line 1e is input to a line receiver 38, and its output 39 is input to an interrupt mask register 36. If the shared interrupt signal line 1e is driven even once by another bus slave module, its output 37 becomes significant, and the interrupt mask register 36 sets the interrupt signal line 1e shared by its own bus slave module. This is to prevent driving at an improper timing and prevent a multiple interrupt state from occurring. The bus slave module 2 needs to be able to confirm the presence / absence of the five interrupt factors, the state of the interrupt mask register, and reset the interrupt mask register 36 by the bus master 3.

FIG. 7 shows an example of the interrupt signal line drive circuit 35 and the interrupt mask register 36. The D-flip-flops 40 and 41 can generate an interrupt signal for one cycle of the bus clock signal 16, and the generation condition is that five interrupt factors are significant and 3
When the interrupt mask signal of No. 7 is not significant, the reset signal 43 of the D-flip-flops 40 and 41 is released by the AND gate 42. The interrupt mask register 36 is also formed of a D-flip-flop, and the “H” → “L” of the shared interrupt signal line 1e is used.
At the falling edge of, the interrupt inhibition signal 37 becomes significant. The interrupt mask register 36 stores the bus master 3 decoded by the own bus slave module.
Can be reset by an interrupt mask register signal 44 from the CPU. The NOR gate 45 prevents the interrupt mask register from being set when the own bus slave module drives the shared interrupt signal line 1e.

FIG. 8 is a flowchart of the interrupt processing program 50 of the bus master 3. The interrupt processing program 50 is a program that is started when an interrupt service request is transmitted from the interrupt control circuit 8 to the CPU. Check the status of the interrupt mask register. Then, in S2, an interrupt service is performed to the bus slave module having the interrupt request. Further, at S3, the interrupt disable signal 3
The interrupt mask register reset signal 44 is made significant for the bus slave module in which 7 is significant,
The interrupt mask register 36 is reset.

Embodiment 3 FIG. In the above embodiment, the bus master 3
Although the bus slave module 2 and the bus slave module 2 are physically separated from each other via the system bus 1, they may be present on the same wiring board. Does not need to be particularly adhered to, and the same effects as in the above embodiment can be obtained.

Embodiment 4 FIG. In the above embodiment, the case where the interrupt signal line is shared is described. However, the case where another signal line is shared may be used.

[0024]

As described above, according to the first and second aspects of the present invention, a large number of necessary signal lines can be replaced by a single shared signal line. The number can be reduced, and in the future expansion of the function of the entire system, there is an effect that the expansion of the function caused by the number of usable interrupt signal lines can be avoided.

The present system is an extension of the conventional system and is a form in which functions are added.
The above-described effects can be obtained by slightly changing the signal specifications without changing the physical specifications of the existing system bus according to the application.

[Brief description of the drawings]

FIG. 1 is a system diagram using an interrupt signal line sharing method according to an embodiment of the present invention.

FIG. 2 is an internal block diagram of a bus master and a bus slave showing one embodiment of the present invention.

FIG. 3 is a diagram of an interrupt signal line driving circuit showing one embodiment of the present invention.

FIG. 4 is a diagram of a demodulation circuit showing one embodiment of the present invention.

FIG. 5 is an operation timing chart showing one embodiment of the present invention.

FIG. 6 is an internal block diagram of a bus master and a bus slave showing one embodiment of the present invention.

FIG. 7 is a diagram showing an interrupt signal line drive circuit and an interrupt mask register circuit showing one embodiment of the present invention.

FIG. 8 is a flowchart of an interrupt processing program according to an embodiment of the present invention.

FIG. 9 is a system diagram of a conventional microcomputer system.

FIG. 10 is an internal block diagram of a bus master and a bus slave of a conventional microcomputer system.

[Explanation of symbols]

 Reference Signs List 1 system bus 1e shared interrupt signal line 1f interrupt transmission timing signal line 2 bus master 3 bus slave

Claims (2)

(57) [Claims] 1. A master processing unit having the following elements :
Sharing signal lines between at least one slave processing unit
Timing for connecting the signal line sharing scheme (a) the master processor and the slave processor to
Ring signal line, sharing that connects the slave processing unit (b) master processing unit
Signal line, the master processor having the following elements (c), child synthesized (c1) different timing signals periodic components
With this, the slave processing unit drives the shared signal line.
To generate a timing signal
Timing signal generating means for outputting to the bridging signal line, sharing the signal lines driven by (c2) the slave processor
The drive signal is received based on the above timing signal.
Receiving to identify whether it is a drive signal from the slave processing unit of the deviation
Means, (d) a timing output by the timing signal generating means
Output a drive signal to the sharing signal line based on the switching signal
A slave processing unit having a driving unit. 2. A master processing unit comprising:
Line sharing to share signal lines between slave processing units
Method (a) The clock connecting the master processing unit and the slave processing unit
Click signal line, sharing that connects the slave processing unit (b) master processing unit
Signal lines, system for connecting the slave processing unit (c) master processing unit
Mubasu outputs a master unit having (d) is the following elements, the (d1) clock signal to the clock signal line Black
Click generating means, drive by either (d2) said plurality of slave processing unit
Activated by the driven drive signal of the shared signal line
Queries multiple slave processing units for interrupt requests.
By matching, the drive from any slave
Processing means for identifying whether dynamic signal, the slave processor having the following elements (e), based on the clock signal from the (e1) master processing unit,
Signal driving means for outputting a driving signal to the sharing signal line; (e2) presence or absence of output of a driving signal by the signal driving means
Output means for outputting to the system bus, shared by (e3) the other slave processing unit of the signal driving means
Of the drive signal line, and execute its own signal drive means.
Prohibition means to prohibit.