JP2980459B2 - Semiconductor device manufacturing method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a one-dimensional characteristic in a semiconductor element is accurately and efficiently extracted, and a semiconductor element is manufactured using semiconductor element manufacturing conditions determined by analyzing the one-dimensional characteristic. The present invention relates to a device manufacturing method and an apparatus therefor.

[0002]

2. Description of the Related Art As a multi-dimensional effect in a semiconductor device manufacturing process, for example, a region (source / drain region) where there is no (gate) polysilicon 11 when oxidizing a field effect transistor (MOSFET) as shown in FIG. Of silicon substrate 12 (channel region) covered with polysilicon 11 is affected by the effect of oxidation of silicon substrate 12 (eg, M. Orlowski, et. Al. 1987 IEDM).
Multidimensional (in this case, two-dimensional) effects are known, such as those shown in CONFERENCE, pp. 632-635.

In a conventional one-dimensional simulation method,
For example, in order to regard the simulation area on the one-dimensional line AA ′ in FIG. 3 as being equivalent to the two-dimensional plane shown in FIG. It was difficult to obtain good simulation results.

On the other hand, by performing a multidimensional simulation, a highly accurate result incorporating the multidimensional effect can be obtained, but the calculation time becomes enormous as compared with the one-dimensional calculation, and an effective simulation for designing a semiconductor element is performed. It was difficult.

In the simulation of a semiconductor device, there are a part where a multidimensional simulation is required and a part where a sufficiently high accuracy is obtained by a one-dimensional simulation.

Conventionally, when a continuous simulation is to be performed using data obtained by a multidimensional simulation, the simulation must be performed by the same multidimensional simulation.

For example, to calculate the threshold voltage of a MOSFET using the results of a two-dimensional process simulation, as shown in FIG. 20, a two-dimensional device simulator is used to calculate the threshold voltage of the two-dimensional device obtained by the two-dimensional process simulation. A two-dimensional device simulation has to be performed by inputting the impurity concentration distribution and the like.

[0008]

As described above, the conventional one-dimensional simulation method has a problem that it is not possible to calculate by taking in a multidimensional effect, and it is not possible to obtain an accurate simulation result. .

Conventionally, a one-dimensional simulation could not be performed using a multidimensional simulation result, so that performing the multidimensional simulation all had a drawback that the calculation time was enormous.

A first object of the present invention is to take into account a multidimensional effect appearing in an actual semiconductor device manufacturing process when performing a one-dimensional analysis, thereby enabling highly accurate one-dimensional characteristic extraction in a short analysis time. Further, the present invention provides a semiconductor device manufacturing method and apparatus for improving the efficiency of a semiconductor device manufacturing process by manufacturing a semiconductor device using semiconductor device manufacturing conditions determined by analyzing one-dimensional characteristics. is there.

A second object is to extract a one-dimensional characteristic using a multidimensional analysis result, thereby extracting a semiconductor element characteristic with high accuracy in a short evaluation time, and further determining the characteristic based on the semiconductor element characteristic. It is an object of the present invention to provide a semiconductor device manufacturing method and a device for manufacturing a semiconductor device with high efficiency by manufacturing a semiconductor device using the semiconductor device manufacturing conditions described above.

[0012]

In order to achieve the above-mentioned object, a first feature of the present invention is that a one-dimensional distribution state of an impurity in an arbitrary one-dimensional region in a semiconductor device to be manufactured is determined by an impurity diffusion equation. In the semiconductor device manufacturing apparatus for manufacturing semiconductor devices using the manufacturing conditions after determining the manufacturing conditions of the semiconductor device from the one-dimensional distribution state of the impurities by extracting the semiconductor device using the manufacturing conditions, the multidimensional effect from the multidimensional region is diffused. Based on the means for quantitatively estimating the effect on the physical quantities that make up the equation, and on the basis of the quantitatively estimated magnitude of the effect of the multidimensional effect, extract the amount of change in the physical quantity that makes up the diffusion equation due to the multidimensional effect Means for extracting a one-dimensional distribution of impurities in consideration of a multidimensional effect based on the amount of change, and determining a manufacturing condition of the semiconductor element from the one-dimensional distribution of impurities. Lies in a semiconductor device manufacturing method and apparatus and a stage.

A second feature of the present invention is that a one-dimensional analysis of device characteristics of a semiconductor device to be manufactured is performed, and a manufacturing condition of the semiconductor device is determined from the one-dimensional analysis. In a semiconductor device manufacturing apparatus for manufacturing a device, means for executing a multi-dimensional analysis on a semiconductor device to be manufactured and a one-dimensional analysis region for executing a one-dimensional analysis from a semiconductor device region on which a multi-dimensional analysis has been performed are designated. Means for extracting device characteristics in the one-dimensional analysis area from the multidimensional analysis result, means for performing one-dimensional analysis using the element characteristics in the one-dimensional analysis area, A method and apparatus for manufacturing a semiconductor device having means for determining manufacturing conditions.

[0014]

According to the first aspect of the present invention, when performing a one-dimensional simulation of a semiconductor device, first, an influence exerted on a one-dimensional simulation region by a multidimensional effect obtained from the multidimensional region is determined by using an initial physical quantity. Estimate. From the estimated influence and the physical relationship between the multi-dimensional region and the one-dimensional simulation region, the amount of change in the simulation parameter in the one-dimensional simulation region is determined.

Then, a one-dimensional simulation is executed based on the amount of change, and a physical quantity on the one-dimensional simulation area is determined.

According to the second invention, when performing a one-dimensional simulation of a semiconductor device, first, a multi-dimensional simulation is performed. Next, on the multidimensional area where the multidimensional simulation result was obtained, a one-dimensional area where one-dimensional simulation was desired to be executed was specified, and physical quantities on the specified one-dimensional area were obtained by the multidimensional simulation. Calculate from the result.

Then, a one-dimensional simulation is performed using the calculated physical quantities on the one-dimensional area.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a semiconductor device simulation method and apparatus according to the present invention.

First, first, as an example of the multidimensional effect, the source / drain regions are oxidized by impurities (boron) forming a channel diffusion layer during a post-oxidation step after a manufacturing step of an n-type MOSFET. The simulation method and the result will be described with reference to the drawings by taking as an example a two-dimensional effect that is affected by the oxidation-enhanced diffusion effect by the method.

In this embodiment, the above-described two-dimensional effect will be described as an example. For example, in the case of a narrow channel MOSFET in which the influence not only from the source / drain region but also from the element isolation region affects the diffusion of the channel region, etc. Handling three-dimensional effects is possible in a similar manner.

FIG. 1 is a block diagram showing the configuration of an embodiment of the simulation apparatus according to the first invention.

In FIG. 1, an initial value input unit 1 is used to input an initial physical quantity for estimating an influence exerted on a one-dimensional simulation area by a multidimensional effect obtained from a multidimensional area.

The two-dimensional effect estimating unit 2 includes an initial value input unit 1
Is used to estimate the influence exerted on the one-dimensional simulation area by using the initial physical quantities input from.

The one-dimensional simulation execution unit 3 changes simulation parameters in the one-dimensional simulation region based on the influence estimated by the two-dimensional effect estimation unit 2 and the physical relationship between the multidimensional region and the one-dimensional simulation region. The amount is determined and a one-dimensional simulation is performed.

The physical quantity determining section 4 has a function of determining a physical quantity in the one-dimensional simulation area from the one-dimensional simulation result obtained by the one-dimensional simulation executing section 3.

FIG. 3 is a schematic diagram showing a two-dimensional effect on the impurity diffusion phenomenon in the post-oxidation step. Point defects generated by oxidization of the source / drain regions flow into the channel region immediately below the gate polysilicon 11.
3. Impurity (boron) in the channel region due to this
Is increased by the oxidation enhanced diffusion effect (OED) 14.

In this example, the gate polysilicon 11
(Thousands of Å) is sufficiently thicker than the oxide film thickness (about 100）) generated in the post-oxidation step, and since the gate oxide film 15 exists between the polysilicon 11 and the silicon substrate 12, It is stated that the OED effect due to the oxidation of the gate polysilicon 11 does not reach the silicon substrate 12, but if the effect of oxidizing the polysilicon 11 extends to the silicon substrate 12, if the OED effect is treated independently of the above, good.

Now, consider a one-dimensional simulation of the above (post) oxidation step on the one-dimensional line AA 'of the channel region shown in FIG. In the one-dimensional simulation according to the conventional method, the simulation is performed on the assumption that the layer structure on the straight line AA ′ is equivalent to the structure shown in FIG. 4 in which the oxide film 15 and the polysilicon 11 are formed in a two-dimensional plane on the silicon substrate 12. Do. Therefore, in the one-dimensional simulation according to the conventional method, the above-described OED effect does not enter the impurity diffusion in the silicon substrate 12.

The one-dimensional simulation method according to the first invention will be described below. As described above, when the source / drain regions are oxidized, the one shown in FIG.
The diffusion coefficient of the impurity (boron) in the silicon substrate 12 on the dimensional line AA 'increases due to the OED effect.

As one model for handling the OED effect of boron, for example, a diffusion coefficient (intrinsic diffusion coefficient) (D ₀ ) in a non-oxidizing atmosphere and an increase in the diffusion coefficient (D _{OE D} ) due to the OED effect are used. There is a model that expresses the diffusion coefficient D as D = D ₀ + D _OED . Here, a specific expression of D _OED is described in, for example, literature (AMLin, DA Antoniadis, RWDutto).
n, J. Electrochem. Soc., 128, 1131 (1981)). In the present embodiment, the OED
Handle effects.

Incidentally, in addition to the OED effect model used in the present embodiment, for example, a document which explicitly incorporates a point defect distribution
(SMHu, J. Appl. Phys., 57, 1069 (1985)), etc., but these models may be used.

In this embodiment, it is assumed that the ion implantation of arsenic or the like for forming the n ⁺ diffusion layer in the source / drain region is not performed. In consideration of the above, the effect of changing the diffusion coefficient due to point defects generated in the source / drain region at the time of ion implantation, and the fact that the impurity concentration in the source / drain region becomes high, the oxidation rate changes and the OED
It is sufficient to individually consider the effect of changing the effect.

Considering the diffusion coefficient D of boron in the silicon substrate 12 on the one-dimensional straight line AA ', the main factor for determining the increase due to the OED effect (D _OED ^AA' ) is as follows. Oxide film thickness (t _ox ^SD ), straight line AA '
(D _{AA ′} ) from the end of the gate polysilicon 11.

Using the above-described model of the OED effect, it is possible to estimate the increase in the diffusion coefficient of boron due to the oxidation of the source / drain region due to the OED effect, that is, the influence (D _OED ^SD ) due to the two-dimensional effect. it can.

As a method of evaluating D _OED ^{AA '} , for example,
Known is a ^'use from OED lateral decay length of the effect ^{_{(L 1at), D OED AA}} D OED SD (C B AA)' (CB AA ') = D OED SD (C B AA') × exp (−d _{AA ′} / L _1at ) (1)

[0036] As the value of L _1at, for example, the literature (AMLin
and RWDutton, Appl.Phys., 35, 799 (1979))
and literature (M. Orlowski, C. Mazure and F. Lan, 1987 EDM)
CONFERENCE, P632-635) proposes a value such as 1.4 μm. In this embodiment, L _1at = 2 μm.

In particular, the channel length (L _chan ) is short (L _chan ).
And ≦ L _{1 at.)} If, _'as in such cases is small _{enough, exp (-d AA' d AA} / L 1at) approximately 1 and when regarded ^{_{in, D OED AA '= (C}} B AA') D ^{_{OED SD (C B AA ')}} ... may be used (2).

As will be described in a simulation example described later, it is understood that when L _chan is small, the one-dimensional simulation using the equation (2) accurately matches the result of the two-dimensional simulation. Furthermore, L _chan is 10μ
Even when the length is as long as m, when evaluating the electrical characteristics of the semiconductor element (the threshold voltage of the MOSFET in this embodiment), the expression
It is shown that the one-dimensional simulation using (2) is effective.

FIG. 2 is a flowchart of the embodiment shown above.
It was shown to.

First, in step S101, the initial impurity distribution (C _B ^{AA '} (t = 0)), the initial oxide film thickness (t _ox ^SD ) of the source / drain regions, and the one-dimensional straight line for performing the one-dimensional simulation shown in FIG. A distance ( _{dAA '} ) between AA' and the end of the polysilicon 11 is input.

At the time of this input, it is specified whether or not to perform a calculation incorporating a multidimensional effect, and the above equations (1) and (2)
It is also specified whether to adopt any of the methods of estimating the amount of change of the diffusion coefficient shown in (1).

In step S102, an initial time is set, and in step S103, the time is advanced by Δt. Next, in step S104, it is determined whether a multidimensional effect is to be incorporated. If you do not want to calculate with multi-dimensional effects,
Similarly to the calculation by the conventional method, the increase (D _OED ^{AA '} ) of the diffusion coefficient due to the OED effect in the cross section AA' becomes zero (step S110).

On the other hand, when incorporating the multidimensional effect,
First, as shown in step S105, D _OED from _tox ^SD etc.
A parameter (for example, an oxidation rate of the source / drain region) for determining the function type of the ^SD is obtained. Next, in step S106, t _ox ^SD with respect to time t + Δt is obtained from the oxidation rate.

[0044] Incidentally, ^'for model does reveal the depend on the t _ox ^SD (depending on the oxidation rate), D _OED ^AA' to D _OED ^AA used in this embodiment of t _ox ^SD before determining the You can update it. However, a case where D _OED ^{AA 'is} revealed in accordance with the t _ox ^SD is may be subjected to processes of steps S106 after step 108 or S109.

Next, it is determined whether D _OED ^{AA '} is to be used by the equation (1) including an attenuation term corresponding to d _AA' or by using the equation (2) not including an attenuation term. , Step S1
In 08 or S109, D _OED ^{AA '} is determined. afterwards,
From D _OED ^{AA ′} determined as described above, the diffusion coefficient (D
_B = D ₀ + D _OED ^{AA ′} ) is determined, and a diffusion equation describing the impurity diffusion is solved in step S111 to determine the impurity concentration (C _B ^{AA ′} (t)) at time t.

Next, in step S112, it is determined whether or not the time t has reached the oxidation time (t _end ). If not, the flow returns to step S103 to advance the time, repeat the above steps, and reach t _end. If so, appropriate output is performed and the processing is terminated.

Hereinafter, an embodiment of the simulation based on the above-described simulation method will be described with reference to the channel length (L
_chan ) The case of an n-type MOSFET of 10 μm is shown, and then the case of L _chan = 2 μm is shown.

FIG. 5 is a two-dimensional cross-sectional view in which an oxide film 15 having a thickness of 100 ° and a polysilicon 11 having a thickness of 2000 ° are formed on the silicon substrate 12 before the oxidation step. The silicon substrate 12 is ion-implanted with boron as an impurity for forming a channel. This silicon substrate 12
FIG. 6 shows the boron concentration distribution before the oxidation step in the depth direction inside.

Subsequently, under an oxygen atmosphere at 900.degree.
FIG. 7 shows a state after the two-dimensional simulation of oxidation for one minute is performed. Here, the curve in the silicon substrate 12 is
It is a boron concentration line. In this embodiment, the oxidation of the polysilicon 11 was ignored.

The one-dimensional boron concentration distribution in the silicon substrate 12 in the depth direction at x = 2, 4, 6 μm on the x-coordinate in FIG. 7 is indicated by black triangles in FIGS.
Here, x = 2, 4, 6 μm in FIG.
_{AA '} = 1, 3, 5 μm. In particular, x =
In the case of 6 μm (d _{AA ′} = 5 μm), it represents one dimension in the central portion of the polysilicon 11 in FIG.

FIGS. 8 to 10 show the results of the two-dimensional simulation (black triangles) shown in FIG. 7 and the results of the one-dimensional simulation (solid line) according to the first invention. The result of the dimensional simulation (dotted line) is shown. In this embodiment, the effect of the oxidation-enhanced diffusion represented by the formula (1) is adopted.

8 to 10, it can be seen that the results obtained by the one-dimensional simulation method according to the first invention can reproduce the results of the two-dimensional simulation more accurately in all the sections than the results obtained by the conventional method. In particular, in the calculation according to the conventional method, the difference between the result in the central portion of the polysilicon 11 (when x = 6 μm) and the two-dimensional simulation is relatively small, but the difference increases as approaching the end of the polysilicon 11.

The calculation time of the two-dimensional simulation shown in FIG. 7 is about 15 minutes using a large computer, whereas the calculation time of the one-dimensional simulation according to the first invention shown in FIGS. One second.

In this embodiment, only one oxidation step is considered. However, in the step of fabricating an actual semiconductor device, only a heating step is performed several tens of times, which is required for a two-dimensional simulation in which a simulation of all steps is performed. Obviously, the computation time is enormous. From this point, the one-dimensional simulation for accurately reproducing the two-dimensional simulation has a great significance in terms of element design efficiency in terms of calculation time.

In the above embodiment, D _OED ^{AA ′} in each section was estimated and calculated based on equation (1).
By using D _OED ^{AA '} which does not include the attenuation term shown in (2), the maximum value of the effect of the two-dimensional effect of oxidation-enhanced diffusion on the boron concentration distribution in the channel region can be estimated. Also, a normal one-dimensional simulation (this is D _OE
D ^{AA ′} = 0), it is possible to estimate the minimum value of the effect of the two-dimensional effect.

[0056] As an example of the evaluation of the electric characteristics of these by, for example element, when the evaluation of the MOSFET threshold voltage (V _TH), the maximum value of V _TH only 1-dimensional calculation (V _TH
^MAX) and minimum value (V _TH ^MIN) can estimate, without actually seeking V _TH obtained by using a two-dimensional profile, practical example integrated by using the V _TH ^MAX and V _TH ^MIN The circuit and the like can be designed effectively.

Next, an embodiment in the case of L _chan = 2 μm (= L _1at ) will be described. The cross-sectional view of FIG.
_This corresponds to a sectional view of _chan = 10 μm. The thickness of the oxide film 15 and the thickness of the polysilicon 11 are the same as in the previous embodiment. The boron concentration distribution in the silicon substrate capacitor 12 before oxidation is the same as that of the previous example, and is shown in FIG. FIG. 12 shows the results of a two-dimensional simulation of the same oxidation step (oxidation under an oxygen atmosphere at 900 ° C. for 40 minutes) in the state shown in FIG. 11. The calculation time required for the two-dimensional simulation is about 15 minutes for a large-scale computer, as in the case of the previous embodiment.

The channel region shown in FIG. 12 (1 μm ≦
In the boron distribution (x ≦ 3 μm), there is no unevenness in the concentration in the channel direction seen in the channel region (1 μm ≦ x ≦ 11 μm) in FIG. It can be seen that they are almost the same regardless of the position of the cross section.

It can be interpreted that this is because the influence of the OED effect appears almost uniformly over the entire channel region because L _1at = 2 μm. That is, in this case, D in equation (2)
By using _OED ^{AA '} , the boron concentration distribution in the channel region can be obtained with high accuracy even in a one-dimensional simulation.

FIG. 13 shows the results of the one-dimensional boron concentration distribution in the silicon substrate 12 at x = 2 μm (black triangles). FIG. 13 also shows the result of the one-dimensional simulation of the first invention based on the equation (2) (solid line) and the result of the one-dimensional simulation by the conventional method (dotted line) for comparison.

As can be seen from FIG. 13, the result of the conventional method is significantly different from the result of the two-dimensional simulation.
It can be seen that there is a problem in the accuracy of element evaluation in one-dimensional simulation based on the conventional method. On the other hand, it can be seen that the result of the calculation method of the first invention matches the result of the two-dimensional simulation with high accuracy. Therefore, according to the first invention, 1
The accuracy of the dimensional simulation is greatly improved.

Second Embodiment Next, the method and apparatus for simulating a semiconductor device according to the second invention will be described in detail with reference to the drawings, taking MOSFET simulation as an example. In the present embodiment, a two-dimensional simulation will be described. However, the present invention is not limited to this, and the second invention is applicable to a multidimensional simulation such as a three-dimensional simulation.

FIG. 14 is a block diagram showing the configuration of one embodiment of the simulation apparatus according to the second invention.

In the figure, a two-dimensional simulation execution unit 21 is to perform a two-dimensional simulation on a two-dimensional plane.

One-dimensional simulation position designation unit 22
Is a part for specifying a position on the two-dimensional plane where the two-dimensional simulation result is obtained by the two-dimensional simulation execution unit 21 at which the one-dimensional simulation is desired to be executed.

The physical quantity calculating section 23 has a function of calculating a physical quantity on the one-dimensional area specified by the one-dimensional simulation position specifying section 22 from the two-dimensional simulation result obtained by the two-dimensional simulation executing section 21. I have.

The one-dimensional simulation executing section 24 is about to perform a one-dimensional simulation using the physical quantities on the one-dimensional area calculated by the physical quantity calculating section 23.

The display unit 25 displays the two-dimensional simulation results obtained by the two-dimensional simulation execution unit 21, the physical quantities on the one-dimensional area calculated by the physical quantity calculation unit 23, or the ones obtained by the one-dimensional simulation execution unit 24. It displays a dimensional simulation result and the like.

This simulation apparatus performs a one-dimensional and two-dimensional simulation of a semiconductor device manufacturing process such as deposition, etching, ion implantation, oxidation, diffusion, and the like, and an electric characteristic such as a diffusion layer resistance and a MOSFET threshold voltage. It has a function of performing dimensional simulation (device simulation) and a function of displaying an element shape, impurity distribution, electrical characteristics, and the like on an output device.

As a specific device, a CPU, this CP
An ordinary computer equipped with an input device connected to the U, a storage device such as a ROM, a RAM, a magnetic disk and the like and an output device such as a CRT terminal is used, and arithmetic processing in each step of the simulation is performed by an arithmetic unit of the CPU. At the same time, data such as numerical information generated in each step is stored in a memory such as a RAM or a storage device such as a magnetic disk.

The simulation apparatus used in this embodiment has a program structure that shares part of a subroutine or function used for one-dimensional semiconductor device simulation and part of a subroutine or function used for two-dimensional semiconductor device simulation. Te

FIG. 15 is a flowchart of the simulation method according to the second invention. The second invention will be described below with reference to this flowchart.

First, in step S201, data for performing a two-dimensional simulation of the MOSFET manufacturing process is input to the simulator. Next, in step S202, a two-dimensional simulation of a MOSFET manufacturing process such as deposition, etching, ion implantation, oxidation, or diffusion is performed.

In step S203, as shown in FIG. 16, the two-dimensional element shape including the silicon substrate 31, the gate oxide film 32, the gate electrode 33, the channel region 34, and the source / drain region 35, and the impurity concentration distribution in the element (Not shown) is displayed on a CRT terminal, for example.

In step S204, while looking at the two-dimensional element shape displayed on the CRT terminal as shown in FIG. 16 and the pointer 36 for designating the position at which the one-dimensional simulation is desired to be executed, the user moves the mouse or keyboard. To interactively specify a one-dimensional simulation position.

In step S205, for example, FIG.
A node for one-dimensional simulation is generated at the position of the pointer 36 passing through the center of the gate electrode 33, and a physical quantity such as an impurity concentration on each one-dimensional node is calculated from a two-dimensional simulation result using an interpolation method or the like. . FIG. 17 shows the calculated physical quantities on the pointer 36.

Here, in order to confirm the element structure, the obtained physical quantity in the one-dimensional cross section may be displayed on a CRT terminal. The physical quantities in the one-dimensional cross section shown in FIG.
4 shows an impurity distribution in the gate electrode layer 33, the gate oxide film layer 32, and the silicon substrate 31.

Next, the physical quantities in the one-dimensional section obtained in step S205 are set as initial values,
In step 206, data for performing a one-dimensional simulation is input, and in step S207, a one-dimensional simulation for solving, for example, a one-dimensional Poisson equation is performed to calculate a threshold voltage. In step S208, the obtained threshold voltage is displayed on a part of the CRT terminal as shown in FIG.

In the case of a normal MOSFET having a short gate length, the threshold voltage obtained by this method matches the threshold voltage calculated by the two-dimensional device simulation with good accuracy. As described above, according to the second aspect, the threshold voltage can be calculated with high accuracy in a calculation time shorter than the ordinary two-dimensional simulation.

In the case of a MOSFET having a long gate length, the threshold voltage calculated from the one-dimensional physical quantity at the gate end may be different from the threshold voltage calculated from the physical quantity in the one-dimensional cross section at the center of the gate.

In this case, an instruction to continue the simulation is issued in step S209, and step S204 is performed.
Then, the position where execution of the one-dimensional simulation is desired is changed, and the one-dimensional simulation is performed again. At this time, as shown in FIG.
If both the threshold voltage and the threshold voltage are displayed, and the position of the pointer 36 is interactively designated using a mouse or the like, the simulation can be performed efficiently.

Thus, the MOSFE having a long gate length
In the case of T, the upper limit value of the threshold voltage according to the second invention,
You can know the lower limit. Further, a region that controls the threshold voltage of the MOSFET can be specified, and can be used as an important guideline in element design.

In the above embodiment, the physical quantity in the one-dimensional cross section of the channel region 34 was calculated in order to calculate the threshold voltage. However, if the diffusion layer resistance of the source / drain region 35 is required, the source / drain region 35 It is sufficient to calculate the physical quantity in the one-dimensional cross section, and solve the one-dimensional Poisson equation, for example, to calculate the diffusion layer resistance.

The necessary two-dimensional process simulation at this time is the same as the process simulation of the above embodiment. Therefore, it is not necessary to newly perform a process simulation, and merely by changing the position of the pointer 36 in the necessary one-dimensional section. Physical quantities can be obtained.

Alternatively, if the junction depth of the source / drain region 35 is simply required, a two-dimensional process simulation is performed until the gate electrode 33 is formed, and then the source / drain region 35 is formed.
If a physical quantity in a one-dimensional cross section of the drain region 35 is calculated, and a subsequent process simulation is performed in one dimension, a desired junction depth can be obtained in a short calculation time.
As described above, the simulation apparatus used in this embodiment has a program structure that shares part of the subroutine or function used for one-dimensional semiconductor device simulation and part of the subroutine or function used for two-dimensional semiconductor device simulation. Te

Therefore, a program can be efficiently developed in a shorter time than a case where the one-dimensional semiconductor element simulator and the two-dimensional semiconductor element simulator are individually developed, and the maintenance work of the program becomes easy. Further, if the models used for both the one-dimensional and two-dimensional simulations are improved, the accuracy of the one-dimensional and two-dimensional simulations is simultaneously improved, so that the improvement work can be performed efficiently.

[0087]

As described above, according to the first aspect,
Conventionally, two-dimensional effects that could only be taken in two-dimensional simulation can be effectively taken in one-dimensional simulation. As a result, the calculation time of the simulation can be greatly reduced, and as a result, the element development efficiency can be significantly improved.

According to the second aspect of the present invention, since the one-dimensional semiconductor device simulation is performed using the results of the multi-dimensional semiconductor device simulation, the calculation time can be greatly reduced as compared with the case where all the multi-dimensional simulations are performed. it can. As a result, semiconductor element design, analysis, and evaluation can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a simulation device according to the first invention.

FIG. 2 is an example of a flowchart of a simulation method according to the first invention.

FIG. 3 is a schematic diagram of a two-dimensional plane showing that a diffusion coefficient is two-dimensionally affected by an OED effect during an oxidation process.

FIG. 4 shows a two-dimensional structure equivalent to the one-dimensional simulation by the conventional method for the first invention.

FIG. 5: L _chan = 10 μ before oxidation process simulation
FIG. 4 is a two-dimensional cross-sectional view of a MOSFET in the case of m.

FIG. 6 shows a boron concentration distribution in a depth direction in a silicon substrate before oxidation.

FIG. 7 is a two-dimensional simulation result after the oxidation step.

FIG. 8 is a one-dimensional simulation result after the oxidation step according to the first invention.

FIG. 9 is a one-dimensional simulation result after an oxidation step at a position different from FIG. 8;

FIG. 10 is a one-dimensional simulation result after an oxidation step at a position different from FIGS. 8 and 9;

FIG. 11: L _chan = 2 before simulation of oxidation process
It is a two-dimensional sectional view in case of μm.

FIG. 12 shows a two-dimensional simulation result of the oxidation step.

FIG. 13 is a one-dimensional simulation result of the oxidation step according to the first invention.

FIG. 14 is a block diagram showing a configuration of one embodiment of a simulation device according to the second invention.

FIG. 15 is a flowchart of a simulation method according to the second invention.

FIG. 16 is a sectional view of a two-dimensional element shape obtained by a two-dimensional simulation in the second invention.

FIG. 17 shows one-dimensional physical quantities on the pointer shown in FIG.

FIG. 18 is a diagram showing a state where a one-dimensional simulation result in the second invention is displayed.

FIG. 19 is a diagram illustrating a cross-sectional view of a two-dimensional element shape and a state in which a one-dimensional simulation result is displayed when a gate length is long.

FIG. 20 is a flowchart of a conventional simulation method for the second invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Initial value input part 2 Two-dimensional effect estimation part 3 One-dimensional simulation execution part 4 Physical quantity determination part 11 Polysilicon 12 Semiconductor substrate 13 Point defect diffusion 14 Oxidation enhancement diffusion 15 Oxide film 21 Two-dimensional simulation execution part 22 One-dimensional simulation position Designation unit 23 Physical quantity calculation unit 24 One-dimensional simulation execution unit 25 Display unit 31 Silicon substrate 34 Channel region 35 Source / drain region 32 Gate oxide film 33 Gate electrode 36 Pointer

Continuation of the front page (56) References Ulrich Weinert et al. "A Simulation System for Difficultive Oxidation of Silicon: One-Dimensional Analysis" Zeits chrift ｕr Nature forschung A: Physicol. 11, pp. 955-966 (1991) Sheid et. al. "1D Simulaton of Oxidation-Enhanced and Oxidation Rotated Diffusion in Silicone and Validity of the Physical Model, (No. 1986, No. 533, Philips, Stat.

Claims (4)

(57) [Claims] 1. A one-dimensional distribution state of an impurity in an arbitrary one-dimensional region in a semiconductor element to be manufactured is extracted using an impurity diffusion equation, and a manufacturing condition of the semiconductor element is determined from the one-dimensional distribution state of the impurity. A method of manufacturing a semiconductor device using the manufacturing conditions, the method further comprising: quantitatively estimating an influence of a multidimensional effect from a multidimensional region on a physical quantity constituting the diffusion equation; and Extracting the amount of change in the physical quantity constituting the diffusion equation due to the multi-dimensional effect based on the magnitude of the effect of the multi-dimensional effect estimated in, and considering the multi-dimensional effect based on the change amount Extracting the one-dimensional distribution state of the impurity, and determining the manufacturing condition of the semiconductor element from the one-dimensional distribution state of the impurity. Semiconductor device manufacturing method comprising and. 2. A one-dimensional distribution state of an impurity in an arbitrary one-dimensional region in a semiconductor element to be manufactured is extracted using an impurity diffusion equation, and a manufacturing condition of the semiconductor element is determined from the one-dimensional distribution state of the impurity. After that, in a semiconductor device manufacturing apparatus that manufactures a semiconductor device using the manufacturing conditions, a means for quantitatively estimating the influence of a multidimensional effect from a multidimensional region on a physical quantity constituting the diffusion equation, Means for extracting the amount of change in the physical quantity constituting the diffusion equation due to the multidimensional effect based on the magnitude of the effect of the multidimensional effect estimated in, and considering the multidimensional effect based on the change amount A means for extracting a one-dimensional distribution state of the impurity, and a means for determining a manufacturing condition of the semiconductor element from the one-dimensional distribution state of the impurity. Body element manufacturing apparatus. 3. A semiconductor which performs one-dimensional analysis of device characteristics of a semiconductor device to be manufactured, determines manufacturing conditions of the semiconductor device from the one-dimensional analysis, and manufactures the semiconductor device using the manufacturing conditions. In the device manufacturing method, a step of performing a multidimensional analysis on a semiconductor device to be manufactured; a step of designating a one-dimensional analysis region for performing a one-dimensional analysis from the semiconductor device region having performed the multidimensional analysis; Extracting device characteristics in the one-dimensional analysis region from the multidimensional analysis result; performing one-dimensional analysis using the device characteristics in the one-dimensional analysis region; manufacturing the semiconductor device from the one-dimensional analysis Determining a condition. 4. A semiconductor that performs one-dimensional analysis of device characteristics of a semiconductor device to be manufactured, determines manufacturing conditions of the semiconductor device from the one-dimensional analysis, and manufactures the semiconductor device using the manufacturing conditions. A device for performing a multi-dimensional analysis on a semiconductor device to be manufactured; a device for specifying a one-dimensional analysis region for performing a one-dimensional analysis from a semiconductor device region on which the multi-dimensional analysis has been performed; Means for extracting element characteristics on the one-dimensional analysis area from the multidimensional analysis result; means for executing one-dimensional analysis using the element characteristics on the one-dimensional analysis area; and manufacture of the semiconductor element from the one-dimensional analysis. Means for determining conditions.