JP2985092B2 - Time-division multitasking controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time-resolved multitask processing device that performs a plurality of tasks in a time-sharing and parallel manner using one central processing unit (CPU).

(Prior Art) Conventionally, as described in Japanese Patent Application Laid-Open No. 1-169540, this kind of time-division multitasking control apparatus has a plurality of control registers under the control of a set of control registers and a queue switching control unit. One central processing unit is occupied by the task execution queue in a time-sharing manner, and a plurality of tasks are processed by the plurality of task execution queues in a time-division parallel manner. In addition,
Among the control registers, a queue switching mode register that sets the switching mode of multiple task execution queues, a queue switching scheduling register that specifies the task execution queue, and a queue execution schedule that sets the CPU occupation time of each task execution queue A time designation register and the like are provided so that multitasking can be performed in a time-division parallel manner.

(Problems to be Solved by the Invention) However, in the above-described conventional configuration, when a plurality of tasks are executed by one CPU, a program is created in order to perform task switching using task time management and interrupt processing. At times, a task control block (hereinafter referred to as TCB) table to which priorities are assigned in advance is created, and the contents of the memory of the TCB are rewritten to the start address of the task to be executed, thereby managing the task to be executed. However, as the number of tasks that need to be controlled increases, the number of tasks stored in this TCB increases. Further, in this method, since the task to be executed next is searched for from the task with the higher priority, the time for searching for the task with the lower priority becomes longer. In order to execute multiple tasks on a single CPU in this way, the switching settings of each task and the priority of the execution time of each task are set by the program, and the actual task execution time is shortened by searching. However, there is a problem that the time during which the control program is executed becomes long.

An object of the present invention is to provide a time-division multitask control device that solves such a conventional problem.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a time-division multitasking control device in which a single central processing unit executes a plurality of tasks. As the data to indicate, a task that stores the value of the address itself, or the value of the start address of the execution task in place of that value.
Comparing means for comparing a value indicating the address itself in the control block table with a value stored as data at the address; selecting means for selecting a flag register from the address; and comparing means based on the output of the selecting means When there are a plurality of flag registers holding the outputs of the priority encoder, the priority encoder that selects the highest priority and outputs one designated signal, and the designated signal of the priority encoder and the base address written by initialization are synthesized, A port for outputting the address of the task control block table, and the highest priority task is selected from a plurality of tasks.

(Operation) Therefore, according to the present invention, it is possible to easily search for tasks to be executed in the priority order and set the execution specifications of the tasks simply by setting the start address of the necessary task in the TCB.

(Embodiment) FIG. 1 shows a basic configuration of a highest priority task selection control circuit in one embodiment of the present invention. In FIG. 1, 1 is an address data comparison circuit, 2 is a decoder,
3 is a flag register, 4 is a priority encoder,
5 is a TCB base address and 6 is a port.

Conventionally, as shown in FIG. 2, when a task is not used, its own address (TCB address) is written in the TCB. When the task 1 is executed when the TCB address TCB2 corresponds to the task 1, the TCB2 address is rewritten to the head address of the task 1 to be executed. The software searches for a task registered in the TCB. If the first address of the task 1 has the highest priority, the task 1 written in that task is executed.
Rewrite address 2 from the start address of task 1 to TCB2 address. At this point, the TCB is searched for the next task to be executed, and the time division multitask is executed. In the embodiment of the present invention, the above search part is implemented by hardware,
TCB addresses can be read from dedicated ports in the order of tasks with higher priorities. FIG. 3 shows a TCB control flow in the embodiment of the present invention.

Next, the operation of the embodiment of FIG. 1 will be described with reference to FIG. Write TCB base address by initialization (S
_1), also in TCB writes TCB address initialization (S _2). At this time, since the TCB address and the address (data) to be written in the position corresponding to the TCB address match, the output of the address data comparison circuit 1 becomes 0. Further, the decoder 2 generates a latch pulse to the corresponding F / F of the flag register 3, and the output of the corresponding F / F of the flag register 3 becomes 0. Therefore, since none of the outputs of the priority encoder 4 are selected, the signal with the lowest priority is output (when none is selected, the priority encoder outputs the lowest priority). At this time, when the port 6 is read (S ₃ ), the priority encoder 4 and the TCB base address 5 are combined to form the TCB address TCB3
I can read 1.

When rewritten contents of the TCB for TCB2 address to perform a task 1 to the start address of the task 1 by an interrupt (S _7), after completion of the interrupt, the address data comparison circuit 1 of the task selection control circuit, the TCB table Since the TCB2 address and the rewritten task 1 start address (data) do not match in the address TCB2, the output of the address data comparison circuit 1 is 1. The decoder 2 generates a latch pulse for the corresponding F / F of the flag register 3, and the output of the corresponding F / F becomes 1. Therefore, the output of the priority encoder 4 is "00" to select TCB2.
02H "(not shown). At this point T
Reading the port 6 to the search for CB, TCB2 address is read address of the TCB base address 5 and a priority encoder 4 are combined (S _3). Here, when the data of TCB written in TCB2 is read (S ₄ ), since the start address of task 1 is written, task 1 is executed (S ₅ ). rewritten from the start address to TCB2 address (S _6). As a result, TC
Since the B address and the write address (data) match, the output of the address data comparison circuit 1 becomes 0.
The decoder 2 generates a latch pulse for the flag register 3, and the output of the corresponding F / F of the flag register 3 becomes 0. Therefore, since none of the outputs of the priority encoder 4 are selected, a signal having the lowest priority is output. At this point, when port 6 is read, the addresses of priority encoder 4 and TCB base address 5 are combined and T
CB31 address can be read. Is there another task to execute
At the next address in the TCB table, the above processing is performed to read the port 6, thereby executing the time-division multitasking.

(Effect of the Invention) As is clear from the above embodiment, the present invention easily and quickly searches for tasks to be executed in priority order only by setting the start address of a necessary task in the TCB table, and executes task execution specifications. Has the effect of being able to set

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a time-division multi-task control device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating task processing by a conventional TCB, and FIG. It is a TCB control flowchart. 1 ... address data comparison circuit, 2 ... decoder, 3 ...
... Flag register, 4 ... Priority encoder,
5: TCB base address, 6: Port.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9 / 46,15 / 00 G06F 15 / 16,1 / 00

Claims (1)

(57) [Claims] 1. A control device for executing a plurality of tasks by one central processing unit, wherein data indicated by each address is a value indicating an address itself, or a value of a head address of an execution task in place of the value. Comparing means for comparing a value indicating the address itself in the task control block table storing the value with a value stored as data at the address;
Selecting means for selecting a flag register from the address, and priority encoder for selecting the highest priority one and outputting one designation signal when there are a plurality of flag registers holding the output of the comparing means by the output of the selecting means And a designation signal of the priority encoder and a base address written by initialization,
A port for outputting an address of the task control block table, wherein a highest priority task is selected from a plurality of tasks.