Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP2985376B2 - Automatic frequency control circuit - Google Patents
[go: Go Back, main page]

JP2985376B2 - Automatic frequency control circuit - Google Patents

Automatic frequency control circuit

Info

Publication number
JP2985376B2
JP2985376B2 JP3155009A JP15500991A JP2985376B2 JP 2985376 B2 JP2985376 B2 JP 2985376B2 JP 3155009 A JP3155009 A JP 3155009A JP 15500991 A JP15500991 A JP 15500991A JP 2985376 B2 JP2985376 B2 JP 2985376B2
Authority
JP
Japan
Prior art keywords
frequency
signal
controlled oscillator
control circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3155009A
Other languages
Japanese (ja)
Other versions
JPH057132A (en
Inventor
伊作 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3155009A priority Critical patent/JP2985376B2/en
Publication of JPH057132A publication Critical patent/JPH057132A/en
Application granted granted Critical
Publication of JP2985376B2 publication Critical patent/JP2985376B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Radio Transmission System (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は受信機の局部発振器等に
使用される自動周波数制御回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit used for a local oscillator of a receiver.

【0002】[0002]

【従来の技術】一般に、SCPC等の所要帯域幅の狭い
信号を使用して通信を行う場合に、送信機及び中継機内
の局部発振器周波数の経年変化あるいは衛星通信におけ
るドップラー効果による周波数変動分を受信機において
吸収して、復調器に入力される信号の周波数を一定にし
ておく必要がある。衛星通信においては親局より通信信
号以外のパイロット信号を送出し、受信局はこのパイロ
ット信号の周波数変動分を検出し、その検出した信号に
対して受信機の局部発振器の出力周波数を変化させ、復
調器に入力される信号周波数が一定となるよう制御して
いるが、この方式はいわゆる自動周波数制御方式(AF
C)として知られている。
2. Description of the Related Art In general, when communication is performed using a signal having a small required bandwidth such as an SCPC, a secular change of a local oscillator frequency in a transmitter and a repeater or a frequency variation due to a Doppler effect in satellite communication is received. It is necessary that the frequency of the signal input to the demodulator be absorbed and absorbed by the demodulator. In satellite communication, a pilot signal other than the communication signal is transmitted from the master station, the receiving station detects the frequency variation of this pilot signal, and changes the output frequency of the local oscillator of the receiver with respect to the detected signal, Control is performed so that the signal frequency input to the demodulator is constant. This method is a so-called automatic frequency control method (AF).
Known as C).

【0003】従来、この種のAFC回路は図2に示すよ
うに、受信機に入力された信号は電圧制御発振器(以下
VCOとする)2よりの信号と周波数混合器1(以下M
IXとする)において周波数混合され、両信号の差周波
数が出力信号となる。この出力信号の一部は雑音成分を
帯域制限する帯域ろ波器3を通り、周波数位相比較器5
に供給される。一方、基準信号発生器4の出力信号も周
波数位相比較器5に供給され、両者の周波数及び位相が
比較される。比較された結果、生ずる誤差成分はVCO
2に負帰還されVCO2の周波数を変化させる。この一
連の動作は、周波数位相比較器5の誤差成分がゼロにな
るまで続き、AFC回路の出力周波数は、入力信号の周
波数変化を吸収して常に一定周波数となる。
Conventionally, in this type of AFC circuit, as shown in FIG. 2, a signal input to a receiver is composed of a signal from a voltage controlled oscillator (hereinafter referred to as VCO) 2 and a frequency mixer 1 (hereinafter referred to as MCO).
IX), and the difference frequency between the two signals becomes the output signal. A part of this output signal passes through the bandpass filter 3 for band-limiting the noise component, and passes through the frequency phase comparator 5
Supplied to On the other hand, the output signal of the reference signal generator 4 is also supplied to the frequency / phase comparator 5, where the frequency and the phase of the two are compared. The error component resulting from the comparison is VCO
2 to change the frequency of VCO2. This series of operations continues until the error component of the frequency phase comparator 5 becomes zero, and the output frequency of the AFC circuit always becomes a constant frequency by absorbing the change in the frequency of the input signal.

【0004】[0004]

【発明が解決しようとする課題】上述した従来の自動周
波数制御回路は、SCPC等の狭帯域幅の信号を受信し
ようとする場合に、その信号の周波数の近傍には別の信
号が存在するので、AFCのプルイン・レンジが大きく
とれない。従って、パイロット信号の周波数オフセット
がAFCのプルイン・レンジを超えた場合はAFCがか
けられないという欠点があった。
In the conventional automatic frequency control circuit described above, when a signal having a narrow bandwidth such as an SCPC is to be received, another signal exists near the frequency of the signal. The AFC pull-in range cannot be made large. Therefore, when the frequency offset of the pilot signal exceeds the pull-in range of AFC, there is a disadvantage that AFC cannot be performed.

【0005】[0005]

【課題を解決するための手段】本発明の自動周波数制御
回路は、電圧制御発振器と、この電圧制御発振器により
入力信号を中間周波数に変換する周波数混合器と、この
周波数混合器の出力信号の一部を分岐して帯域ろ波器を
通過させた帯域制限信号と基準信号発生器の出力信号と
を比較して誤差信号を出力する周波数位相比較器と、前
記誤差信号を前記電圧制御発振器に帰還するループを有
する自動周波数制御回路において、前記誤差信号をA/
D変換して論理処理する論理回路と、前記論理回路の制
御信号により前記入力信号の周波数をステップ状に周波
数変換して前記電圧制御発振器の自動周波数制御レンジ
内に近付くにしたがって前記電圧制御発振器の周波数変
動幅を小さくするように制御するシンセサイザを備えた
周波数変換器を前記周波数混合器の前段に備えている。
SUMMARY OF THE INVENTION An automatic frequency control circuit according to the present invention comprises a voltage controlled oscillator, a frequency mixer for converting an input signal to an intermediate frequency by the voltage controlled oscillator, and an output signal of the frequency mixer. A frequency-phase comparator that compares an output signal of a reference signal generator with a band-limited signal that has passed through a band-pass filter by branching a unit to output an error signal; and feeding back the error signal to the voltage-controlled oscillator. In an automatic frequency control circuit having a loop for
A logic circuit for performing D-conversion and performing logic processing, and a step-like frequency conversion of the frequency of the input signal according to a control signal of the logic circuit, and as the voltage-controlled oscillator approaches the automatic frequency control range, Frequency change
A frequency converter provided with a synthesizer for controlling the dynamic width to be small is provided in front of the frequency mixer.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例のブロック図、図3は本実
施例のAFCレンジの説明図である。図1において、図
2の従来例と同一の符号は同一の機能と構成を有する。
すなわち、MIX1により周波数変換された信号に帯域
ろ波器3により帯域制限を加えた信号と、基準信号発生
器4の出力信号との間で周波数位相比較器5で比較を行
い誤差信号を取り出すまでは従来と同じである。本発明
においては、取り出された誤差信号をまずA/D変換器
6によりディジタル変換を行う。変換されたディジタル
信号は論理回路7に供給される。論理回路7はディジタ
ル信号に応じてVCO2の制御信号を発生する。この信
号はD/A変換器8によりアナログ信号に変換されVC
O2に加えられる。また、論理回路7は、VCO2の周
波数変動幅が大きくなりAFCのプルイン・レンジ近く
になると、VCO2の周波数変動幅が小さくなるように
周波数変換器9に制御信号を送り、AFC回路の入力周
波数を変化させる。
Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 3 is an explanatory diagram of an AFC range of the present embodiment. 1, the same reference numerals as those in the conventional example of FIG. 2 have the same functions and configurations.
That is, a signal obtained by subjecting the signal subjected to frequency conversion by the MIX 1 to band limiting by the band pass filter 3 and an output signal of the reference signal generator 4 are compared by the frequency phase comparator 5 until an error signal is extracted. Is the same as before. In the present invention, the extracted error signal is first subjected to digital conversion by the A / D converter 6. The converted digital signal is supplied to the logic circuit 7. The logic circuit 7 generates a control signal for the VCO 2 according to the digital signal. This signal is converted to an analog signal by the D / A
Added to O2. The logic circuit 7 sends a control signal to the frequency converter 9 so as to reduce the frequency fluctuation range of the VCO 2 when the frequency fluctuation range of the VCO 2 becomes close to the pull-in range of the AFC and the input frequency of the AFC circuit is reduced. Change.

【0007】ここで、論理回路7の出力信号によって制
御される周波数変換器9内部の周波数シンセサイザの周
波数をfsとすれば、周波数変換器9の入力周波数fr
及び出力周波数fiは(1)式のように表される。
Here, assuming that the frequency of the frequency synthesizer inside the frequency converter 9 controlled by the output signal of the logic circuit 7 is fs, the input frequency fr of the frequency converter 9
And the output frequency fi are expressed as in equation (1).

【0008】 fi=fr−fs …(1) また、MIX1の出力周波数をfo、VCO2の出力周
波数をflとすれば、(2)式のように表される。
Fi = fr−fs (1) Further, if the output frequency of MIX1 is fo and the output frequency of VCO2 is fl, it is expressed by equation (2).

【0009】 fo=fi−fl …(2) (1)式と(2)式より(3)式が導かれる。Fo = fi−fl (2) Equation (3) is derived from equations (1) and (2).

【0010】 fr=fo+fs+fl …(3) ここで、VCO2の出力周波数flは、発振中心周波数
をflo、中心周波数からの変位量をΔflとおくと、 fl=flo+Δfl …(4) と表すことができる。図3に示すように、AFCレンジ
を±Δfとおくと(5)式の関係がある。
Fr = fo + fs + fl (3) Here, the output frequency fl of the VCO 2 can be expressed as: fl = flo + Δfl (4), where Flo is the oscillation center frequency and Δfl is the displacement from the center frequency. . As shown in FIG. 3, if the AFC range is set to ± Δf, there is a relationship represented by Expression (5).

【0011】 flo−Δf≦fl≦flo+Δf …(5) (4)式を(3)式に代入して、(6)式が導かれる。Flo−Δf ≦ fl ≦ Flo + Δf (5) By substituting equation (4) into equation (3), equation (6) is derived.

【0012】 fr=fo+fs+flo+Δfl …(6) 図3において、受信機のパイロット信号の周波数の設定
値をfci、周波数変換器9内の周波数シンセサイザの
周波数をfsiとおくと、fciは(6)式より(7)
式のように表される。
Fr = fo + fs + flo + Δfl (6) In FIG. 3, if the set value of the frequency of the pilot signal of the receiver is fci and the frequency of the frequency synthesizer in the frequency converter 9 is fsi, fci is given by equation (6). (7)
It is expressed like a formula.

【0013】 fci=fo+fsi+flo …(7) また、パイロット信号の実際の受信周波数をfrとおく
とfrは(8)式で表される。
Fci = fo + fsi + flo (7) Further, if the actual reception frequency of the pilot signal is defined as fr, fr is expressed by equation (8).

【0014】 fr=fo+fsi+fli =fo+fsi+flo+Δfli …(8) ただし、fli=flo+Δfliである。fliはV
CO2の出力周波数である。
Fr = fo + fsi + fli = fo + fsi + flo + Δfli (8) where fli = flo + Δfli. fli is V
This is the output frequency of CO2.

【0015】ここで、論理回路7からの制御信号により
周波数変換器9内の周波数シンセサイザの周波数ステッ
プをfsとして、その出力周波数をf(si+1)=f
si+Δfsに変更し、その時VCO2の出力周波数を
f(li+1)=flo−Δf(li+1)とおけば、
frは(3)式より次のように表さる。
Here, the frequency step of the frequency synthesizer in the frequency converter 9 is set to fs by the control signal from the logic circuit 7, and the output frequency is f (si + 1) = f
If the output frequency of the VCO 2 is f (li + 1) = flo-Δf (li + 1),
fr is expressed as follows from equation (3).

【0016】 fy=fo+f(si+1)+f(li+1) =fo+fsi+Δfs+flo−Δf(i+1) …(9) 本発明では、(8)式=(9)式となるから、 Δfs=Δfli+Δf(li+1) …(10) ここで、Δfli≦Δfであり、Δf(li+1)≦Δ
fの関係があるので、(10)式より(11)式のよう
な関係が導かれる。
Fy = fo + f (si + 1) + f (li + 1) = fo + fsi + Δfs + flo−Δf (i + 1) (9) In the present invention, since equation (8) = (9), Δfs = Δfli + Δf (li + 1) (10) Here, Δfli ≦ Δf, and Δf (li + 1) ≦ Δ
Since there is a relationship of f, a relationship such as Expression (11) is derived from Expression (10).

【0017】 Δfs≦2・Δf …(11) (11)式は、周波数変換器9内の周波数シンセサイザ
の周波数ステップが、AFCレンジ以下であれば本発明
が実現できることを示している。
Δfs ≦ 2 · Δf (11) Equation (11) indicates that the present invention can be realized if the frequency step of the frequency synthesizer in the frequency converter 9 is equal to or smaller than the AFC range.

【0018】また図3より、論理回路7からの周波数変
換器9内の周波数シンセサイザの周波数切り替えは、パ
イロット信号の周波数オフセットが前述のシンセサイザ
の周波数ステップの2分の1になったときに行えばよい
ことがわかる。
FIG. 3 shows that the switching of the frequency of the frequency synthesizer in the frequency converter 9 from the logic circuit 7 is performed when the frequency offset of the pilot signal becomes one half of the frequency step of the synthesizer. It turns out to be good.

【0019】[0019]

【発明の効果】以上説明したように本発明の自動周波数
制御回路では、パイロット信号の受信周波数オフセット
の増加を検出し、それに応じて受信機に設定したパイロ
ット信号の周波数を自動的に変更することにより、パイ
ロット信号の受信周波数オフセットがAFCのプルイン
・レンジを超えた場合でもAFCをかけることが可能と
なる効果がある。
As described above, the automatic frequency control circuit according to the present invention detects an increase in the reception frequency offset of the pilot signal and automatically changes the pilot signal frequency set in the receiver accordingly. Thus, there is an effect that AFC can be performed even when the reception frequency offset of the pilot signal exceeds the pull-in range of AFC.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

【図2】従来の自動周波数制御回路のブロック図であ
る。
FIG. 2 is a block diagram of a conventional automatic frequency control circuit.

【図3】本実施例のAFCレンジの説明図である。FIG. 3 is an explanatory diagram of an AFC range of the present embodiment.

【符号の説明】[Explanation of symbols]

1 周波数混合器(MIX) 2 電圧制御発振器(VCO) 3 帯域ろ波器 4 基準信号発生器 5 周波数位相比較器 6 A/D変換器 7 論理回路 8 D/A変換器 9 周波数変換器 REFERENCE SIGNS LIST 1 frequency mixer (MIX) 2 voltage controlled oscillator (VCO) 3 bandpass filter 4 reference signal generator 5 frequency phase comparator 6 A / D converter 7 logic circuit 8 D / A converter 9 frequency converter

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電圧制御発振器と、この電圧制御発振器
により入力信号を中間周波数に変換する周波数混合器
と、この周波数混合器の出力信号の一部を分岐して帯域
ろ波器を通過させた帯域制限信号と基準信号発生器の出
力信号とを比較して誤差信号を出力する周波数位相比較
器と、前記誤差信号を前記電圧制御発振器に帰還するル
ープを有する自動周波数制御回路において、前記誤差信
号をA/D変換して論理処理する論理回路と、前記論理
回路の制御信号により前記入力信号の周波数をステップ
状に周波数変換して前記電圧制御発振器の自動周波数制
御レンジ内に近付くにしたがって前記電圧制御発振器の
周波数変動幅を小さくするように制御するシンセサイザ
を備えた周波数変換器を前記周波数混合器の前段に備え
ていることを特徴とする自動周波数制御回路。
1. A voltage controlled oscillator, a frequency mixer for converting an input signal to an intermediate frequency by the voltage controlled oscillator, and a part of an output signal of the frequency mixer is branched and passed through a bandpass filter. A frequency-phase comparator for comparing the band-limited signal with an output signal of a reference signal generator to output an error signal, and an automatic frequency control circuit having a loop for feeding back the error signal to the voltage-controlled oscillator, a logic circuit for logic processing and a / D conversion, the logic circuit and the voltage according to the frequency of the input signal to frequency conversion in a stepwise manner by the control signal closer to an automatic frequency control range of the said voltage controlled oscillator Controlled oscillator
Synthesizer that controls to reduce the frequency fluctuation range
An automatic frequency control circuit, comprising a frequency converter provided with a frequency converter before the frequency mixer.
【請求項2】 前記周波数変換器が前記論理回路の制御
信号によりステップ状に周波数を変化するシンセサイザ
を有することを特徴とする請求項1記載の自動周波数制
御回路。
2. The automatic frequency control circuit according to claim 1, wherein said frequency converter has a synthesizer for changing a frequency stepwise according to a control signal of said logic circuit.
JP3155009A 1991-06-27 1991-06-27 Automatic frequency control circuit Expired - Fee Related JP2985376B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3155009A JP2985376B2 (en) 1991-06-27 1991-06-27 Automatic frequency control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3155009A JP2985376B2 (en) 1991-06-27 1991-06-27 Automatic frequency control circuit

Publications (2)

Publication Number Publication Date
JPH057132A JPH057132A (en) 1993-01-14
JP2985376B2 true JP2985376B2 (en) 1999-11-29

Family

ID=15596698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3155009A Expired - Fee Related JP2985376B2 (en) 1991-06-27 1991-06-27 Automatic frequency control circuit

Country Status (1)

Country Link
JP (1) JP2985376B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8138746B2 (en) 2007-03-20 2012-03-20 Pioneer Corporation Physical properties detection device and physical properties detection method
EP2302688A1 (en) 2009-09-23 2011-03-30 Robert Bosch GmbH Method for producing a substrate with a coloured interference filter coating, this substrate, interference filter coating, the use of this substrate as coloured solar cell or as coloured solar cell or as component of same and an array comprising at least two of thee substrates

Also Published As

Publication number Publication date
JPH057132A (en) 1993-01-14

Similar Documents

Publication Publication Date Title
JP2971033B2 (en) Apparatus and method for restoring digital carrier in television signal receiver
JPS623621B2 (en)
US3939425A (en) Noise-squelching circuit using a phase-locked loop
US4669094A (en) FSK data receiver
US6006078A (en) Receiver with improved lock-up time and high tuning stability
US5793819A (en) Radio communication terminal station
JP2985376B2 (en) Automatic frequency control circuit
US4885801A (en) Method and circuit for converting frequency-modulated signals through at least one intermediate frequency into low frequency signals
JPS588617B2 (en) Jiyushinki
EP0176703B1 (en) Intermediate frequency signal processing circuit
US6144844A (en) Method and system for controlling frequency
US4347483A (en) Frequency and phase lock loop with separated AFC and phase locking
JP2877177B2 (en) Receiver for frequency division multiple access communication system
JPH05300015A (en) Local oscillator for radar equipment
JPH10178599A (en) Digital satellite broadcast receiver
JPH0722846A (en) Frequency converter
JP3038877B2 (en) Automatic frequency control circuit
JPS6349962Y2 (en)
JP2998796B2 (en) AFC device for orbiting satellite communication and frequency converter for orbiting satellite communication
JPS61131681A (en) Carrier wave recovery circuit
JPH06104788A (en) Superheterodyne receiver
JPH0250643B2 (en)
KR970013686A (en) Tuner device for satellite broadcasting
JPS63228818A (en) Automatic frequency control circuit
JPS6382084A (en) Oscillation system for highly stable reference frequency

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990831

LAPS Cancellation because of no payment of annual fees