JP2986172B2 - Screening test method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a screening test method for a semiconductor integrated circuit, and more particularly to a method for evaluating the reliability of an interface between an oxide film having a MOS structure and a Si substrate. is there.

(Prior Art) Generally, the failure rate of an electronic component shows a certain fixed tendency as shown by a curve a in FIG. This is divided into three periods, called an initial failure period, a random failure period (stationary period), and a wear failure period. In the range experienced so far, the failure rate gradually decreases during the accidental failure period as shown by the curve b in FIG. 4, and the time to the abrasion period is much longer than the normal use period. Since there is no problem except for use under severe conditions, the initial failure period and the random failure period are generally considered. The target of screening (excluding non-defective products) at the time of product shipment is the early failure period when the failure rate is high. Usually, a screening method called burn-in is widely used. Burn-in is a method of continuously performing an operation test in an atmosphere at a constant temperature of about 150 ° C. Specifically, a product body such as a MOS semiconductor device is operated at a temperature or voltage condition that accelerates a failure factor to forcibly generate an initial failure and perform screening.

(Problems to be solved by the invention) Items of initial failure include oxide film destruction of the MOS structure and characteristic fluctuations such as threshold voltage due to instability based on charges in the oxide film. In order to do so, a sufficient time for the temperature and voltage to exceed the initial failure period is required. However, if the screening test time is too long, it will be a kind of destructive test, and the random failure period with a low failure rate will be eaten by the test, and even for integrated circuits with relatively simple operation timing such as memory, setting appropriate time conditions is not possible. Difficult.

Also, in CPUs or random logic, the actual screening time required for each MOS structure in an integrated circuit during the operation of the integrated circuit differs depending on the case. It is difficult to set the same. If sufficient time is given to each MOS structure, the MOS structure of one specific circuit will undergo much longer stress time than the other MOS structure, and it is not a screening test, but rather a destructive test that enters the wear phase. . At present, a MOS structure having the longest stress time is assumed, and the screening operation time is set according to the MOS structure. Therefore, it cannot be said that screening for initial failure is performed for each MOS structure, and the time tends to be longer.

On the other hand, naturally, a screening test such as burn-in also requires facilities such as a furnace and an integrated circuit operating power supply.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a screening method for removing an initial defective product, which performs screening without giving a stress leading to deterioration of the main body integrated circuit.

[Structure of the Invention] (Means and Action for Solving the Problems) The present invention provides: (1) In order to test a semiconductor integrated circuit, at least a part thereof has a MOS structure on a semiconductor wafer together with the semiconductor integrated circuit. A radiation or ultraviolet ray is applied only to this evaluation area, and then an electric field of 1 MV / cm or more is applied for 1 second or more, and the leakage current of the gate oxide film included in the MOS structure of the evaluation area is two digits. A screening test method for a semiconductor integrated circuit characterized by predicting the reliability of the semiconductor integrated circuit by regarding the semiconductor integrated circuit adjacent to the changed evaluation area as defective.

Further, the present invention provides: (2) for testing a semiconductor integrated circuit, the semiconductor integrated circuit is provided adjacent to the semiconductor integrated circuit on a semiconductor wafer, and at least a part thereof is heated only to an evaluation region of a MOS structure to 50 ° C. or more; At the same time, an electric field of 1 MV / cm or more is applied for 1 second or more, and a semiconductor integrated circuit adjacent to the evaluation area where the leakage current of the gate oxide film included in the MOS structure of the evaluation area has changed by two digits or more is regarded as defective. A screening test method for a semiconductor integrated circuit, wherein reliability of the semiconductor integrated circuit is predicted.

Further, according to the present invention, (3) the evaluation region is partially formed to have the same structure as the semiconductor integrated circuit, and the evaluation region is continuously operated for 1 minute or more at a normal operating power supply voltage or higher of the semiconductor integrated circuit, resulting in a failure. 3. The screening test method for a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit close to the evaluation area is regarded as defective.

(4) The screening test method for a semiconductor integrated circuit according to (2), wherein: (4) a laser, a halogen lamp, or an infrared lamp is used for the heating.

That is, in the present invention, when performing a screening test on a semiconductor integrated circuit having a MOS structure or the like, a semiconductor integrated circuit is manufactured on a wafer at the same time as a main body integrated circuit, and a part of the evaluation region (Test Element) of the MOS structure is used.
Group is abbreviated as TEG), radiation or ultraviolet rays are applied only to this evaluation area to accelerate the deterioration of the evaluation section, and then an electric field of 1 MV / cm or more is applied for 1 second or more, and the MOS structure in the evaluation area is applied to the evaluation area. Leakage current of the included gate oxide film is 2
The reliability of the semiconductor integrated circuit due to the electric field stress is predicted by regarding the semiconductor integrated circuit adjacent to the evaluation area that has changed by an order of magnitude or more as defective. This makes it possible to predict the reliability with respect to electric field stress without applying electric stress to the semiconductor integrated circuit of the main body.
Also, the present invention provides a method for screening a semiconductor integrated circuit having a MOS structure or the like by performing a burn-in test by heating only an evaluation device formed in close proximity to the semiconductor integrated circuit to 50 ° C. or more, and simultaneously, applying an electric field of 1 MV / cm or more. And the leakage current of the gate oxide film included in the MOS structure of the evaluation area is considered as defective by giving it for 1 second or more. Good test results can be obtained without burden.

(Embodiment) A first embodiment of the present invention is to provide (a) an evaluation area (TEG) provided together with a main body integrated circuit on a semiconductor wafer, and irradiating only this evaluation area with radiation or ultraviolet rays and applying an electric field stress. Estimating the reliability of the integrated circuit by evaluating a change in the electrical characteristics of the evaluation area.

FIG. 1 shows one means of realizing the above item (a).
An (ultraviolet) lamp, 2 is a semiconductor wafer, 3 is a chip area where a main body IC (integrated circuit) is formed, and 4 is an evaluation area (TEG) formed together with the main body IC. Evaluation area here
Only... Are exposed, and others (such as the main body IC) are covered so as not to be irradiated with ultraviolet rays.

FIG. 2 shows an example of the structure of the evaluation region 4, and FIG. 3 shows an example of the manufacturing process. The region is the first gate, the region is the second gate, and the region is a portion for evaluating the reliability of the gate oxide film corresponding to the overlapping portion of the first gate and the second gate.

In the manufacturing process, a field oxide film 42 and a 200 ° first gate oxide film 43 are formed on a semiconductor substrate 41 as shown in FIG.
Was formed. Next, as shown in FIG. 3 (b), after depositing and forming a first polysilicon layer 44, a resist film 45 was formed thereon, and this was patterned by photolithography. Next, FIG. 3 (c)
As described above, the polysilicon layer 44 was removed by etching using the resist 45 as a mask. Next, after removing the resist as shown in FIG. 3 (d), a first gate oxide film 46 was formed as shown in FIG. 3 (e). Next, as shown in FIG. 3 (f), a second gate polysilicon layer 47 was formed by lamination and patterned. Then CVD layer 4
8 was deposited and Al wiring 49 was applied to form three types of MOS structures as shown in FIG.

As an embodiment of the present invention, a design rule (1.2 μm)
A MOS memory having almost the same total number of elements (250,000 devices / chip level) and having a two-layer polysilicon gate structure was manufactured. A chip having a part of the chip having the same evaluation area as that shown in FIG. 2 and a chip having the same structure as the main body and having an evaluation area of 10,000 elements were formed.
The effectiveness of the present invention was verified by applying various screening methods to these chips.

First, as a conventional method, a good product is assembled after die sorting, and 12
The device was operated for 128 hours at 5 ° C. and 6V power supply (normal operating condition: 5V), and a memory operation test was performed again to screen non-defective products.

Next, as an embodiment of the present invention (referred to as present invention 1), after die-sorting in a wafer state, the area other than the evaluation area 4 in FIG.
Cover with a μm resist and apply UV light to the exposed evaluation area
Irradiation was performed at 200 mw / cm ² for 10 seconds. After that, the resist is removed and a good die sort product is assembled. When a voltage of 6 V is applied to the capacitor structure in each evaluation area 4, a temperature of 125 ° C.
After leaving for a while, the element in which the leak current was increased was regarded as defective and screened.

As another method (referred to as Invention 2), a multipoint probe is opened and a capacitor (6th volt) is opened at a temperature of 50 ° C. with laser light only in the same evaluation region in a wafer state after the above-mentioned ultraviolet irradiation. (See the figure). Then, after a memory operation test of the main body was performed in a wafer state, a non-defective product having no change in the operation of the evaluation section was assembled. However, as a criterion for the operation of the evaluation section, an electric field of 1 MV / cm or more should be applied to the capacitor section for at least one.
It takes at least two seconds to determine whether the leakage current of the gate oxide film changes by two digits or more, or by operating the evaluation region continuously for at least two minutes or more at the normal operating voltage of the main integrated circuit (here, 6 V). No abnormality was used as a criterion.
After assembling the non-defective product, a memory operation test is performed again to perform screening.

The above conventional burn-in method, the present invention 1 method, the present invention 2
500 for each 10,000 good products screened by the method
When the failure rate after 0-hour operation was investigated, no more than one defect was found in any of the screening methods. On the other hand, if only the initial characteristics are checked and the above-mentioned burn-in or other screening is not performed, 20
More than one defect occurred.

According to the present invention, a screening method corresponding to the prior art and burn-in has been developed, and furthermore, an electric stress is applied only to the evaluation region only and no electric stress is applied to the main body. The point that "screening is a kind of destructive test" was avoided. Further, since the main body is not used, the same screening effect can be expected regardless of whether the main body is a memory or a random logic. Further, in the present invention 1,
It is sufficient to apply a simple DC stress, so that the cost of the apparatus can be reduced. According to the second aspect of the present invention, screening is performed in a wafer state, thereby reducing the cost when the assembly cost is high.

The present invention is not limited to the above embodiment, but can be applied to various applications. For example, in the example, stress acceleration was performed using ultraviolet rays, but similar results were obtained using high-energy radiation.

[Effects of the Invention] As described above, according to the present invention, stress for a short-time test is applied only to the evaluation area, so that it is possible to improve product reliability and reduce costs. .

[Brief description of the drawings]

FIG. 1 is an explanatory view of one embodiment of the present invention, FIG. 2 is a partial configuration diagram thereof, FIG. 3 is a manufacturing process diagram thereof, and FIG. 4 is a characteristic diagram showing a product failure rate-elapsed time. is there. DESCRIPTION OF SYMBOLS 1 ... UV lamp, 2 ... Wafer, 3 ... Chip area, 4 ... Evaluation area (TEG), 41 ... Semiconductor substrate, 42 ...
… Field oxide film, 43,46 …… Gate oxide film, 44 ……
First gate polysilicon layer, 47... Second gate polysilicon layer, 49... Al wiring.

Claims (4)

(57) [Claims] 1. A test area for testing a semiconductor integrated circuit, wherein at least a part of the evaluation area having a MOS structure is provided on a semiconductor wafer together with the semiconductor integrated circuit, and only this evaluation area is irradiated with radiation or ultraviolet light. And then 1MV /
by applying an electric field of at least 1 cm to the semiconductor integrated circuit adjacent to the evaluation area in which the leakage current of the gate oxide film included in the MOS structure of the evaluation area has changed by two digits or more, A screening test method for a semiconductor integrated circuit, which predicts reliability of a semiconductor integrated circuit. 2. A semiconductor integrated circuit for testing a semiconductor integrated circuit, the semiconductor integrated circuit being provided adjacent to the semiconductor integrated circuit on a semiconductor wafer, at least partially heating only an evaluation region of a MOS structure to 50 ° C. or higher, and at the same time, 1 MV. The semiconductor integrated circuit adjacent to the evaluation area where the leakage current of the gate oxide film included in the MOS structure of the evaluation area has changed by two digits or more is regarded as defective by applying an electric field of at least / cm or more for 1 second or more. A screening test method for a semiconductor integrated circuit, comprising predicting circuit reliability. 3. The evaluation area is formed to have a partly the same structure as the semiconductor integrated circuit, and the evaluation area is continuously operated for one minute or more at a normal operating power supply voltage or higher of the semiconductor integrated circuit. 3. The screening test method for a semiconductor integrated circuit according to claim 1, wherein the adjacent semiconductor integrated circuit is regarded as defective. 4. The screening test method for a semiconductor integrated circuit according to claim 2, wherein a laser, a halogen lamp, or an infrared lamp is used for the heating.