JP2986795B2 - Driving device for field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a driving device of a field effect transistor (hereinafter referred to as FET) in a PWM inverter using a switching element as a switching element.

[Prior Art] In a voltage-source inverter in which semiconductor switching elements are bridge-connected, in order to prevent a short circuit of each phase arm, a period (dead time) in which both switching elements of each arm are turned off is provided. This constitutes the driving device.

Hereinafter, a conventional example of this type of driving device will be described with reference to FIG. The figure shows one phase of a PWM type voltage source inverter, where 1 and 2 are DC power supplies (voltage = E /
2) 3 and 4 are FETs that constitute the inverter main circuit INV, 5
Is an inductive load, VL is an inverter output voltage applied to the load 5, and iL is a load current flowing through the load 5. Reference numeral 6 denotes a triangular wave generator, which generates a triangular wave signal (period T) VC as a carrier wave. A comparator 7 compares the voltage command signal V ^* with the triangular wave signal VC and outputs a PWM signal V
Create a and Vb. 8A is a timer circuit (on delay / off instant timer circuit, delay time td),
The PWM signal Va is led and rises with a delay of time td with respect to the PWM signal Va as shown in FIG. The output of the delayed waveform falling in synchronization with the falling is sent out, and the output is shaped by the waveform shaping circuit 9A as shown in FIG. Reference numeral 10A denotes a gate circuit which receives the output of the waveform shaping circuit 9A, creates a gate signal (on / off signal) VGA for the FET 3, and supplies it to the gate of the FET 3. The PWM signal Vb is supplied to a gate circuit 10B through a timer circuit (on delay / off instant timer circuit, delay time td) 8B and a waveform shaping circuit 9B, and the gate circuit 10B is a gate signal (on / off signal) of the FET4. VG
B is prepared and supplied to the FET4.

 FIG. 5 shows the waveform of each part of the drive circuit.

As is apparent from this waveform diagram, the on / off signal VGA of the FET 3 and the on / off signal VGB of the FET 4 always have the time td.
Since the FETs 3 and 4 are both turned off during the time td, the arm short circuit of the inverter main circuit INV does not occur.

[Problems to be Solved by the Invention] However, during the time td, there is a dead time during which voltage control is not performed. Therefore, on / off signal V _GA of FET3 is ON time than the PWM signal V _a corresponding to the voltage command signal V * shortens the time t _d min, while the on / off signal V _GB of FET4 voltage command signal V because the corresponding oN time than the PWM signal V _a is longer the time t _d min to *, the inverter output voltage VL, when the load current iL is positive polarity, the voltage command to indicate so in FIG. 5 (f) smaller than the value V ^*, if the reverse load current iL is negative, as shown in FIG. 5 (g), the voltage command value V ^* becomes larger, the output voltage VL is the voltage command value V ^* On the other hand, a shift corresponding to the dead time td occurs. Since this deviation (error) increases as the dead time td increases and as the frequency of the carrier (carrier frequency) increases, it is desirable that the dead time td be as small as possible. Then, since this is set using the timer circuits 8A and 8B, in order to ensure safety and reliability, taking into account the variation in the operation of the components of the gate circuits 10A and 10B and the operation of the FET3 and FET4, etc.
There is a problem that it is necessary to allow for a margin, and the dead time td cannot be set too short.

The present invention is based on the characteristics of the FET (it is a voltage drive element, and although there is a slight time delay determined by the input capacitance and the equivalent series resistance, it can be considered as being off when the gate voltage is negatively established) It is an object of the present invention to provide an FET driving device that can shorten the dead time and improve control accuracy and responsiveness based on the conventional technology.

Means for Solving the Problems In order to achieve the above object, the present invention provides a detection element which operates when each transistor is reverse-biased,
A configuration in which a gate circuit that receives an M signal and generates an ON signal of one of the FETs forming the arm generates an ON signal on condition that the one FET and the other FET forming the arm are reverse-biased. It is what it was.

[Operation] In the present invention, the gate of the other FET is controlled regardless of the state of the PWM signal until an off signal is supplied to one of the FETs constituting the arm and a reverse bias is established between the gate and the source of the FET. Since the circuit does not generate an ON signal, the arm does not short-circuit, and the dead time is automatically secured by the characteristics of the FET. Therefore, the dead time is smaller than when the setting circuit (timer circuit) sets the dead time.
It is possible to shorten the time as short as possible due to the circuit configuration.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 20A is a gate circuit of FET3, and 20B is a gate circuit of FET4. Gate circuit 20A includes power supplies 21a and 22a
It has an insulated gate PC1 connected in parallel to a DC circuit (both voltage Ea / 2), a series circuit of an on-signal transistor T11 and an off-signal transistor T12 connected in parallel to a series circuit of power supplies 21a and 22a. The output of the gate PC (in this example, composed of a photocoupler and an inversion element for inverting the polarity of the output) is connected to the base of the transistor T11 by the photocoupler TX2
(Phototransistor) X22, and is directly supplied to the base of the transistor T12. X11 is a primary side (light emitting diode) of the photocoupler TX1, and is connected via a backflow prevention diode D and a resistor r.
It is inserted between the gate and source of FET3 in the direction shown in the figure (gate-side forward direction). R is a resistance. The gate circuit 20B also includes an insulated gate (in this example, a photocoupler and an inverting element that inverts the output of the photocoupler) PC2 and a power supply 21b, which are connected in parallel to a series circuit of the power supplies 21b and 22b (both have a voltage Ea / 2). T2 for ON signal connected in parallel to the series circuit of 22b
1. It has a series circuit of an off signal transistor T22, and the output of the insulated gate PC2 is supplied to the base of the transistor T21 via the secondary side (phototransistor) X12 of the photocoupler TX1, and the base of the transistor T22 Supplied directly to X21 is the primary side (light emitting diode) of the photocoupler TX2 and is inserted between the gate and source of the FET3 via the backflow prevention diode D and the resistor r. R is a resistance. The PWM signals Va and Vb are guided to the insulated gates PC1 and PC2, respectively. The other configuration is the same as the conventional configuration shown in FIG. 3, and the same components are denoted by the same reference numerals.

Next, the operation of this embodiment will be described with reference to the waveform time chart of FIG. In FIG. 2, VG1 and VG2 indicate the gate voltages of the FETs 3 and 4, respectively.

In this configuration, since the light emitting diode X21 of the photocoupler TX2 is inserted between the gate and the source of the FET4 with the forward side as the gate side, the FET4 receives the ON signal VG2 and turns on, and the gate between the gate and the source. While the positive gate voltage VG2 is applied, the transistor X2 of the photocoupler TX2
2 is off, the on signal transistor T11 of the gate circuit 20A is in the off state, and no on signal is supplied to the FET 3 regardless of the state of the PWM signal Va. When the PWM signal Vb is turned off, the off signal transistor T22 of the gate circuit 20B is turned on to generate an off signal, and a certain short time Δtb determined by the characteristics of the FET 4 (input capacitance, equivalent series resistance, etc.).
After (<td), a reverse bias starts to be applied between the gate and the source of the FET4, and the phototransistor X2 of the photocoupler TX2
2 turns on. At this time, since the PWM signal Va is on, the transistor T11 is immediately turned on, and for a certain time Δta
The voltage V applied between the gate and source of FET3 after (<td)
G1 becomes a positive voltage and FET3 turns on. Simultaneously with the turning on of the FET3, the phototransistor X12 of the photocoupler TX1 turns off, and the transistor T21 of the gate circuit 20B turns off regardless of the state of the PWM signal Vb.

As described above, in the present embodiment, the ON transistor T11 in the gate circuit 20A of the FET 3 on the positive side of the arm receives the PWM signal Va via the photodiode X22 of the photocoupler TX2, and the light emitting diode X21 of the photocoupler TX2 Since the negative side FET 4 is off until the gate-source is reverse-biased upon receiving the off signal, the above-described setting circuit (timer circuit) is not provided.
FET4 is always turned on △ tb time after FET4 is turned off, and similarly, FET4 is always turned on △ ta time after FET3 is turned off.

In this embodiment, the dead times Δta and Δtb are FET3 and FET4
Is determined automatically, and the setting circuit (timer circuit) as described above does not need to be provided.
There is no need to allow for margins in consideration of the operation delays of 10A and 10B and variations in elements, and the dead time can be reduced as compared with the conventional case.

[Effects of the Invention] As described above, according to the present invention, since the operation delay of the FET itself becomes a dead time, the influence of the dead time on the inverter operation can be minimized. , The responsiveness can be improved. In addition, regarding the prevention of arm short circuit of the control element of each inverter phase, FET
From the characteristics of the element, one F of a pair of FETs
If a reverse bias is applied between the base and source of the ET, the other FET can be turned on at any time.Therefore, it is necessary to provide a reference power supply to set the reverse bias level to a certain voltage or higher like an inverter using a general transistor. There is no.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform time chart of each part of the above embodiment, FIG. 3 is a circuit diagram showing a conventional inverter drive circuit, and FIG. FIG. 5 is a waveform time chart for explaining the operation of the timer circuit in FIG. 3, 4, field-effect transistor, 6, triangular wave generator 7, comparator, 20A, 20B gate circuit T11, T12, T21, T22 transistor, TX1, TX2 ...
Photocoupler PC1, PC2 …… Insulated gate

Claims (1)

(57) [Claims] In a field effect transistor driving device for a PWM type voltage inverter using a field effect transistor as a switching element constituting an arm of each phase of a main circuit, a pair of field effect transistors constituting each phase arm are provided. There are first circuit means for giving ON / OFF commands at opposite phases, and second circuit means for allowing ON command of one field effect transistor when the other field effect transistor is reverse biased. The second circuit means is a photocoupler, the primary side of which is inserted between the gate and the source of one field effect transistor, and the secondary side of which is incorporated in the gate circuit of the other field effect transistor. A field effect transistor driving device for a PWM type voltage type inverter.