JP2986932B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dynamic random access memory (DRAM).

[0002]

BACKGROUND ART FIG. 3 (a) ~ (f) are process sequence sectional views showing a manufacturing method of the conventional semiconductor device. Figure 3 As shown in (a), n ⁺ -type active region 100 on the silicon substrate 1 of p-type
, Gate insulating film 100a and word line 2 serving as a gate electrode
Switching transistor, element isolation film 3a
And an insulating film 100b is formed.

[0003] Next, as shown in FIG. 3 (b), Si on the surface
After depositing the O ₂ film 3 and forming an opening in the SiO ₂ film 3, a bit line 4 electrically connected to one active region 100 of the switching transistor is formed through the opening. Then, a SiO ₂ film 5 is further formed on the surface. Next, as shown in FIG. 3 (c), the contact window 6 reaching the active region 100 of the switching transistor formed on the silicon substrate 1 is formed by anisotropic etching.
Openings are formed in the O ₂ films 3 and 5. Then, after forming a polysilicon film 7 containing impurities on the SiO ₂ film 5 and the contact window 6, a resist pattern 8 is formed on the polysilicon film 7.

[0004] Next, as shown in FIG. 3 (d), a resist pattern 8 as a mask, by RIE (reactive ion etching), by all vertically etched polysilicon film 7, the pattern shape memory node 9 is formed. Next, as shown in FIG. 3 (e), the surface of the storage node 9, to form a dielectric film 10 made of silicon oxide (SiO ₂₎ and silicon nitride (SiN), a cell on the dielectric film 10 plate 11a after forming, SiO ₂ film 12b is deposited on the surface.

[0005] Then, as shown in FIG. 3 (f), SiO ₂
After depositing an aluminum film on the film 12b, the aluminum film is etched into a wiring shape to form an aluminum wiring 13b.

[0006]

However, in such a conventional method of manufacturing a semiconductor device, the edge of the memory cell array region 14 has a substantially vertical shape, and the memory cell array region 14 and the peripheral circuit region (not shown). A step occurs at the boundary 16 between the two. As a result, the aluminum film formed on the boundary portion 16 cannot be favorably etched into a wiring shape, and an etching residue occurs. As a result, there is a problem that the formed aluminum wiring 13b is short-circuited.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a short circuit of an aluminum wiring and improving the yield of wiring formation in view of the above problems.

[0008]

A method of manufacturing a semiconductor device according to claim 1 is as follows. An interlayer insulating film is formed on a semiconductor substrate having a switching transistor formed in a memory cell array region. A contact window reaching the active region of the switching transistor is formed in the interlayer insulating film excluding the edge of the memory cell array region. A first conductive film is formed on the interlayer insulating film and on the active region of the switching transistor via the contact window. After forming a resist pattern on the first conductive film, the first conductive film is anisotropically etched using the resist pattern as a mask to form a storage node and to form an edge portion of the memory cell array region. A forward tapered portion is formed on a side wall of the formed first conductive film. A dielectric film is formed on the surface of the storage node. A second conductive film serving as a cell plate is formed on the surface of the dielectric film.

[0009]

[0010]

According to the structure of the first aspect, the first conductive film electrically connected to the active region of the switching transistor is anisotropically etched to form a storage node and to form an edge of the memory cell array region. Forming a forward tapered portion on the side wall of the first conductive film formed in the portion; Thereby, the edge of the memory cell array region is made gentle.
Therefore, the step at the edge of the memory cell array region, that is, at the boundary between the memory cell array region and the peripheral circuit region can be reduced.

[0011]

[0012]

1A to 1F are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of FIG. As shown in FIG. 1A, an n ⁺ -type active region 10 is formed on a p-type silicon substrate 1.
0, a gate insulating film 100a and a word line 2 serving as a gate electrode.
a and the insulating film 100b are formed. The region where the switching transistor is formed becomes a memory cell array region.

[0013] Next, as shown in FIG. 1 (b), depositing a SiO ₂ film 3 as an interlayer insulating film on the surface, after forming the contact windows in the SiO ₂ film 3, Sui through the opening
A bit line 4 electrically connected to one of the active regions 100 of the switching transistor is formed. Then, an SiO ₂ film 5 serving as an interlayer insulating film is further formed on the surface. Next, as shown in FIG. 1C, a switching transistor is formed on the SiO ₂ films 3 and 5 excluding the edge of the memory cell array region.
A contact window 6 reaching the other active region 100 is formed by anisotropic etching.

Then, a polysilicon film 7 containing P (phosphorus), which is an impurity to be a first conductive film, is deposited on the SiO ₂ film 5 and the active region 100 via the contact window 6 and then deposits the polysilicon film 7. A resist pattern 8 is formed on the polysilicon film 7. Next, as shown in FIG. 1 (d), by using the resist pattern 8 as a mask and etching the polysilicon film 7 by anisotropic etching by ECR plasma etching, a storage node 9 having a pattern shape is formed. A forward tapered portion X is formed on the side wall of the polysilicon film 9a formed at the edge of the memory cell array region. The forward tapered portion X moderates the step at the edge of the memory cell array region, that is, at the boundary between the memory cell array region and the peripheral circuit region.

At this time, the etching conditions of the polysilicon film 7 are as follows: SiCl ₄ : flow rate 30 [sccm], SF ₆ : flow rate 1
8 [sccm], C ₄ F ₈ : flow rate 70 [sccm], cooling He:
The flow rate was 10 [sccm], the RF power was 160 [W], the microwave was 200 [mA], the gas pressure was 2 [Pa], the electrode interval was 45 [mm], and the overetch rate was 70 [%].

Next, as shown in FIG.
9 on the surface of silicon oxide (SiO _Two) And silicon nitride
A dielectric film 10 made of silicon (SiN) is formed.
A polysilicon film serving as a second conductive film on the conductor film 10
After forming the cell plate 11 consisting of
SiO which is an edge film_TwoA film 12 is deposited. And FIG.
As shown in FIG._TwoAluminum on the film 12
After depositing the film, this aluminum film is etched into a wiring shape.
To form an aluminum wiring 13
(See FIG. 2).

At this time, due to the forward tapered portion X formed on the side wall of the polysilicon film 9a at the edge of the memory cell array region 14, the step at the boundary 16 between the memory cell array region 14 and the peripheral circuit region 15 is moderate. Because
The aluminum film formed at the boundary portion 16 can be favorably etched into a wiring shape, and the aluminum wiring 13 can be formed without leaving an etching residue of the aluminum film at the boundary portion 16. Therefore, boundary 1
It is possible to prevent the aluminum wiring from being short-circuited due to the etching residue of No. 6, and to improve the yield of wiring formation.

In the step shown in FIG.
Using ₆ and C ₄ F _8, but not limited to, CH ₂ F
The same effect can be obtained by anisotropic etching with a gas system using ₂ or the like.

[0019]

[0020]

[0021]

[0022]

In the first embodiment, the polysilicon film 7 containing P (phosphorus) as an impurity is used as the first conductive film to be the storage node 9, but the present invention is not limited to this. May contain n-type As (arsenic). The same effect can be obtained even if the n-type and p-type conductivity types of the components are replaced.

A dummy cell having no contact in the active region of the switching transistor is provided at the edge of the memory cell array region, and a forward tapered portion is formed in the dummy cell by anisotropic etching using ECR. The step at the boundary between the cell array region and the peripheral circuit region may be reduced.

[0025]

According to the first aspect of the present invention, the storage node is formed by anisotropically etching the first conductive film electrically connected to the active region of the switching transistor. At the same time, a forward tapered portion is formed on the side wall of the first conductive film formed at the edge of the memory cell array region. Thereby, the edge of the memory cell array region is made gentle. Therefore, the step at the edge of the memory cell array region, that is, at the boundary between the memory cell array region and the peripheral circuit region can be reduced.

As a result, when aluminum wiring is formed in the memory cell array region and the peripheral circuit region, the aluminum film formed at the boundary between the memory cell array region and the peripheral circuit region can be etched in a good wiring shape. The aluminum wiring can be formed without leaving any etching residue at the boundary. Therefore,
A short circuit of the aluminum wiring can be prevented, and the yield of wiring formation can be improved.

[0027]

[0028]

[Brief description of the drawings]

FIGS. 1A to 1F are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of FIG. 1 (f).

3 (a) to 3 (f) are cross-sectional views in the order of steps showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 semiconductor substrate 3,5 SiO_TwoFilm (interlayer insulating film) 6 contact window 7 polysilicon film (first conductive film) 8 resist pattern 9 storage node 10 dielectric film 11 cell plate 12 SiO_TwoFilm (interlayer insulating film)  14 memory cell array area 100 active area X forward tapered part

(56) References JP-A-1-143351 (JP, A) JP-A-58-176950 (JP, A) JP-A-62-2353 (JP, A) (58) Fields investigated (Int .Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242 H01L 21/768

Claims (1)

(57) [Claims] A step of forming an interlayer insulating film on a semiconductor substrate having a switching transistor formed in a memory cell array region; and forming an interlayer insulating film on an active region of the switching transistor except for an edge of the memory cell array region. Forming a contact window reaching the first conductive film; forming a first conductive film on the interlayer insulating film and on the active region of the switching transistor via the contact window; and forming a first conductive film on the first conductive film. After forming a resist pattern, the first conductive film is anisotropically etched using the resist pattern as a mask to form a storage node and to form a first conductive film formed at an edge of the memory cell array region. Forming a forward tapered portion on the side wall of the conductive film, and forming a dielectric film on the surface of the storage node And a cell on the surface of this dielectric film
Forming a second conductive film serving as a plate.