JP2988138B2 - Bipolar transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art Compound semiconductor heterojunction bipolar transistors (hereinafter abbreviated as HBTs) are expected to be applied to ultrahigh-speed digital integrated circuits and microwave analog circuits due to their excellent high-frequency characteristics. By the way, HBT
In order to further increase the speed of an element, it is known to miniaturize the element structure. As an index showing the high-frequency characteristics of the transistor elements, although current gain _cut-off frequency f _T and the maximum oscillation frequency f _max is known, f _T and f _max is
In the case of a bipolar transistor, it is expressed as Equations 1 and 2 by parameters specific to the crystal structure of the element and resistance values and capacitance values specific to the structure of the element.

[0003]

(Equation 1)

[0004]

(Equation 2)

Here, I _C is the collector current, C _BE is the base-emitter capacitance, C _BC is the base-collector capacitance,
τ _B is the base traveling time of minority carriers in the base region,
tau _C collector transit time of majority carriers in the collector region, R _E is an emitter resistor, R _B represents a base resistor, R _C is the collector resistance.

In order to improve the f _T and f _max of the element, it is necessary to reduce the values of τ _B and τ _C and to reduce the resistance and capacitance. τ _B and τ _C are determined by the crystal structure of the device. In order to reduce each resistance value, the contact resistance (ρ _C ) between each electrode and the semiconductor layer is reduced, and, for example, by forming the base electrode in a self-aligned manner with respect to the emitter mesa, the intrinsic base layer and the base are formed. The distance from the lead electrode is reduced, and the resistance at the base lead portion is reduced.

Next, each of the capacitances of C _BE and C _BC is provided between the base and the emitter in the intrinsic region of the transistor and between the base and the emitter.
It is divided into a depletion layer capacitance between the collector and an external capacitance formed outside the transistor intrinsic region. In the former, the width of the depletion layer at the pn junction can be controlled by changing the impurity concentration of each semiconductor layer, and the capacitance value can be reduced. However, there is a balance with the reduction of τ _B and τ _C by the crystal structure. To some extent.

The junction capacitance of the intrinsic region of the transistor can be reduced by reducing the area (base-emitter junction area, base-collector junction area) of the intrinsic transistor region. As for the external capacitance, it is effective to reduce the area outside the intrinsic region together with the semi-insulating implantation technique.

As described above, in order to increase the speed of the transistor, it is necessary to optimize the semiconductor crystal structure and to miniaturize the element.

FIG. 10 shows a conventional example of a method for manufacturing an HBT. In FIG. 10, first, proton ions are implanted.
Semi-insulation of the ion-implanted region 11 for device isolation is performed, and subsequently, an emitter electrode 9 is formed (FIG. 10A).
With this emitter electrode 9, the emitter contact layer 6 and the emitter layer 5 are processed by anisotropic dry etching to expose the base layer 4 (see FIG. 10B). Thereafter, the collector layer immediately below the base electrode outside the transistor intrinsic region is semi-insulated by proton ion implantation, and an ion implantation region 12 for reducing parasitic capacitance is formed to reduce the base-collector capacitance [FIG. 10
(See (b)). Subsequently, an emitter side wall 10 made of an insulating film is formed (see FIG. 10B), and the base electrode 8 is vapor-deposited in a self-aligned manner (see FIG. 10C). Subsequently, a part of the collector layer 3 is etched to expose the collector contact layer 2, and the collector electrode 7 is deposited (see FIG. 10D). This is a HBT self-alignment process. Here, the intrinsic region of the transistor is a region where the proton ion implantation has not been performed twice, that is, immediately below the emitter electrode 9. Therefore, the emitter-base capacitance and the base-collector capacitance are determined by the area of the emitter electrode 9 formed first, and reducing the width of the emitter electrode 9 leads to reduction of C _BE and C _BC. The speed of the device can be increased. However, in the conventional example shown in FIG. 10, the width of the emitter electrode 9 is
The optical exposure using a photoresist is about 0.5 μm. In order to further reduce the width of the emitter electrode 9, it is possible to use EB or FIB exposure, but the limit is still about 0.1 μm. In addition, exposure techniques such as EB and FIB are not suitable for manufacturing an HBT integrated circuit because the throughput cannot be increased because of the direct writing method.

[0011]

In the prior art, when miniaturizing a transistor element, as shown in FIG. 10, an emitter electrode 9 (or a dummy emitter made of an insulating film) is formed on an emitter contact layer 6 as shown in FIG. Is formed by patterning. The emitter electrode 9 (or dummy emitter) is processed by etching the emitter contact layer 6 and the emitter layer 5 to expose the base layer 4, and the emitter electrode 9 (or dummy emitter) is formed. The base electrode 8 is formed in a self-aligned manner. Therefore, the junction area of the intrinsic region of the transistor is determined by the emitter electrode 9 (or the emitter electrode 9 formed on the emitter contact layer 6).
(Dummy emitter).
Therefore, in order to miniaturize the element, the emitter electrode 9 is required.
(Or a dummy emitter) needs to be reduced in size.

By the way, when the current optical exposure technology is used, the processing size is limited to about 0.5 μm. Also,
Electron beam exposure (EB) and focused ion beam (FIB)
When the exposure technology is used, processing of about 0.1 μm is possible. However, since these exposure technologies are direct writing technologies, there is a problem in throughput, and they are not suitable for an integrated circuit manufacturing technology.

Therefore, it is important to develop a processing technique for the fine emitter electrode 9 which can be formed by the conventional optical exposure technique.

By the way, even if the HBT element is miniaturized, the following problem is considered to occur. That is, since the electrodes are fine, the resistance in the electrode lead-out direction increases. In addition, when the transistor is operated at high speed, the current flowing through the wiring flows only in the vicinity of the display in a high frequency region, so that there is a problem that the extraction resistance of the electrode increases in the high frequency region. Thus, when the emitter resistance of the transistor increases due to the increase in the emitter electrode 9,
As is clear from the expressions of f _T and f _max described above, there is a problem that the high-frequency characteristics of the transistor are impaired.

Therefore, when miniaturizing a bipolar transistor, it is necessary to simultaneously increase the cross-sectional area of the electrode and reduce the resistance of the electrode. It is important to take measures to reduce the resistance of the device.

Further, even if fine elements can be manufactured, when forming a circuit with these elements, it is necessary to draw out each electrode of each element with a sufficient length from a margin in a wiring step.

This means that even if the element is miniaturized, the area of the element region is increased by the length of the extraction electrode, thereby preventing the element from being integrated at a higher density and increasing the wiring length. As a result, the wiring delay becomes large, and the operation speed of the circuit cannot sufficiently bring out the high speed of the fine element.

An object of the present invention is to use a conventional optical exposure technique without adding a large number of steps as compared with the conventional bipolar transistor self-alignment process, and to use a high-throughput fine bipolar transistor. An object of the present invention is to provide a method of manufacturing a bipolar transistor which can manufacture an element and does not cause an increase in resistance of an electrode due to miniaturization. Another object of the present invention is to achieve a compact arrangement of a circuit constituted by the fine emitter element of the present invention and a reduction in wiring, thereby enabling high-speed operation of the circuit.

[0019]

In order to solve the problem that the transistor electrode cannot be miniaturized, a method of manufacturing a bipolar transistor according to the present invention comprises a method for manufacturing a bipolar transistor on a semiconductor substrate, comprising: A step of forming a semiconductor layer having at least a base layer 4, an emitter layer 5, and an emitter contact layer 6, a step of separating elements using ion implantation, and an insulating film patterned on the emitter contact layer 6 13, forming an emitter electrode metal 92 by a vapor deposition method having a high covering property, processing the emitter electrode metal 92 into an annular emitter electrode 91 by using anisotropic dry etching, and removing the emitter electrode metal 92. Removing the insulating film 13 using etching capable of obtaining a selectivity with respect to the annular emitter electrode 91; The emitter contact layer 6 and the emitter layer 5 are etched in a self-aligned manner on the emitter contact layer 6 using the annular emitter electrode 91 left on the side of the outer periphery of the insulating film 13 as a mask. Exposing the annular emitter electrode 91, the emitter contact layer 6, and the side wall 10 made of an insulating film on the side of the emitter layer 5.
And at least a step of self-aligningly depositing the base electrode 8 on the side wall 10 made of an insulating film using the patterned photoresist 14.

In order to solve the problem of the increase in the resistance of the fine emitter electrode, particularly at high frequencies, the structure of the bipolar transistor according to the present invention is based on the semiconductor substrate 1.
A collector contact layer 2, a collector layer 3 and a collector electrode 7 on the collector contact layer 2, a base layer 4 on the collector layer 3, and an emitter layer 5 on the base layer 4.
And a base electrode 8, an emitter contact layer 6 on the emitter layer 5, and at least an emitter electrode 9 on the emitter contact layer 6, wherein the height of the emitter electrode 9 is The configuration is larger than the width.

Further, in order to effectively reduce the extraction resistance of the emitter electrode and thereby improve the high-frequency characteristics of the device, the method of manufacturing a bipolar transistor according to the present invention comprises the steps of: Forming a flattening photoresist 16 on the entire surface of the wafer after the step of forming the base electrode 8, and processing the flattening photoresist 16 to expose at least a part of the emitter electrode 9; The method includes a step of forming the second emitter electrode 19 so as to cover at least a part of the region of the emitter electrode 9.

Further, in order to achieve a compact arrangement of the circuit constituted by the fine emitter elements of the present invention and to shorten the wiring, the method of manufacturing a bipolar transistor according to the present invention employs a method for separating at least two or more elements. The method includes a step of forming a ring-shaped emitter electrode 91 on the region 15 not subjected to ion implantation by the method for manufacturing a bipolar transistor according to the present invention, and a step of removing a part of the ring-shaped emitter electrode 91.

[0023]

According to the present invention, the width of the emitter electrode 9 can be formed with a reproducibility of less than several thousand angstroms, and a bipolar transistor having an emitter width of less than several thousand angstroms in a self-aligned manner can be manufactured using the emitter electrode 9. , Becomes possible. In addition, since the width of the emitter electrode 9 is determined by the thickness of the emitter electrode metal 92 deposited so as to cover the patterned insulating film 13, a size of several hundred angstroms can be realized. Furthermore, since this structure can be realized by a normal optical exposure technique without using an exposure technique such as EB or FIB, the throughput can be improved.

In a fine bipolar transistor,
Since the width of the emitter electrode 9 is very small, the cross-sectional area and the surface area of the emitter electrode 9 are significantly reduced. In particular, when operated at a high frequency, the emitter metal resistance increases and the high-frequency characteristics of the element deteriorate. However, in contrast, the bipolar transistor of the present invention has a structure in which the height of the emitter electrode 9 is larger than its width, so that the cross-sectional area and the surface area of the emitter electrode 9 can be increased.
Such a problem can be solved and the high frequency characteristics of the element can be improved.

Further, by locating a part of the fine emitter electrode 9 and forming the second emitter electrode 19 on the emitter electrode 9, the resistance of the lead portion at the electrode metal part is greatly increased. Can be expected, and the high-frequency characteristics of the element can be greatly improved.

Further, the structure in which the emitter electrode of the micro-bipolar transistor element manufactured according to the present invention is connected does not require the emitter electrode to be drawn out sufficiently for wiring, so that the area of the element region can be reduced and the wiring between elements can be reduced. Therefore, it is possible to reduce the length of the circuit, and to realize an ultra-high-speed operation of a circuit configured by using the transistor having the differential pair configuration.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show a method of manufacturing a bipolar transistor according to a first embodiment of the present invention. 1 and 2, first, using proton injection,
An ion implantation region 11 for element isolation is formed. Subsequently, a patterned insulating film 13 is formed on the emitter contact layer 6, and an emitter electrode metal 92 is deposited so as to cover the entire surface of the emitter contact layer 6 and the insulating film 13 [FIGS. 1 (a) and 1 (b)]. )reference〕. At this time, as a method of depositing the emitter electrode metal 92, a sputtering method with good coatability is used so that the emitter electrode metal 92 is also deposited on the side of the insulating film 13.

Subsequently, the deposited emitter electrode metal 92
Is removed by processing with strong anisotropic dry etching (see FIG. 1C). Next, the emitter electrode metal 92
In contrast, only the insulating film 13 is removed by an etching method that increases the etching rate of the insulating film 13 [FIG.
(D)]. By this step, the annular emitter electrode 91 adhered along the side of the patterned insulating film 13 is left on the emitter contact layer 6.

Next, the emitter contact layer 6 and the emitter layer 5 are formed using the annular emitter electrode 91 as a mask.
Is etched to expose the base layer 4 (see FIG. 2A). Here, the collector layer immediately below the base electrode 8 is semi-insulated by proton ion implantation to form an ion implantation region 12 for reducing parasitic capacitance, thereby reducing the base-collector capacitance and defining the intrinsic region of the device. I do. Subsequently, a side wall 10 made of an insulating film is formed [FIG.
Then, the base electrode 8 is formed in a self-aligned manner on the side wall 10 made of the insulating film by the lift-off method using the photoresist 14 (see FIG. 2C). Subsequently, the collector layer 3 is etched to expose the collector contact layer 2, and a collector electrode 7 is formed [FIG.
(D)].

Here, the formed annular emitter electrode 9 is formed.
The width of 1 is determined by the thickness of the patterned insulating film 13 and the thickness of the emitter electrode metal 92 to be deposited. By optimizing the thickness of the insulating film 13 and the emitter electrode metal 92, the annular emitter electrode The width of 91 can be on the order of several thousand angstroms to several hundred angstroms. Therefore, as compared with a device manufactured by a conventional manufacturing method, when the emitter length is the same, the area of the intrinsic region of the transistor can be reduced to 1/10 or less. Therefore, the junction areas C _BE and C _{BC of} the bipolar transistor are greatly reduced, and the high f _T and f _max
Can be obtained, and the high-frequency characteristics of the element can be improved.

FIG. 3A is a top view of the HBT manufactured according to the first embodiment of the present invention, and FIG. 3B is a side view. A fine annular emitter electrode 91 is formed in a rectangular annular shape, and the transistor intrinsic region is located immediately below two opposing sides of the annular emitter electrode 91. The base electrode 8 is also formed inside the annular emitter electrode 91, so that the base current can be made uniform between the two transistor intrinsic regions.

FIG. 4 is a sectional structural view of an HBT element formed by the manufacturing method according to the first embodiment of the present invention. When the manufacturing method shown in FIGS. 1 and 2 is used, the shape of the formed fine emitter electrode 9 has a structure in which the height is much larger than the width. This is because, even when a fine photoresist pattern is formed using EB or FIB exposure, it is difficult to uniformly embed a vapor-deposited metal in an opening having a high aspect ratio (a depth is larger than an opening width). Because
The structure of the emitter electrode 9 that can be formed by this embodiment cannot be realized. Further, when the width of the emitter electrode 9 is reduced, the cross-sectional area of the emitter electrode 9 is reduced, and
Although the resistance in the extraction direction of the emitter electrode 9 increases,
In the structure of the emitter electrode 9 according to the present embodiment, the height can be increased as compared with the width, so that the cross-sectional area of the emitter electrode 9 can be increased, and therefore, the rise of the extraction resistance of the emitter electrode 9 can be suppressed.

In particular, when the transistor is used in a high frequency region, the current flows only near the surface of the emitter electrode 9 and causes an increase in the resistance of the emitter electrode 9. In the structure of the emitter electrode 9 according to the present embodiment, The surface area can be increased, so that an increase in the resistance of the emitter electrode 9 can be suppressed even in a high frequency region.

FIG. 5 is a diagram showing a method of manufacturing a bipolar transistor according to a second embodiment of the present invention. FIG. 5 (b)
FIG. 5A is a view in which a part (upper and lower portions of a broken line) of the annular emitter electrode 91 in FIG.
After forming 1, pattern with photoresist
This part is removed by ion milling,
By performing the self-alignment process, FIG.
Transistor structure can be realized. Also in this case, similarly to the transistor element of FIG. 3, the base electrode 8 is also formed between the two emitter stripes, so that the base current is uniform between the two transistor intrinsic regions.

FIG. 6 is a view showing a method of manufacturing a bipolar transistor according to a third embodiment of the present invention. In the present embodiment, when proton ions are implanted into the ion implantation region 11 for device isolation, two regions 15 where no ion implantation for device isolation is performed are provided. An annular emitter electrode 91 is formed so as to straddle the region 15 where no ion implantation has been performed. Thereafter, similarly to the method described in the second embodiment, a part of the annular emitter electrode 91 is removed, and the device is formed in a self-aligned manner.

In this manufacturing method, two symmetrical fine emitters HBT can be formed, and the insulating film 13 and the emitter electrode metal 9 are formed during the step of forming the annular emitter electrode 91.
By sufficiently improving the uniformity of the film formation and processing method of No. 2, the size of the fine emitter electrode 9 of each element can be made highly uniform, so that the characteristics between the two elements can be made highly uniform. it can.

FIG. 7 is a view showing a plurality of transistor pairs manufactured by the method for manufacturing a bipolar transistor according to the third embodiment of the present invention. In FIG. 7, a plurality of non-ion-implanted regions 15 are provided at the time of proton ion implantation for element isolation, and an annular emitter electrode 91 is formed thereon (see FIG. 7A). A part of the electrode 91 is removed, and an element is manufactured by a self-alignment process using the same manufacturing method as in the first embodiment.
According to this manufacturing method, a plurality of fine emitter HBT elements symmetrical two by two can be formed uniformly as shown in FIG. 7B. Therefore, this embodiment is suitable for forming an integrated circuit using a fine HBT element, particularly, an ultra-high-speed digital circuit including a differential pair or a gate array.

FIG. 8 is a view showing a method of manufacturing a bipolar transistor according to a fourth embodiment of the present invention. In FIG. 8A, at the time of proton ion implantation for element isolation,
Two regions 15 where no ions are implanted are provided, and an annular emitter electrode 91 is formed. Subsequently, one side of the annular emitter electrode 91 is removed, and two fine emitter HBT elements are formed in a self-aligned manner. This structure is a structure in which the emitter electrodes of two elements are connected, and has the same circuit configuration as the transistor differential pair in FIG. By the way, conventionally, when forming a differential pair, 2
It was common to form two HBT elements and connect their emitter electrodes to each other later by wiring. However, this method involves extracting an emitter extraction electrode of each element with a sufficient length,
Because of the connection, the element size increases accordingly,
The wiring length was long. However, in the present embodiment, it is possible to connect the emitter electrodes of the two elements very close to the intrinsic region of the element and with a short wiring length. The size of the transistor can be reduced, and the wiring length can be reduced. The transistor differential pair formed by this manufacturing method is most suitable for analog applications such as a differential amplifier and digital applications such as an emitter coupled logic (ECL).

With this configuration, excellent high-frequency characteristics of the element obtained by making the emitter fine can be achieved, a compact layout of the element can be achieved by shortening the wiring, and the propagation delay in the wiring can be shortened. It is possible to realize a high gain and a wide band and an ultra-high-speed operation of a flip-flop (F / F) circuit having an ECL configuration.

FIG. 9 shows a method of manufacturing a bipolar transistor according to a fifth embodiment of the present invention. FIG. 9 (a)
FIG. 5 is a cross-sectional view in which a flattening photoresist 16 is applied on the entire surface of the HBT element shown in FIG. Subsequently, the photoresist 1 for planarization is
6 is etched back to locate a part of the emitter electrode 9 (see FIG. 9B). Then, using the patterned photoresist 18,
A second emitter electrode 19 is formed (FIG. 9C,
(D)]. By adopting such a configuration of the emitter electrode 9 and the second emitter electrode 19, the resistance of the emitter electrode 9 in the lead-out direction can be significantly reduced. The emitter electrode 9 of the bipolar transistor element manufactured according to the present embodiment can be made smaller and the cross-sectional area of the emitter electrode 9 can be increased, so that the advantage that the emitter resistance can be reduced can be further greatly improved. Further, since the second emitter electrode 19 can be formed on the high emitter electrode 9, the distance between the second emitter electrode 19 projecting on the emitter electrode 9 and the base electrode 8 can be increased, and the C
Don't worry about increasing _BE . Therefore, the device can be operated at a significantly high frequency. Here, in this embodiment, all the explanations are made using the emitter-top type bipolar transistor. However, the effects of the manufacturing method and structure of the present invention are the same for the collector-top type bipolar transistor.

[0042]

As described above, according to the present invention, it is possible to manufacture a fine emitter electrode with a size that cannot be realized by the conventional technology. The HBT element manufactured using this fine emitter electrode has a junction capacitance C _BE and _CBC are greatly reduced, and thus, the high frequency characteristics of the transistor are improved. Further, the fine emitter electrode of the HBT element manufactured according to the present invention can have a shape whose height is sufficiently large with respect to its width, so that the cross-sectional area and surface area of the emitter electrode can be increased. , And an increase in emitter resistance during high-frequency operation can be suppressed. Furthermore, in the HBT differential pair according to the manufacturing method of the present invention, miniaturization of elements and shortening of inter-element wiring can be achieved, and therefore, ultrahigh-speed operation of a circuit configured using the transistors of the differential pair configuration can be realized. It has the effect of. Further, in a transistor having a structure in which a wide second emitter electrode is provided on a fine emitter electrode manufactured according to the present invention, a large reduction in resistance in the direction in which the emitter electrode is drawn out can be achieved between the base electrode and the base electrode. Since the capacitance can be reduced at the same time, there is an effect that the element can be operated at a higher frequency.

[Brief description of the drawings]

FIG. 1 is a view showing a part of a method for manufacturing a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a view showing the remaining part of the method for manufacturing the bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a bipolar transistor manufactured according to a first embodiment of the present invention.

FIG. 4 is a sectional structural view of a bipolar transistor formed by the manufacturing method according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a method for manufacturing a bipolar transistor according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a method for manufacturing a bipolar transistor according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a plurality of transistor pairs manufactured by a method for manufacturing a bipolar transistor according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a method for manufacturing a bipolar transistor according to a fourth embodiment of the present invention.

FIG. 9 is a view illustrating a method of manufacturing a bipolar transistor according to a fifth embodiment of the present invention.

FIG. 10 is a view showing a conventional method of manufacturing an HBT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Collector contact layer 3 Collector layer 4 Base layer 5 Emitter layer 6 Emitter contact layer 7 Collector electrode 8 Base electrode 9 Emitter electrode 91 Annular emitter electrode 92 Emitter electrode metal 10 Side wall 11 Ion implantation region for element isolation REFERENCE SIGNS LIST 12 Ion implantation region for reducing parasitic capacitance 13 Insulating film 14 Photoresist 15 Non-ion-implanted region for device isolation 16 Planarization photoresist 18 Photoresist 19 Second emitter electrode

Claims (5)

(57) [Claims] 1. A collector contact layer on a semiconductor substrate, a collector layer and a collector electrode on the collector contact layer, a base layer on the collector layer, an emitter layer and a base electrode on the base layer, and an emitter on the emitter layer. contact layer, the fine emitter of the bipolar transistor structure in which the emitter electrode in the emitter contact layer is formed at least, larger than the width of the height emitter electrode of the emitter electrode
And the emitter contact layer, the emitter layer, and the collector
The width of the layer is almost the same as the width of the emitter electrode,
On the side of the emitter electrode, emitter contact layer and emitter layer
Equipped with sidewalls made of insulating film, around the transistor region
A bipolar transistor comprising an ion implantation region for element isolation . 2. A step of forming a collector contact layer, a collector layer, a base layer, an emitter layer, and a semiconductor layer having at least an emitter contact layer on a semiconductor substrate, and partially omitting a part of the semiconductor layer by ion implantation. Forming an ion-implanted region for insulation and isolation between elements, forming a patterned insulating film on the emitter contact layer, depositing an emitter electrode metal, and using anisotropic dry etching to form the emitter electrode. Processing the metal into an annular emitter electrode and removing the same; removing the insulating film using etching capable of obtaining a selectivity with respect to the annular emitter electrode; and removing the insulating film on the emitter contact layer. Using the annular emitter electrode left on the outer peripheral side as a mask, the emitter contact layer and the emitter Exposing the base layer, etching the annular emitter electrode, the emitter contact layer, and forming a sidewall made of an insulating film on a side of the emitter layer, using a patterned photoresist. And e. Depositing a base electrode in a self-aligning manner on the side wall made of an insulating film. 3. A step of forming a collector contact layer, a collector layer, a base layer, an emitter layer, and a semiconductor layer having at least an emitter contact layer on a semiconductor substrate, and partially removing the semiconductor layer by ion implantation. Forming an ion-implanted region for insulation and isolation between elements, forming a patterned insulating film on the emitter contact layer, depositing an emitter electrode metal, and using anisotropic dry etching to form the emitter electrode. Processing the metal into an annular emitter electrode and removing the same; removing the insulating film using etching capable of obtaining a selectivity with respect to the annular emitter electrode; and removing the insulating film on the emitter contact layer. A step of forming two emitter electrodes by etching away a part of the annular emitter electrode left on the outer peripheral side; Using serial two emitter electrode as a mask to expose the base layer by etching the emitter contact layer and the emitter layer, the 2
Forming a side wall made of an insulating film on the side of the emitter electrode, the emitter contact layer, and the emitter layer; and forming a self-aligned side wall on the side wall made of the insulating film using a patterned photoresist. And a step of depositing a base electrode on the bipolar transistor. 4. A step of forming a collector contact layer, a collector layer, a base layer, an emitter layer, and a semiconductor layer having at least an emitter contact layer on a semiconductor substrate, and ions for separating at least two or more elements. Forming a non-implanted region; forming a patterned insulating film on the non-implanted region for separating at least two or more elements; depositing an emitter electrode metal; Removing the emitter electrode metal by processing into an annular emitter electrode using reactive dry etching, and removing the insulating film using etching capable of obtaining a selectivity with respect to the annular emitter electrode; small portions of said annular emitter electrode left on the outer peripheral side of the insulating film to the emitter contact layer is etched away Forming a Kutomo two or more emitter electrode, a step of exposing the base layer by the use of at least two or more emitter electrode as a mask, etching the emitter contact layer and the emitter layer, at least 2 more than five emitter electrodes, the emitter contact layer, and forming a sidewall made of an insulating film on the side of the emitter layer, the non-ion implantation for separating between at least two device regions Forming a base electrode in a self-aligned manner on the side wall made of an insulating film using a patterned photoresist. 5. A step of forming a collector contact layer, a collector layer, a base layer, an emitter layer, and a semiconductor layer having at least an emitter contact layer on a semiconductor substrate, and partially omitting a part of the semiconductor layer by ion implantation. Forming an ion-implanted region for insulation and isolation between elements, forming a patterned insulating film on the emitter contact layer, depositing an emitter electrode metal, and using anisotropic dry etching to form the emitter electrode. Ring the metal
Removing processed into data electrode, remaining on the insulating film and removing by etching can take a selectivity with respect to the emitter electrode, the sides of the outer periphery of the insulating film on the emitter contact layer Using the formed emitter electrode as a mask, etching the emitter contact layer and the emitter layer to expose a base layer; and forming the emitter electrode, the emitter contact layer, and
Forming a sidewall made of an insulating film on a side portion of the emitter layer; depositing a base electrode in a self-aligned manner on the sidewall made of an insulating film using a patterned photoresist; Forming a planarizing photoresist and processing the planarizing photoresist to expose at least a portion of the emitter electrode; and a second emitter configured to cover at least a region of the emitter electrode. A method for manufacturing a bipolar transistor, comprising at least a step of forming an electrode.