JP2989207B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a bipolar semiconductor device capable of high integration and high-speed operation, and to the semiconductor device.

<Prior Art> A conventional method of manufacturing a bipolar semiconductor device and a semiconductor device manufactured by this manufacturing method will be described with reference to FIG.

As shown in FIG. 3A, a P ⁺ polycrystalline silicon film 302 containing a P-type impurity such as boron atom is formed on an N ⁻ -type silicon substrate 301.
Is formed, and an oxide film 303 is further formed on the P ⁺ polycrystalline silicon film 302. After that, using photolithography technology and anisotropic etching technology, a groove having substantially vertical side walls is formed, and a part of the surface of the N ⁻ type silicon substrate 301 is exposed.

Next, as shown in FIG. 3B, a thin oxide film 308 is formed by thermally oxidizing the exposed N ⁻ type silicon substrate 301 and the side wall of the P ⁺ polycrystalline silicon film 302. Subsequently, boron atoms are implanted into the surface layer of the N ^- type silicon substrate 301 through the thin oxide film 308 by ion implantation, and then a heat treatment is performed in an inert atmosphere such as nitrogen gas to form an active base on the N ^- type silicon substrate. The layer 310 is formed. By the heat treatment at this time, P ⁺ diffusion layers 309 are formed by diffusion from P ⁺ polycrystalline silicon film 302. Further, after a thick oxide film (not shown) is attached and formed on the entire surface, the thick oxide film is anisotropically etched using an anisotropic etching technique to obtain sidewall oxide films 311 and 311. At this time, the thin oxide film 308 between the sidewall oxide films 311 and 311 is removed by anisotropic etching to expose a part of the active base layer 310.

Next, as shown in FIG. 3C, an N ⁺ polycrystalline silicon film 313 containing an N-type impurity such as arsenic is attached and formed on the entire surface. Then, after forming an etching mask (not shown) using a resist by using a photolithography technique, a part of the N ⁺ polysilicon film 313 is removed by using an etching technique to form an emitter electrode polysilicon 313a. Further, a heat treatment is performed in an inert atmosphere such as nitrogen gas to form an emitter diffusion layer 314 by diffusion from the emitter electrode polycrystalline silicon 313a in a part of the surface region of the active base layer 310. Then, the active region of the self-aligned reduced bipolar transistor having the double polysilicon structure is completed.

In the above description, only the structure of the active region of the transistor element has been described, but other parts constituting the entire semiconductor device, such as the structure of the isolation region and the metal wiring region, are omitted because they are not the main objects of the present invention. .

<Problem to be Solved by the Invention> However, in the above-described conventional method for manufacturing a semiconductor device, as shown in FIG. 3C, a part of the N ⁺ polycrystalline silicon (313) is removed by etching. In order to form an emitter electrode portion using emitter electrode polycrystalline silicon (313a), it is necessary to form an etching mask using a resist by using a photolithography technique. At this time, mask alignment is required for the active base layer (310) exposed between the side wall oxide films (311) and (311). Therefore, the pattern width of the emitter electrode polycrystalline silicon (313a) must be designed to have a large width including the mask alignment allowance as a matter of course. Therefore, the degree of integration of the element must be reduced, and the width of the base electrode must be increased. Therefore, a large parasitic capacitance and a large parasitic resistance are given to the base electrode, thereby hindering high-speed operation of the element.

Further, in the semiconductor device obtained by the above-mentioned conventional technology,
Using photolithography technology and etching technology
Since the emitter electrode portion is formed with the emitter electrode polycrystalline silicon (313a) on the P ⁺ polycrystalline silicon (302), a structure in which a large step is formed at the end of the emitter electrode polycrystalline silicon (313a) is obtained. The step causes a disconnection or a short circuit of the wiring in a subsequent metal wiring process, and causes a reduction in wiring reliability.

<Means for Solving the Problems> The present invention has been made to solve the above-mentioned problems, and a method of manufacturing a semiconductor device which is excellent in high integration, high speed, and excellent in wiring reliability, and a semiconductor device thereof. It is intended to provide a device.

That is, a first insulating film is formed on a main surface of a semiconductor substrate, a second insulating film is formed on the first insulating film, and a predetermined region of the second insulating film is selectively removed to form a substantially vertical side wall. For forming a plurality of island-shaped second insulating films having the following (1)
And (2) selectively forming a first sidewall insulating film on each side wall of each of the second insulating films; and using the second insulating film and each of the first sidewall insulating films as masks. Removing the first insulating film and exposing the semiconductor substrate (3); and forming a second sidewall insulating film provided on each side wall of the first insulating film and extending on the surface of the semiconductor substrate. And (4) forming an electrode layer that fills a gap between the first sidewall insulating films or a gap between the second insulating films and a gap between the second sidewall insulating films. )
And a step (6) of flattening the surface of the electrode layer to substantially the same height as the second insulating film.

Furthermore, a first conductivity type semiconductor substrate is used as the semiconductor substrate, and a first polycrystalline silicon film containing a second conductivity type impurity is formed on a main surface of the semiconductor substrate. Next, the first insulating film is formed on the first polycrystalline silicon film. The first insulating film is formed by sequentially stacking a first oxide film and a first nitride film. Further, a second insulating film is formed on the first insulating film. The second insulating film is formed by sequentially stacking a second oxide film and a second nitride film. Next, a predetermined region of the second insulating film is removed to obtain a substantially vertical side wall. Then, the first side wall insulating film is formed in contact with the side wall of the second insulating film and extending on the first insulating film. Next, the first nitride film between the first sidewall insulating films is removed to expose the first oxide film. Further, the exposed first oxide film and the first polycrystalline silicon film thereunder are removed to form substantially vertical side walls, and the semiconductor substrate is exposed. Subsequently, a third oxide film is formed on the exposed surface of the semiconductor substrate and on the side wall of each first polycrystalline silicon film. Then, the second side wall insulating film is formed on the third side of the first polycrystalline silicon film.
It is formed in contact with the oxide film and extending to the third oxide film on the semiconductor substrate side. Next, the third oxide film in the gap between the second sidewall insulating films is removed to expose the semiconductor substrate. Further, the second nitride film, the first sidewall insulating film, and the first nitride film immediately below the first sidewall insulating film are removed. Then, the electrode layer is connected to the gap between the first sidewall insulating films or the gap between the first insulating films and to the second
It is buried in the gap between the sidewall insulating films. As this electrode layer, a second polycrystalline silicon film containing impurities of the first conductivity type is used. Further, the electrode layer is flattened to substantially the same height as the surface of the second insulating film.

In the semiconductor device manufactured by the above-described manufacturing method, the gap between the second sidewall insulating films, the gap between the first nitride films, and the gap between the second oxide films are filled and the second oxide film is formed. An electrode layer flattened to substantially the same height with respect to the surface is formed.

<Operation> The method of manufacturing a semiconductor device according to the above-described method first includes
The width of the gap space between the insulating films is defined, and then the width of the gap space between the first insulating films is defined by the first sidewall insulating film formed on the side wall of each second insulating film. The width of the active base layer is defined by each second side wall insulating film formed on the side wall of the insulating film, and the electrode layer is embedded in each gap space, so that the alignment between the active base layer and the electrode layer is self-aligned. Done in Therefore, the necessity of mask alignment is eliminated by eliminating the photolithography technique when forming the electrode layer on the active base layer. Therefore, the width of the electrode layer is reduced by excluding the margin for mask alignment from the width of the electrode layer. In addition, the obstruction is eliminated by the electrode layer generated when the metal electrode is drawn from the base electrode of the first polycrystalline silicon film, and the width of the base electrode is reduced.

Further, the electrode layer is flattened to substantially the same height as the surface of the second insulating layer, so that a step larger than a region where the metal electrode is formed is eliminated. Therefore, the reliability of the wiring is ensured.

<Example> An example of the present invention will be described with reference to FIGS. Also, the numerical values used in the following description are examples, and it is obvious that the numerical values are not limited to these numerical conditions.

As shown in FIG. 1 (1), the specific resistance is 0.1 to 1.0 Ω-cm.
N ^- type (first conductivity type) silicon substrate (semiconductor substrate) 101
A P ⁺ polycrystalline silicon (first polycrystalline silicon containing a second conductivity type impurity) 102 having a thickness of 5000 ° is formed on the surface of the substrate. Next, a first insulating film 121 is formed by sequentially stacking a first oxide film 103 having a thickness of 2000 と and a first nitride film 104 having a thickness of 1000 CVD by using a CVD technique. In addition, the thickness is 5000mm using CVD technology.
The second oxide film 105 and the second nitride film 106 having a thickness of 2000 積 層 are sequentially laminated to form a second insulating film 122. Next, using a photolithography technique, a resist pattern (not shown)
Is formed, the second oxide films 105a (105) and 105b (105) and the second nitride films 106a (106) and 106b having substantially vertical side walls are formed by anisotropic etching using the resist pattern as an etching mask. (106) is obtained. Then, the structure shown in FIG. 1 (1) is obtained.

Next, after forming a nitride film 107 having a thickness of 7000 ° on the entire surface, the nitride film 107 is etched back by an anisotropic etching technique to form sidewall nitride films (first sidewall insulating films) 107a (107) and 107b (107). The second oxide films 105a and 105b and the second nitride films 106a and 106b are formed on respective sidewall portions. At this time, the first nitride film 104 in the gap between the sidewall nitride film 107a and the sidewall nitride film 107b is also removed by etching, exposing the first oxide film 103 in the gap.
Also, the upper portion of the remaining second nitride film 106 is also removed by the above-mentioned etching, and the thickness is from 2000 to 1000.
Thinner. Then, the structure shown in FIG. 1 (2) is obtained.

Next, the sidewall nitride films 107a, 107b and the second nitride films 106a,
Using 106b as a mask, the first oxide film 103 having substantially vertical side walls is etched by anisotropic etching technology.
P ⁺ polycrystalline silicon 102a and 102b having substantially vertical side walls as with a and 103b are obtained. At the same time, the N ^- type silicon substrate 101 is exposed. Then, the structure shown in FIG. 1 (3) is obtained.

Subsequently, thermal oxidation is performed at 900 ° C. for 30 minutes in a dry oxygen atmosphere, and a thin oxide film of 200 ° C. is formed on the exposed side walls of the P ⁺ polycrystalline silicon 102a and 102b and the exposed N ⁻ type silicon substrate 101. A tri-oxide film 108 is generated. Further, a P-type impurity composed of boron atoms or a compound thereof is introduced into the surface layer of the N ^- type silicon substrate 101 through the thin oxide film 108 at a dose of 1 × 10 ¹⁴ atms / cm ² by ion implantation. Next, heat treatment is performed at 900 ° C. for 30 minutes in an inert atmosphere such as nitrogen gas to diffuse impurities in the P ⁺ polycrystalline silicon 102 into the surface layer portion of the N ⁻ type silicon substrate 101, thereby forming a P ⁺ diffusion layer 109a. to form a 109b, the active base layer 110 that extends between the P ⁺ diffusion layer 109a and the P ⁺ diffusion layer 109b. Next, a CVD oxide film 11 with a thickness of 7000 mm
1 is adhered and generated on the entire surface, and then etched back by anisotropic etching technology to form a sidewall oxide film (second sidewall insulating film).
111a and 111b are formed. At the same time, each sidewall oxide film 111a,
The thin oxide film 108 in the gap between the sidewall oxide films 111b is removed by etching to expose a part of the active base layer 110. Then, the structure shown in FIG. 1 (4) is obtained.

 Further, the thin oxide film 108 may not be formed.

Next, an N ⁺ polycrystalline silicon film (second polycrystalline silicon film) 112 containing an N-type impurity (first conductivity type impurity) such as arsenic is formed on the entire surface and has a thickness of 1.0 μm. To 1.5 μm. Then, the structure shown in FIG. 1 (5) is obtained.

Before the N ⁺ polycrystalline silicon film 112 is formed on the entire surface, the second nitride films 106a and 106b and the first sidewall nitride films 107a and 107b are formed.
7b and the first nitride films 104a and 104b in the region immediately below the first sidewall nitride films 107a and 107b may be removed.

Next, after a resist (not shown) having a thickness of 2 to 3 μm is spin-coated on the entire surface to flatten the surface, N ⁺
Etch-back is performed under a polycrystalline silicon resist uniform etching condition to expose the second nitride films 106a and 106b and to make the emitter electrode polycrystalline silicon having substantially the same plane as each surface of the exposed second nitride films 106a and 106b ( (Electrode layer) 113 is obtained. Further, heat treatment is performed to diffuse the N-type impurities in the emitter electrode polycrystalline silicon 113 into the surface layer of the active base layer 110 to obtain the emitter diffusion layer 114. And Fig. 1 (6)
The structure shown in FIG.

Further, the emitter diffusion layer 114 may be formed by a thermal diffusion process before the above-described resist application.

Therefore, the width L-1 of the polysilicon
Is defined by the distance between the first sidewall nitride film 107a and the first sidewall nitride film 107b or the distance between the second oxide film 105a and the second oxide film 105b. This eliminates the need for mask alignment. Therefore, the emitter electrode polycrystalline silicon
The width L-1 of the emitter electrode polycrystalline silicon 113 is designed to be smaller than the width L-1 of the mask 113 so as to exclude the margin for mask alignment.

The width L-1 of the emitter electrode polycrystalline silicon 113 is designed to be small, so that when connecting a metal base electrode (not shown) to each of the P ⁺ polycrystalline silicon layers 102a and 102b serving as base electrodes, the emitter electrode Since the polycrystalline silicon 113 does not interfere, the width of each of the P ⁺ polycrystalline silicon layers 102a and 102b is designed to be short.

A semiconductor device manufactured by the above manufacturing method will be described with reference to FIG.

In the semiconductor device 1 shown in FIG. 2, the second nitride film 106, the first sidewall nitride film 107, and the first nitride film in the region immediately below the first sidewall nitride film in FIG. It is manufactured by removing the film 104.

The semiconductor device 1 includes a plurality of P ⁺ polycrystalline silicon films (including a second conductivity type impurity) forming a base electrode on a main surface of an N ⁻ type (first conductivity type) silicon substrate (semiconductor substrate) 101. First polycrystalline silicon films) 102a and 102b are selectively formed.

First oxide films 103a and 103b are respectively formed on the P ⁺ polycrystalline silicon films 102a and 102b. Also, each side wall of each P ⁺ polycrystalline silicon film 102a, 102b and the silicon substrate 1 on each side wall side
On top of 01, thin oxide films (third oxide films) 108a and 108b are formed so as to be connected to the respective first oxide films 103a and 103b.

Further, the second side wall oxide film 1 is in contact with each of the thin oxide films 108a and 108b.
11a and 111b are formed respectively. In the above-described manufacturing method, when the thin oxide films 108a and 108b are not formed, each of the second sidewall oxide films 111a and 111b becomes the first oxide film 103a and 103b.
Each P ⁺ polycrystalline silicon film 102a with connecting to each P ⁺ polycrystalline silicon film 102a in contact with 102b, exposed between the 102b, are provided extending on the silicon substrate 101.

A first nitride film 104a is formed on the remaining first oxide films 103a and 103b except for the vicinity of the second sidewall oxide films 111a and 111b.
104b and the second oxide films 105a, 105b are formed by sequentially laminating them, respectively.

Further, N-type impurities (in the gap between the first nitride films 104a and 104b, the gap between the second oxide films 105a and 105b, and the gap between the second sidewall nitride films 111a and 111b) are formed. First
An N ⁺ polycrystalline silicon film (second polycrystalline silicon film) (112) containing a conductive impurity) is buried to form an emitter electrode polycrystalline silicon 113 (electrode layer). The height of the surface of the emitter electrode polycrystalline silicon 113 is formed to be substantially the same as the height of the upper surface of each of the second oxide films 105a and 105b.

Therefore, the surface of the semiconductor device 1 described above is substantially flattened, so that a large step in the wiring region is eliminated, and the wiring reliability is improved.

<Effect of the Invention> As described above in detail, according to the present invention, in the step of forming the emitter electrode polycrystalline silicon (electrode layer),
Since the width of the emitter electrode polycrystalline silicon is determined by the side wall of the second oxide film (second insulating film) or the first side wall nitride film (first side wall insulating film) formed in a self-aligned manner with respect to the active base layer 110. N ⁺ polycrystalline silicon film (second polycrystalline silicon film)
Since it is not necessary to use photolithography technology when obtaining polycrystalline silicon for the emitter electrode, mask alignment is naturally unnecessary. Therefore, since the mask alignment allowance can be excluded from the width of the emitter electrode polycrystalline silicon, the width of the emitter electrode polycrystalline silicon can be significantly reduced.

Further, since the width of the polysilicon of the emitter electrode can be reduced, the polysilicon of the emitter electrode does not hinder the connection of the metal electrode to the P ⁺ polysilicon layer serving as the base electrode. Therefore, the width of P ⁺ polycrystalline silicon can also be reduced.

Therefore, the degree of integration of the element can be increased, and the parasitic capacitance and the parasitic resistance generated at the base electrode can be reduced.

Further, since the surface of the emitter electrode polycrystalline silicon is formed to be substantially the same height as the surface of the second oxide film or the first nitride film and flattened, the step at the end of the emitter electrode polycrystalline silicon is largely eliminated. it can. Therefore, the step coverage of the metal wiring can be improved, and the wiring reliability can be significantly improved.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a method of manufacturing a semiconductor device according to an embodiment, FIG. 2 is a sectional view of the semiconductor device of the embodiment, and FIG. 3 is an explanatory view of a method of manufacturing a conventional semiconductor device. 1. Semiconductor device, 101 N ^- type (first conductivity type) silicon substrate (semiconductor substrate), 102, 102a, 102b P ⁺ polycrystalline silicon film (first polycrystal containing impurity of second conductivity type) 103, 103a, 103b ... first oxide film, 104, 104a, 104b ... first nitride film, 105, 105a, 105b ... second oxide film, 106, 106a, 106b ... second nitride film, 107, 107a , 107b... Sidewall nitride film (first sidewall insulating film), 108, 108a, 108b... Thin oxide film (third oxide film), 111, 111a, 111b. ... N ⁺ polycrystalline silicon film (second polycrystalline silicon film), 113... Emitter electrode polycrystalline silicon (electrode layer), 121... First insulating film, 122.

Claims (3)

(57) [Claims] A first insulating film formed on a main surface of a semiconductor substrate; a second insulating film formed on the first insulating film; and a predetermined region of the second insulating film is selectively removed. (1) forming a plurality of island-shaped second insulating films having substantially vertical sidewalls, and selectively forming a first sidewall insulating film on each sidewall of each of the second insulating films. (2) removing the first insulating film using the respective second insulating films and the respective first sidewall insulating films as masks and exposing the semiconductor substrate; and (3) the first insulating film. Forming a second sidewall insulating film provided on each side wall of the semiconductor substrate and extending on the surface of the semiconductor substrate; and (4) at least a gap between the second sidewall insulating films and the first insulating film. (5) forming an electrode layer that fills the gap and the gap between the second insulating films; A step (6) of flattening the surface of the electrode layer to substantially the same height as the second insulating film, wherein the steps (1) to (6) are sequentially performed. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein a first conductive type semiconductor substrate is used as the semiconductor substrate, and a first conductive type semiconductor includes a second conductive type impurity on a main surface of the semiconductor substrate. Forming a silicon film, forming a first insulating film in which a first oxide film and a first nitride film are sequentially stacked on the first polycrystalline silicon film, and further forming a second oxide film and a second nitride film in order; Forming a plurality of island-shaped second insulating films having substantially vertical side walls by removing a predetermined region of the second insulating film after forming the laminated second insulating film; Forming a first sidewall insulating film provided on a sidewall of the film and extending on a first nitride film of the first insulating film;
Removing the first nitride film in a gap between the first sidewall insulating films to expose the first oxide film; the exposed first oxide film and the first polycrystalline silicon film below the exposed first oxide film Forming a substantially vertical side wall by exposing the semiconductor substrate under the removed first polycrystalline silicon film; and removing each side wall of the first polycrystalline silicon film and a surface of the exposed semiconductor substrate. And forming a second sidewall insulating film in contact with the third oxide film on the first polycrystalline silicon film side and extending to the third oxide film on the semiconductor substrate side. Removing the third oxide film in the gap between the second sidewall insulating films to expose the surface of the semiconductor substrate; and an electrode layer formed of a second polycrystalline silicon film containing impurities of a first conductivity type. And at least a gap between the first insulating films. Filling the gaps between the second insulating films and the gaps between the second sidewall insulating films; and flattening the surface of the electrode layer to approximately the same height as the surface of the second oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the steps of: 3. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1 or 2, further comprising a semiconductor substrate of a first conductivity type and an impurity of a second conductivity type. A plurality of first polycrystalline silicon films selectively formed on a main surface of the semiconductor substrate; a first oxide film formed on each of the first polycrystalline silicon films; A third oxide film provided on the side wall of the polycrystalline silicon film and extending on the main surface of the semiconductor substrate and connected to each of the first oxide films; and a second oxide film provided in contact with each of the third oxide films. A sidewall insulating film; a first nitride film formed on each of the first oxide films except for a portion near each of the second sidewall insulating films; and a second oxide film formed on each of the first nitride films. And a gap portion between the first insulating films, the first insulating film containing impurities of the first conductivity type. A second polycrystal buried in a gap between the second insulating films and a gap between the second sidewall insulating films, and planarized to substantially the same height as the surface of the second insulating film; A semiconductor device comprising an electrode layer formed of a silicon film.